TI1 BQ2050SN-D119TR Lithium ion power gaugeâ ¢ ic Datasheet

Not Recommended For New Designs
bq2050
Lithium Ion Power Gauge™ IC
Features
General Description
➤ Conservative and repeatable
measurement of available capacity in Lithium Ion rechargeable
batteries
The bq2050 Lithium Ion Power
Gauge™ IC is intended for batterypack or in-system installation to
maintain an accurate record of
available battery capacity. The IC
monitors a voltage drop across a
sense resistor connected in series
between the negative battery termina l a n d g r ou n d t o d e t e r m i n e
charge and discharge activity of
the battery. Compensations for battery temperature and rate of charge
or discharge are applied to the
charge, discharge, and self-discharge
calculations to provide available capacity information across a wide
range of operating conditions. Battery capacity is automatically recalibrated, or “learned,” in the course of
a discharge cycle from full to empty.
➤ Designed for battery pack integration
-
120µA typical operating
current
-
Small size enables implementations in as little as 1 2
square inch of PCB
➤ Integrate within a system or as a
stand-alone device
-
Display capacity via singlewire serial communication
port or direct drive of LEDs
➤ Measurements compensated for
current and temperature
➤ Self-discharge compensation using internal temperature sensor
supports a simple single-line bidirectional serial link to an external
processor (common ground). The
bq2050 outputs battery information
in response to external commands
over the serial link.
The bq2050 may operate directly
from one cell (VBAT > 3V). With the
REF output and an external transistor, a simple, inexpensive regulator
can be built for systems with more
than one series cell.
Internal registers include available
capacity, temperature, scaled available energy, battery ID, battery
status, and programming pin settings. To support subassembly testing, the outputs may also be controlled. The external processor may
also overwrite some of the bq2050
power gauge data registers.
Nominal available capacity may be
directly indicated using a fivesegment LED display. These segments are used to graphically indicate available capacity. The bq2050
➤ 16-pin narrow SOIC
Pin Connections
Pin Names
LCOM
1
16
VCC
SEG1/PROG1
2
15
REF
SEG2/PROG2
3
14
N/C
SEG3/PROG3
4
13
DQ
SEG4/PROG4
5
12
RBI
SEG5/PROG5
6
11
SB
PROG6
7
10
DISP
VSS
8
9
SR
LCOM
LED common output
REF
Voltage reference output
SEG1/PROG1
LED segment 1/
program 1 input
N/C
No connect
DQ
SEG2/PROG2
LED segment 2/
program 2 input
Serial communications
input/output
RBI
Register backup input
SEG3/PROG3
LED segment 3/
program 3 input
SB
Battery sense input
DISP
Display control input
SEG4/PROG4
LED segment 4/
program 4 input
SR
Sense resistor input
SEG5/PROG5
LED segment 5/
program 5 input
VCC
3.0–6.5V
Program 6 input
VSS
System ground
16-Pin Narrow SOIC
PN205001.eps
PROG6
9/96 C
1
Not Recommended For New Designs
bq2050
SR
Pin Descriptions
LCOM
The voltage drop (VSR) across the sense resistor RS is monitored and integrated over
time to interpret charge and discharge activity. The SR input is tied between the negative terminal of the battery and the sense resistor. VSR < VSS indicates discharge, and VSR
> VSS indicates charge. The effective voltage
drop, VSRO, as seen by the bq2050 is VSR +
VOS .
LED common output
Open-drain output switches VCC to source
current for the LEDs. The switch is off during initialization to allow reading of the soft
pull-up or pull-down program resistors.
LCOM is also high impedance when the display is off.
SEG1–
SEG5
LED display segment outputs (dual function with PROG1–PROG6)
DISP
Programmed full count selection inputs
(dual function with SEG1–SEG2)
These three-level input pins define the programmed full count (PFC) thresholds described in Table 2.
PROG3–
PROG4
SB
RBI
Self-discharge rate selection (dual function with SEG5)
DQ
Capacity initialization selection
Serial I/O pin
This is an open-drain bidirectional pin.
This three-level pin defines the battery state
of charge at reset as shown in Table 1.
N/C
Register backup input
This pin is used to provide backup potential to
the bq2050 registers during periods when
VCC ≤ 3V. A storage capacitor or a battery
can be connected to RBI.
This three-level input pin defines the
selfdischarge and battery compensation factors as shown in Table 1.
PROG6
Secondary battery input
This input monitors the battery cell voltage
potential through a high-impedance resistive divider network for end-of-discharge
voltage (EDV) thresholds, and battery removed.
Power gauge rate selection inputs (dual
function with SEG3–SEG4)
These three-level input pins define the scale
factor described in Table 2.
PROG5
Display control input
DISP high disables the LED display. DISP
tied to VCC allows PROGX to connect directly
to VCC or VSS instead of through a pull-up or
pull-down resistor. DISP floating allows the
LED display to be active during charge.
DISP low activates the display. See Table 1.
Each output may activate an LED to sink
the current sourced from LCOM.
PROG1–
PROG2
Sense resistor input
REF
No connect
Voltage reference output for regulator
REF provides a voltage reference output for
an optional micro-regulator.
2
VCC
Supply voltage input
VSS
Ground
Not Recommended For New Designs
bq2050
Functional Description
scaled available energy measurement is corrected for
the environmental and operating conditions.
General Operation
Figure 1 shows a typical battery pack application of the
bq2050 using the LED display capability as a chargestate indicator. The bq2050 is configured to display capacity in relative display mode. The relative display
mode uses the last measured discharge capacity of the
battery as the battery “full” reference. A push-button
display feature is available for momentarily enabling
the LED display.
The bq2050 determines battery capacity by monitoring the amount of current input to or removed from a
rechargeable battery. The bq2050 measures discharge and charge currents, measures battery voltage, estimates self-discharge, monitors the battery
for low battery voltage thresholds, and compensates
for temperature and charge/discharge rates. The current measurement is made by monitoring the voltage
across a small-value series sense resistor between the
negative battery terminal and ground. The estimate of
scaled available energy is made using the remaining
average battery voltage during the discharge cycle
and the remaining nominal available charge. The
The bq2050 monitors the charge and discharge currents
as a voltage across a sense resistor (see RS in Figure 1).
A filter between the negative battery terminal and the
SR pin may be required if the rate of change of the battery current is too great.
R1
1M
bq2050
Power Gauge IC
Q1
ZVNL110A
REF
C1
0.1 F
LCOM
SEG1/PROG1
VCC
VCC
SB
VCC
SEG2/PROG2
C2
RB2
SEG3/PROG3
DISP
SEG4/PROG4
SR
SEG5/PROG5
PROG6
RB1
RS
VSS
RBI
PSTAT
DQ
Charger
Indicates optional.
Load
Directly connect to VCC across 1 cell (VBAT > 3V).
Otherwise, R1, C1, and Q1 are needed for regulation of > 1 cell.
Programming resistors (6 max.) and ESD-protection diodes are not shown.
R-C on SR may be required, application-specific.
A series Zener may be used to limit discharge current at low voltages
in designs using 3 or more cells.
FG205001.eps
Figure 1. Battery Pack Application Diagram—LED Display
3
Not Recommended For New Designs
bq2050
Voltage Thresholds
In conjunction with monitoring VSR for charge/discharge
currents, the bq2050 monitors the battery potential
through the SB pin. The voltage is determined through
a resistor-divider network per the following equation:
RB1
= 2N − 1
RB2
where N is the number of cells, RB1 is connected to the
positive battery terminal, and RB2 is connected to the
negative battery terminal. The single-cell battery voltage is monitored for the end-of-discharge voltage (EDV).
EDV threshold levels are used to determine when the
battery has reached an “empty” state.
Two EDV thresholds for the bq2050 are programmable
with the default values fixed at:
EDV1 (early warning) = 1.52V
EDVF (empty) = 1.47V
If VSB is below either of the two EDV thresholds, the associated flag is latched and remains latched, independent of VSB, until the next valid charge. The VSB value is
also available over the serial port.
During discharge and charge, the bq2050 monitors VSR
for various thresholds used to compensate the charge
and discharge rates. Refer to the count compensation
section for details. EDV monitoring is disabled if the
discharge rate is greater than 2C (typical) and resumes
1 second after the rate falls below 2C.
2
TMP (hex)
Temperature Range
0x
< -30°C
1x
-30°C to -20°C
2x
-20°C to -10°C
3x
-10°C to 0°C
4x
0°C to 10°C
5x
10°C to 20°C
6x
20°C to 30°C
7x
30°C to 40°C
8x
40°C to 50°C
9x
50°C to 60°C
Ax
60°C to 70°C
Bx
70°C to 80°C
Cx
> 80°C
Layout Considerations
RBI Input
The bq2050 measures the voltage differential between
the SR and VSS pins. VOS (the offset voltage at the SR
pin) is greatly affected by PC board layout. For optimal
results, the PC board layout should follow the strict rule
of a single-point ground return. Sharing high-current
ground with small signal ground causes undesirable
noise on the small signal nodes. Additionally:
The RBI input pin is intended to be used with a storage capacitor or external supply to provide backup potential to the
internal bq2050 registers when VCC drops below 3.0V. VCC
is output on RBI when VCC is above 3.0V. A diode is required to isolate the external supply.
Reset
n
The bq2050 can be reset either by removing VCC and
grounding the RBI pin for 15 seconds or by writing 0x80
to register 0x39.
Temperature
n
The bq2050 internally determines the temperature in
10°C steps centered from approximately -35°C to +85°C.
The temperature steps are used to adapt charge and discharge rate compensations, self-discharge counting, and
available charge display translation. The temperature
range is available over the serial port in 10°C increments as shown in the following table:
n
4
The capacitors (C1 and C2) should be placed as
close as possible to the VCC and SB pins,
respectively, and their paths to VSS should be as
short as possible. A high-quality ceramic capacitor
of 0.1µf is recommended for VCC.
The sense resistor capacitor should be placed as close
as possible to the SR pin.
The sense resistor (RS) should be as close as possible to
the bq2050.
Not Recommended For New Designs
bq2050
The battery's initial capacity is equal to the Programmed Full Count (PFC) shown in Table 2. Until
LMD is updated, NAC counts up to but not beyond this
threshold during subsequent charges. This approach allows the gas gauge to be charger-independent and compatible with any type of charge regime.
Gas Gauge Operation
The operational overview diagram in Figure 2 illustrates
the operation of the bq2050. The bq2050 accumulates a
measure of charge and discharge currents, as well as an
estimation of self-discharge. Charge and discharge currents are temperature and rate compensated, whereas
self-discharge is only temperature compensated.
1.
Last Measured Discharge (LMD) or learned
battery capacity:
The main counter, Nominal Available Capacity (NAC),
represents the available battery capacity at any given
time. Battery charging increments the NAC register,
while battery discharging and self-discharge decrement
the NAC register and increment the DCR (Discharge
Count Register).
LMD is the last measured discharge capacity of the
battery. On initialization (application of VCC or battery replacement), LMD = PFC. During subsequent
discharges, the LMD is updated with the latest
measured capacity in the Discharge Count Register
(DCR) representing a discharge from full to below
EDV1. A qualified discharge is necessary for a capacity transfer from the DCR to the LMD register. The
LMD also serves as the 100% reference threshold
used by the relative display mode.
The Discharge Count Register (DCR) is used to update
the Last Measured Discharge (LMD) register only if a
complete battery discharge from full to empty occurs
without any partial battery charges. Therefore, the
bq2050 adapts its capacity determination based on the
actual conditions of discharge.
Inputs
Charge
Current
Discharge
Current
Self-Discharge
Timer
Rate and
Temperature
Compensation
Rate and
Temperature
Compensation
Temperature
Compensation
+
Main Counters
and Capacity
Reference (LMD)
+
-
Nominal
Available
Charge
(NAC)
Last
Discharge
Count
Qualified Register
(DCR)
Transfer
Measured
< Discharged
(LMD)
Temperature Step,
Other Data
Temperature
Translation
Outputs
Compensated
Available Charge
LED Display, etc.
Serial
Port
Figure 2. Operational Overview
5
+
FG205002.eps
Not Recommended For New Designs
bq2050
2.
Programmed Full Count (PFC) or initial battery capacity:
Example: Selecting a PFC Value
Given:
The initial LMD and gas gauge rate values are programmed by using PROG1–PROG4. The bq2050 is
configured for a given application by selecting a
PFC value from Table 2. The correct PFC may be
determined by multiplying the rated battery capacity in mAh by the sense resistor value:
Sense resistor = 0.05Ω
Number of cells = 2
Capacity = 1000mAh, Li-Ion battery, coke-anode
Current range = 50mA to 1A
Relative display mode
Serial port only
Self-discharge = NAC 512 per day @ 25°C
Voltage drop over sense resistor = 2.5mV to 50mV
Nominal discharge voltage = 3.6V
Battery capacity (mAh) * sense resistor (Ω) =
PFC (mVh)
Selecting a PFC slightly less than the rated capacity provides a conservative capacity reference until
the bq2050 “learns” a new capacity reference.
Therefore:
1000mAh * 0.05Ω = 50mVh
Table 1. bq2050 Programming
Pin
Connection
PROG5 Compensation/
Self-Discharge
PROG6
NAC on Reset
DISP
Display State
H
Table 4/Disabled
PFC
LEDs disabled
512
0
LEDs on when charging
512
0
LEDs on for 4 sec.
Z
Table 4/
NAC
L
Table 3/
NAC
Note:
PROG5 and PROG6 states are independent.
Table 2. bq2050 Programmed Full Count mVh Selections
PROGx
1
2
Programmed
Full
Count
(PFC)
PROG4 = L
PROG3 = H
PROG4 = Z
PROG3 = Z PROG3 = L PROG3 = H PROG3 = Z PROG3 = L
Units
-
-
-
SCALE =
1/80
H
H
49152
614
307
154
76.8
38.4
19.2
mVh
H
Z
45056
563
282
141
70.4
35.2
17.6
mVh
H
L
40960
512
256
128
64.0
32.0
16.0
mVh
Z
H
36864
461
230
115
57.6
28.8
14.4
mVh
Z
Z
33792
422
211
106
53.0
26.4
13.2
mVh
Z
L
30720
384
192
96.0
48.0
24.0
12.0
mVh
L
H
27648
346
173
86.4
43.2
21.6
10.8
mVh
L
Z
25600
320
160
80.0
40.0
20.0
10.0
mVh
L
L
22528
282
141
70.4
35.2
17.6
8.8
mVh
90
45
22.5
11.25
5.6
2.8
mV
VSR equivalent to 2
counts/sec. (nom.)
SCALE =
1/160
SCALE =
1/320
SCALE =
1/640
SCALE =
1/1280
SCALE =
1/2560
mVh/
count
6
Not Recommended For New Designs
bq2050
E(mWh) = (SAEH * 256 + SAEL) *
Select:
2.4 ∗ SCALE ∗ (R B1 + R B2 )
R S ∗ R B2
PFC = 30720 counts or 48mVh
PROG1 = float
PROG2 = low
PROG3 = high
PROG4 = float
PROG5 = float
PROG6 = float
where RB1, RB2 and RS are resistor values in ohms.
SCALE is the selected scale from Table 2. SAEH
and SAEL are digital values read via DQ.
6. Compensated Available Capacity (CAC)
The initial full battery capacity is 48mVh (960mAh)
until the bq2050 “learns” a new capacity with a
qualified discharge from full to EDV1.
3.
CAC counts similar to NAC, but contains the available capacity compensated for discharge rate and
temperature.
Nominal Available Capacity (NAC):
Charge Counting
NAC counts up during charge to a maximum value
of LMD and down during discharge and self-discharge to 0. NAC is reset to 0 on initialization and on
the first valid charge following discharge to EDV1. To
prevent overstatement of charge during periods of
overcharge, NAC stops incrementing when NAC =
LMD.
4.
Charge activity is detected based on a positive voltage
on the VSR input. If charge activity is detected, the
bq2050 increments NAC at a rate proportional to VSR and,
if enabled, activates an LED display. Charge actions increment the NAC after compensation for temperature.
The bq2050 determines charge activity sustained at a
continuous rate equivalent to VSRO > VSRQ. A valid
charge equates to sustained charge activity greater
than 256 NAC counts. Once a valid charge is detected,
charge counting continues until VSRO (VSR + VOS) falls
below VSRQ. VSRQ is 210µV, and is described in the
Digital Magnitude Filter section.
Discharge Count Register (DCR):
The DCR counts up during discharge independent of
NAC and could continue increasing after NAC has
decremented to 0. Prior to NAC = 0 (empty battery),
both discharge and self-discharge increment the
DCR. After NAC = 0, only discharge increments the
DCR. The DCR resets to 0 when NAC = LMD. The
DCR does not roll over but stops counting when it
reaches FFFFh.
Discharge Counting
Discharge activity is detected based on a negative voltage
on the VSR input. All discharge counts where VSRO < VSRD
cause the NAC register to decrement and the DCR to
increment. VSRD is -200µV, and is described in the
Digital Magnitude Filter section.
The DCR value becomes the new LMD value on the
first charge after a valid discharge to VEDV1 if:
No valid charge initiations (charges greater than
256 NAC counts, where VSRO > VSRQ) occurred during the period between NAC = LMD and EDV1 detected.
Self-Discharge Estimation
The bq2050 continuously decrements NAC and increments
DCR for self-discharge based on time and temperature. The
self-discharge count rate is programmed to be a nominal
1
512 * NAC per day or disabled. This is the rate for a battery whose temperature is between 20°–30°C. The NAC
register cannot be decremented below 0.
The self-discharge count is not more than 4096
counts (8% to 18% of PFC, specific percentage
threshold determined by PFC).
The temperature is ≥ 0°C when the EDV1 level is
reached during discharge.
Count Compensations
The valid discharge flag (VDQ) indicates whether
the present discharge is valid for LMD update.
5.
Discharge Compensation
Scaled Available Energy (SAE):
Corrections for the rate of discharge, temperature, and anode
type are made by adjusting an internal compensation factor.
This factor is based on the measured rate of discharge of the
battery. Tables 3A and 3B outline the correction factor typically used for graphite anode Li-Ion batteries, and Tables 4A
and 4B outline the factors typically used for coke anode
Li-Ion batteries. The compensation factor is applied to
CAC and is based on discharge rate and temperature.
SAE is useful in determining the available energy
within the battery, and may provide a more useful
capacity reference in battery chemistries with
sloped voltage profiles during discharge. SAE may
be converted to a mWh value using the following
formula:
7
Not Recommended For New Designs
bq2050
Charge Compensation
Table 3A. Graphite Anode
The bq2050 applies the following temperature compensation to NAC during charge:
Approximate
Discharge Rate
Discharge
Compensation
Factor
Efficiency
< 0.5C
1.00
100%
≥ 0.5C
1.05
95%
Temperature
Temperature
Compensation
Factor
< 10°C
0.95
95%
≥ 10°C
1.00
100%
Efficiency
This compensation applies to both types of Li-Ion cells.
Table 3B. Graphite Anode
Self-Discharge Compensation
Temperature
Temperature
Compensation
Factor
Efficiency
≥ 10°C
1.00
100%
0°C to 10°C
1.10
90%
-10°C to 0°C
1.35
74%
≤ -10°C
2.50
40%
The self-discharge compensation is programmed for a
nominal rate of 1 512 * NAC per day. This is the rate for a
battery within the 20°C–30°C temperature range. This
rate varies across 8 ranges from < 10°C to > 70°C, changing with each higher temperature (approximately 10°C).
See Table 5 below:
Table 5. Self-Discharge Compensation
Typical Rate
Temperature Range
Table 4A. Coke Anode
Approximate
Discharge Rate
Discharge
Compensation
Factor
<0.5C
1.00
≥ 0.5C
PROG5 = Z or L
< 10°C
NAC
10–20°C
NAC
2048
1024
20–30°C
NAC
30–40°C
NAC
Efficiency
40–50°C
NAC
100%
50–60°C
NAC
86%
60–70°C
NAC
> 70°C
NAC
1.15
512
256
128
64
32
16
Self-discharge may be disabled by connecting PROG5 = H.
Table 4B. Coke Anode
Digital Magnitude Filter
Temperature
Temperature
Compensation
Factor
Efficiency
≥ 10°C
1.00
100%
0°C to 10°C
1.25
80%
-10°C to 0°C
2.00
50%
≤ -10°C
8.00
12%
The bq2050 has a digital filter to eliminate charge and discharge counting below a set threshold. The bq2050 setting
is 200µV for VSRD and 210µV for VSRQ.
8
Not Recommended For New Designs
bq2050
Table 6. bq2050 Current-Sensing Errors
Symbol
Parameter
Typical
INL
Integrated non-linearity
error
±2
INR
Integrated nonrepeatability error
±1
Maximum
Units
Notes
±4
%
Add 0.1% per °C above or below 25°C
and 1% per volt above or below 4.25V.
±2
%
Measurement repeatability given
similar operating conditions.
eight bits that have a maximum transmission rate of
333 bits/sec. The least-significant bit of a command or
data byte is transmitted first. The protocol is simple
enough that it can be implemented by most host processors using either polled or interrupt processing. Data
input from the bq2050 may be sampled using the pulsewidth capture timers available on some microcontrollers.
Error Summary
Capacity Inaccurate
The LMD is susceptible to error on initialization or if no
updates occur. On initialization, the LMD value includes the error between the programmed full capacity
and the actual capacity. This error is present until a
valid discharge occurs and LMD is updated (see the
DCR description on page 7). The other cause of LMD error is battery wear-out. As the battery ages, the measured capacity must be adjusted to account for changes in
actual battery capacity.
If a communication error occurs, e.g. tCYCB > 6ms, the
bq2050 should be sent a BREAK to reinitiate the serial
interface. A BREAK is detected when the DQ pin is
driven to a logic-low state for a time, tB or greater. The
DQ pin should then be returned to its normal readyhigh logic state for a time, tBR. The bq2050 is now ready
to receive a command from the host processor.
A Capacity Inaccurate counter (CPI) is maintained and
incremented each time a valid charge occurs (qualified
by NAC; see the CPI register description) and is reset
whenever LMD is updated from the DCR. The counter
does not wrap around but stops counting at 255. The capacity inaccurate flag (CI) is set if LMD has not been updated following 64 valid charges.
The return-to-one data bit frame consists of three distinct sections. The first section is used to start the
transmission by either the host or the bq2050 taking the
DQ pin to a logic-low state for a period, tSTRH,B. The
next section is the actual data transmission, where the
data should be valid by a period, tDSU, after the negative
edge used to start communication. The data should be
held for a period, tDV, to allow the host or bq2050 to
sample the data bit.
Current-Sensing Error
Table 5 illustrates the current-sensing error as a function of VSRO. A digital filter eliminates charge and discharge counts to the NAC register when VSRO is between
VSRQ and VSRD.
The final section is used to stop the transmission by returning the DQ pin to a logic-high state by at least a period, tSSU, after the negative edge used to start communication. The final logic-high state should be held until
a period, tSV, to allow time to ensure that the bit transmission was stopped properly. The timings for data and
break communication are given in the serial communication timing specification and illustration sections.
Communicating With the bq2050
The bq2050 includes a simple single-pin (DQ plus return) serial data interface. A host processor uses the interface to access various bq2050 registers. Battery characteristics may be easily monitored by adding a single
contact to the battery pack. The open-drain DQ pin on
the bq2050 should be pulled up by the host system, or may
be left floating if the serial interface is not used.
Communication with the bq2050 is always performed with
the least-significant bit being transmitted first. Figure 3
shows an example of a communication sequence to read
the bq2050 NAC register.
The interface uses a command-based protocol, where the
host processor sends a command byte to the bq2050.
The command directs the bq2050 to either store the next
eight bits of data received to a register specified by the
command byte or output the eight bits of data specified
by the command byte.
The communication protocol is asynchronous return-toone. Command and data bytes consist of a stream of
9
Not Recommended For New Designs
bq2050
Written by Host to bq2050
CMDR = 03h
LSB
MSB
Break 1 1 0 0 0 0 0 0
Received by Host to bq2050
NAC = 65h
LSB
MSB
1 0 1 0 011 0
DQ
TD205002.eps
Figure 3. Typical Communication With the bq2050
bq2050 Registers
Primary Status Flags Register (FLGS1)
The bq2050 command and status registers are listed in
Table 7 and described below.
The read-only FLGS1 register (address=01h) contains
the primary bq2050 flags.
Command Register (CMDR)
The charge status flag (CHGS) is asserted when a
valid charge rate is detected. Charge rate is deemed
valid when VSRO > VSRQ. A VSRO of less than VSRQ or
discharge activity clears CHGS.
The write-only CMDR register is accessed when eight
valid command bits have been received by the bq2050.
The CMDR register contains two fields:
n
W/R bit
n
Command address
The CHGS values are:
FLGS1 Bits
The W/R bit of the command register is used to select whether
the received command is for a read or a write function.
7
6
5
4
3
2
1
0
CHGS
-
-
-
-
-
-
-
Where CHGS is:
The W/R values are:
0
Either discharge activity detected or VSRO <
VSRQ
1
VSRO > VSRQ
CMDR Bits
7
6
5
4
3
2
1
0
W/R
-
-
-
-
-
-
-
The battery replaced flag (BRP) is asserted whenever
the bq2050 is reset either by application of VCC or by a
serial port command. BRP is reset when either a valid
charge action increments NAC to be equal to LMD, or a
valid charge action is detected after the EDV1 flag is asserted. BRP = 1 signifies that the device has been reset.
Where W/R is:
0
The bq2050 outputs the requested register contents specified by the address portion of CMDR.
1
The following eight bits should be written
to the register specified by the address portion of CMDR.
The BRP values are:
FLGS1 Bits
The lower seven-bit field of CMDR contains the address
portion of the register to be accessed. Attempts to write
to invalid addresses are ignored.
CMDR Bits
7
-
6
5
AD6 AD5
7
6
5
4
3
2
1
0
-
BRP
-
-
-
-
-
-
Where BRP is:
4
3
2
1
0
AD4
AD3
AD2
AD1
AD0
(LSB)
10
0
Battery is charged until NAC = LMD or discharged until the EDV1 flag is asserted
1
bq2050 is reset
Not Recommended For New Designs
bq2050
Table 7. bq2050 Command and Status Registers
Symbol
CMDR
Register Name
Command register
Primary status flags
FLGS1
register
TMP
Temperature register
Nominal available caNACH pacity high byte register
Nominal available
NACL capacity low byte
register
Battery
BATID identification
register
Last measured disLMD
charge register
Secondary status
FLGS2
flags register
Program pin pullPPD
down register
Program pin pull-up
PPU
register
Capacity
CPI
inaccurate count register
Battery voltage
VSB
register
End-of-discharge threshVTS
old select register
Compensated availCACH able capacity high byte
register
Compensated
CACL available capacity low
byte register
Scaled available
SAEH energy high byte register
Scaled available
SAEL
energy low byte register
RST
Reset register
Note:
n/u = not used
Loc. Read/
Control Field
(hex) Write 7(MSB)
6
AD6
00h Write W/R
5
AD5
4
AD4
3
AD3
2
AD2
1
AD1
0(LSB)
AD0
01h Read
CHGS
BRP
n/u
CI
VDQ
n/u
EDV1
EDVF
02h Read
TMP3
TMP2
TMP1
TMP0
GG3
GG2
GG1
GG0
03h
R/W NACH7 NACH6 NACH5 NACH4 NACH3 NACH2 NACH1 NACH0
17h Read NACL7 NACL6 NACL5 NACL4 NACL3 NACL2 NACL1 NACL0
04h
R/W BATID7 BATID6 BATID5 BATID4 BATID3 BATID2 BATID1 BATID0
05h
R/W
LMD7
LMD6
LMD5
LMD4
LMD3
LMD2
LMD1
LMD0
06h Read
n/u
DR2
DR1
DR0
n/u
n/u
n/u
OVLD
07h Read
n/u
n/u
PPD6
PPD5
PPD4
PPD3
PPD2
PPD1
08h Read
n/u
n/u
PPU6
PPU5
PPU4
PPU3
PPU2
PPU1
09h Read
CPI7
CPI6
CPI5
CPI4
CPI3
CPI2
CPI1
CPI0
0Bh Read
VSB7
VSB6
VSB5
VSB4
VSB3
VSB2
VSB1
VSB0
0Ch
VTS7
VTS6
VTS5
VTS4
VTS3
VTS2
VTS1
VTS0
R/W
0Dh Read CACH7 CACH6 CACH5 CACH4 CACH3 CACH2 CACH1 CACH0
0Eh Read CACL7
CACL6 CACL5 CACL4 CACL3 CACL2 CACL1 CACL0
0Fh Read SAEH7
SAEH6 SAEH5 SAEH4 SAEH3 SAEH2 SAEH1 SAEH0
10h Read SAEL7
SAEL6
39h Write
RST
0
11
SAEL5 SAEL4 SAEL3 SAEL2 SAEL1 SAEL0
0
0
0
0
0
0
Not Recommended For New Designs
bq2050
The EDV1 values are:
The capacity inaccurate flag (CI) is used to warn the
user that the battery has been charged a substantial
number of times since LMD has been updated. The CI
flag is asserted on the 64th charge after the last LMD
update or when the bq2050 is reset. The flag is cleared
after an LMD update.
FLGS1 Bits
7
6
5
4
3
2
1
0
-
-
-
-
-
-
EDV1
-
The CI values are:
Where EDV1 is:
FLGS1 Bits
7
6
5
4
3
2
1
0
-
-
-
CI
-
-
-
-
When LMD is updated with a valid full discharge
1
After the 64th valid charge action with no
LMD updates or the bq2050 is reset
n
n
1
VSB < VTS providing that the discharge rate is
< 2C
The EDVF values are:
The valid discharge flag (VDQ) is asserted when the
bq2050 is discharged from NAC=LMD. The flag remains
set until either LMD is updated or one of three actions
that can clear VDQ occurs:
n
Valid charge action detected, VSB ≥ VTS
The final end-of-discharge warning flag (EDVF) flag
is used to warn that battery power is at a failure condition. All segment drivers are turned off. The EDVF flag
is latched until a valid charge has been detected. The
EDVF threshold is set 50mV below the EDV1 threshold.
Where CI is:
0
0
FLGS1 Bits
The self-discharge count register (SDCR) has
exceeded the maximum acceptable value (4096
counts) for an LMD update.
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
EDVF
Where EDVF is:
A valid charge action sustained at VSRO > VSRQ for at
least 256 NAC counts.
0
Valid charge action detected, VSB ≥ (VTS 50mV)
1
VSB < (VTS - 50mV) providing the discharge
rate is < 2C
The EDV1 flag was set at a temperature below 0°C
The VDQ values are:
Temperature Register (TMP)
The read-only TMP register (address=02h) contains the
battery temperature.
FLGS1 Bits
7
6
5
4
3
2
1
0
-
-
-
-
VDQ
-
-
-
TMP Temperature Bits
7
Where VDQ is:
0
1
6
5
4
TMP4 TMP3 TMP2 TMP1
SDCR ≥ 4096, subsequent valid charge action detected, or EDV1 is asserted with the
temperature less than 0°C
3
2
1
0
-
-
-
-
The bq2050 contains an internal temperature sensor.
The temperature is used to set charge and discharge efficiency factors as well as to adjust the self-discharge coefficient. The temperature register contents may be
translated as shown in Table 7.
On first discharge after NAC = LMD
The first end-of-discharge warning flag (EDV1)
warns the user that the battery is almost empty. The
first segment pin, SEG1, is modulated at a 4Hz rate if
the display is enabled once EDV1 is asserted, which
should warn the user that loss of battery power is imminent. The EDV1 flag is latched until a valid charge has
been detected. The EDV1 threshold is externally controlled via the VTS register (see Voltage Threshold Register on this page).
The bq2050 calculates the gas gauge bits, GG3-GG0 as a
function of CACH and LMD. The results of the calculation
give available capacity in 1 16 increments from 0 to 15 16.
12
Not Recommended For New Designs
bq2050
Table 7. Temperature Register
Last Measured Discharge Register (LMD)
TMP3
TMP2
TMP1
TMP0
0
0
0
0
T < -30°C
0
0
0
1
-30°C < T < -20°C
0
0
1
0
-20°C < T < -10°C
0
0
1
1
-10°C < T < 0°C
0
1
0
0
0°C < T < 10°C
0
1
0
1
10°C < T < 20°C
0
1
1
0
20°C < T < 30°C
0
1
1
1
30°C < T < 40°C
LMD is a read/write register (address=05h) that the
bq2050 uses as a measured full reference. The bq2050
adjusts LMD based on the measured discharge capacity
of the battery from full to empty. In this way the bq2050
updates the capacity of the battery. LMD is set to PFC
during a bq2050 reset.
Temperature
1
0
0
0
40°C < T < 50°C
1
0
0
1
50°C < T < 60°C
1
0
1
0
60°C < T < 70°C
1
0
1
1
70°C < T < 80°C
1
1
0
0
T > 80°C
Secondary Status Flags Register (FLGS2)
The read-only FLGS2 register (address=06h) contains
the secondary bq2050 flags.
7
-
TMPGG Gas Gauge Bits
6
5
4
3
2
1
0
-
-
-
-
GG3
GG2
GG1
GG0
2
-
1
-
0
The discharge rate flags, DR2–0, are bits 6–4.
DR2
0
0
0
7
FLGS2 Bits
5
4
3
DR1
DR0
-
6
DR2
DR1
0
0
1
DR0
0
1
0
Discharge Rate
DRATE < 0.5C
0.5C ≤ DRATE < 2C
DRATE ≥ 2C (OVLD = 1)
They are used to determine the current discharge regime as follows:
Nominal Available Charge Registers
(NACH/NACL)
7
-
The read/write NACH high-byte register (address=03h) and
the read-only NACL low-byte register (address=17h) are
the main gas gauging register for the bq2050. The NAC
registers are incremented during charge actions and decremented during discharge and self-discharge actions. The
correction factors for charge/discharge efficiency are applied
automatically to NAC. NACH and NACL are set to 0 during a bq2050 reset.
6
-
5
-
FLGS2 Bits
4
3
-
2
-
1
-
0
OVLD
The overload flag (OVLD) is asserted when a discharge
rate in excess of 2C is detected. OVLD remains asserted
as long as the condition persists and is cleared 0.5 seconds after the rate drops below 2C. The overload condition is used to stop sampling of the battery terminal characteristics for end-of-discharge determination.
Program Pin Pull-Down Register (PPD)
Writing to the NAC registers affects the available charge
counts and, therefore, affects the bq2050 gas gauge operation. Do not write the NAC registers to a value greater than
LMD.
The read-only PPD register (address=07h) contains some
of the programming pin information for the bq2050. The
segment drivers, SEG1–6, have a corresponding PPD register location, PPD1–6. A given location is set if a pull-down
resistor has been detected on its corresponding segment
driver. For example, if SEG1 and SEG4 have pull-down
resistors, the contents of PPD are xx001001.
Battery Identification Register (BATID)
The read/write BATID register (address=04h) is available for use by the system to determine the type of battery pack. The BATID contents are retained as long as
VCC is greater than 2V. The contents of BATID have no
effect on the operation of the bq2050. There is no default setting for this register.
Program Pin Pull-Up Register (PPU)
The read-only PPU register (address=08h) contains the rest
of the programming pin information for the bq2050. The
segment drivers, SEG1–6, have a corresponding PPU register location, PPU1–6. A given location is set if a pull-up resistor has been detected on its corresponding segment
13
Not Recommended For New Designs
bq2050
driver. For example, if SEG3 and SEG6 have pull-up resistors, the contents of PPU are xx100100.
VTS Register Bits
7
PPD/PPU Bits
5
4
3
6
5
4
3
2
1
0
VTS7 VTS6 VTS5 VTS4 VTS3 VTS2 VTS1 VTS0
7
6
2
1
0
-
-
PPU6 PPU5 PPU4 PPU3 PPU2 PPU1
-
-
PPD6 PPD5 PPD4 PPD3 PPD2 PPD1
Compensated Available Charge Registers
(CACH/CACL)
The read-only CACH high-byte register (address = 0Dh)
and the read-only CACL low-byte register (address =
0Eh) represent the available charge compensated for
discharge rate and temperature. CACH and CACL use
piece-wise corrections as outlined in Tables 3A, 3B, 4A,
and 4B, and will vary as conditions change. The NAC
and LMD registers are not affected by the discharge
rate and temperature.
Capacity Inaccurate Count Register (CPI)
The read-only CPI register (address=09h) is used to indicate the number of times a battery has been charged
without an LMD update. Because the capacity of a rechargeable battery varies with age and operating conditions, the bq2050 adapts to the changing capacity over
time. A complete discharge from full (NAC=LMD) to
empty (EDV1=1) is required to perform an LMD update
assuming there have been no intervening valid charges,
the temperature is greater than or equal to 0°C, and the
self-discharge counter is less than 4096 counts.
Scaled Available Energy Registers
(SAEH/SAEL)
The read-only SAEH high-byte register (address = 0Fh)
and the read only SAEL low-byte register (address =
10h) are used to scale battery voltage and CAC to a
value which can be translated to watt-hours remaining
under the present conditions. SAEL and SAEH may be
converted to mWh using the formula on page 7.
The CPI register is incremented every time a valid
charge is detected. When NAC > 0.94 * LMD, however,
the CPI register increments on the first valid charge;
CPI does not increment again for a valid charge until
NAC < 0.94 * LMC. This prevents continuous trickle
charging from incrementing CPI if self-discharge decrements NAC. The CPI register increments to 255 without rolling over. When the contents of CPI are incremented to 64, the capacity inaccurate flag, CI, is asserted in the FLGS1 register. The CPI register is reset
whenever an update of the LMD register is performed,
and the CI flag is also cleared.
Reset Register (RST)
The reset register (address = 39h) enables a softwarecontrolled reset of the device. By writing the RST register contents from 00h to 80h, a bq2050 reset is performed. Setting any bit other than the most-significant
bit of the RST register is not allowed and results in improper operation of the bq2050.
Battery Voltage Register (VSB)
Resetting the bq2050 sets the following:
The read-only battery voltage register is used to read the
single-cell battery voltage on the SB pin. The VSB register (address = 0Bh) is updated approximately once per second with the present value of the battery voltage. VSB =
2.4V * (VSB/256).
n
LMD = PFC
n
CPI, VDQ, NACH, and NACL = 0
n
CI and BRP = 1
Note: Self-discharge is disabled when PROG5 = H.
VSB Register Bits
7
6
5
4
3
2
1
Display
0
VSB7 VSB6 VSB5 VSB4 VSB3 VSB2 VSB1 VSB0
The bq2050 can directly display capacity information
using low-power LEDs. If LEDs are used, the program
pins should be resistively tied to VCC or VSS for a program high or program low, respectively.
Voltage Threshold Register (VTS)
The end-of-discharge threshold voltages (EDV1 and
EDVF) can be set using the VTS register (address =
0Ch). The read/write VTS register sets the EDV1 trip
point. EDVF is set 50mV below EDV1. The default
value in the VTS register is A2h, representing EDV1 =
1.52V and EDVF = 1.47V. EDV1 = 2.4V * (VTS/256).
The bq2050 displays the battery charge state in relative
mode. In relative mode, the battery charge is represented
as a percentage of the LMD. Each LED segment represents 20% of the LMD.
The capacity display is also adjusted for the present battery temperature. The temperature adjustment reflects
the available capacity at a given temperature but does
14
Not Recommended For New Designs
bq2050
SEG1 blinks at a 4Hz rate whenever VSB has been detected to be below VEDV1 (EDV1 = 1), indicating a lowbattery condition. VSB below VEDVF (EDVF = 1) disables
the display output.
not affect the NAC register. The temperature adjustments are detailed in the CACH and CACL register descriptions.
When DISP is tied to VCC, the SEG1–5 outputs are inactive. When DISP is left floating, the display becomes active whenever the bq2050 detects a charge in progress
VSRO > VSRQ . When pulled low, the segment outputs become active for a period of four seconds, ± 0.5 seconds.
Microregulator
The bq2050 can operate directly from one cell. A micropower source for the bq2050 can be inexpensively built
using the FET and an external resistor to accommodate
a greater number of cells; see Figure 1.
The segment outputs are modulated as two banks, with
segments 1, 3, and 5 alternating with segments 2 and 4.
The segment outputs are modulated at approximately
100Hz with each segment bank active for 30% of the period.
15
Not Recommended For New Designs
bq2050
Absolute Maximum Ratings
Symbol
Parameter
Minimum
Maximum
Unit
Notes
VCC
Relative to VSS
-0.3
7.0
V
All other pins
Relative to VSS
-0.3
7.0
V
REF
Relative to VSS
-0.3
8.5
V
Current limited by R1 (see Figure 1)
VSR
Relative to VSS
-0.3
7.0
V
Minimum 100Ω series resistor should
be used to protect SR in case of a
shorted battery (see the bq2050 application note for details).
TOPR
Operating temperature
0
70
°C
Commercial
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation
should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.
DC Voltage Thresholds (TA = TOPR; V = 3.0 to 6.5V)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Notes
VEDVF
Final empty warning
1.44
1.47
1.50
V
SB
VEDV1
First empty warning
1.49
1.52
1.55
V
SB
VSRO
SR sense range
-300
-
2000
mV
SR, VSR + VOS
VSRQ
Valid charge
210
-
-
µV
VSR + VOS (see note)
VSRD
Valid discharge
-
-
-200
µV
VSR + VOS (see note)
VMCV
Maximum single-cell voltage
2.20
2.25
2.30
V
Note:
VOS is affected by PC board layout. Proper layout guidelines should be followed for optimal performance.
See “Layout Considerations.”
16
SB
Not Recommended For New Designs
bq2050
DC Electrical Characteristics (TA = TOPR)
Symbol
Parameter
VCC
Supply voltage
VOS
Offset referred to VSR
VREF
Minimum
Typical
Maximum
Unit
Notes
VCC excursion from < 2.0V to ≥
3.0V initializes the unit.
3.0
4.25
6.5
V
-
±50
±150
µV
DISP = VCC
Reference at 25°C
5.7
6.0
6.3
V
IREF = 5µA
Reference at -40°C to +85°C
4.5
-
7.5
V
IREF = 5µA
RREF
Reference input impedance
2.0
5.0
-
MΩ
VREF = 3V
-
90
135
µA
VCC = 3.0V, DQ = 0
ICC
Normal operation
-
120
180
µA
VCC = 4.25V, DQ = 0
-
170
250
µA
VCC = 6.5V, DQ = 0
-
VCC
V
VSB
Battery input
0
RSBmax
SB input impedance
10
-
-
MΩ
0 < VSB < VCC
IDISP
DISP input leakage
-
-
5
µA
VDISP = VSS
ILCOM
LCOM input leakage
-0.2
-
0.2
µA
DISP = VCC
VRBI > VCC < 3V
IRBI
RBI data retention current
-
-
100
nA
RDQ
Internal pulldown
500
-
-
KΩ
VSR
Sense resistor input
-0.3
-
2.0
V
RSR
SR input impedance
VIH
Logic input high
VIL
Logic input low
VIZ
Logic input Z
VOLSL
10
-
-
MΩ
VCC - 0.2
-
-
V
VSR < VSS = discharge;
VSR > VSS = charge
-200mV < VSR < VCC
PROG1–PROG6
-
-
VSS + 0.2
V
PROG1–PROG6
float
-
float
V
PROG1–PROG6
SEGX output low, low VCC
-
0.1
-
V
VCC = 3V, IOLS ≤ 1.75mA
SEG1–SEG5
VOLSH
SEGX output low, high VCC
-
0.4
-
V
VCC = 6.5V, IOLS ≤ 11.0mA
SEG1–SEG5
VCC = 3V, IOHLCOM = -5.25mA
VOHLCL
LCOM output high, low VCC
VCC - 0.3
-
-
V
VOHLCH
LCOM output high, high VCC
VCC - 0.6
-
-
V
IIH
PROG1-6 input high current
-
1.2
-
µA
IIL
PROG1-6 input low current
IOHLCOM LCOM source current
VCC = 6.5V, IOHLCOM = -33.0mA
VPROG = VCC/2
-
1.2
-
µA
VPROG = VCC/2
-33
-
-
mA
At VOHLCH = VCC - 0.6V
IOLS
SEG1-5 sink current
-
-
11.0
mA
At VOLSH = 0.4V
IOL
Open-drain sink current
-
-
5.0
mA
At VOL = VSS + 0.3V
DQ
IOL ≤ 5mA, DQ
VOL
Open-drain output low
-
-
0.5
V
VIHDQ
DQ input high
2.5
-
-
V
DQ
VILDQ
DQ input low
-
-
0.8
V
DQ
RPROG
Soft pull-up or pull-down resistor value (for programming)
-
-
200
KΩ
PROG1–PROG6
RFLOAT
Float state external impedance
-
5
-
MΩ
PROG1–PROG6
Note:
All voltages relative to VSS.
17
Not Recommended For New Designs
bq2050
Serial Communication Timing Specification (TA = TOPR)
Symbol
Parameter
Minimum
Typical
Maximum
Unit
tCYCH
Cycle time, host to bq2050
3
-
-
ms
tCYCB
Cycle time, bq2050 to host
3
-
6
ms
tSTRH
Start hold, host to bq2050
5
-
-
ns
tSTRB
Start hold, bq2050 to host
500
-
-
µs
tDSU
Data setup
-
-
750
µs
tDH
Data hold
750
-
-
µs
tDV
Data valid
1.50
-
-
ms
tSSU
Stop setup
-
-
2.25
ms
tSH
Stop hold
700
-
-
µs
tSV
Stop valid
2.95
-
-
ms
tB
Break
3
-
-
ms
tBR
Break recovery
1
-
-
ms
Notes:
Notes
See note
The open-drain DQ pin should be pulled to at least VCC by the host system for proper DQ operation.
DQ may be left floating if the serial interface is not used.
Serial Communication Timing
DQ
(R/W "1")
DQ
(R/W "0")
tSTRH
tSTRB
tDH
tDSU
tDV
tSH
tSSU
DQ
(BREAK)
tSV
tCYCH, tCYCB, tB
tBR
TD201002.eps
18
Not Recommended For New Designs
bq2050
16-Pin SOIC Narrow (SN)
16-Pin SN (0.150" SOIC)
D
e
Inches
B
Dimension
Min.
Max.
Min.
Max.
A
0.060
0.070
1.52
1.78
A1
0.004
0.010
0.10
0.25
B
0.013
0.020
0.33
0.51
C
0.007
0.010
0.18
0.25
E
H
A
C
Millimeters
A1
D
0.385
0.400
9.78
10.16
E
0.150
0.160
3.81
4.06
e
0.045
0.055
1.14
1.40
H
0.225
0.245
5.72
6.22
L
0.015
0.035
0.38
0.89
.004
L
Data Sheet Revision History
Change No.
1
Page No.
4
1
2
11, 14
16
2
2
2
Notes:
Description
Changed reset procedure
Was:
Is:
Deleted reset register
Changed values
VEDVF:
VEDV1:
VCC:
17
Changed values
4, 11, 13, 14 Reinserted reset register
9
Maximum offset
VOS:
Change 1 = June 1995 B changes from Dec. 1994.
Change 2 = Sept. 1996 C changes from June 1995 B.
19
Nature of Change
Reset by issuing command over serial port
Reset by removing VCC and grounding RBI for
15 s.
Min. was 1.45; Max. was 1.49
Min. now is 1.44; Max. now is 1.50
Min. was 1.50; Min. now is 1.49
Min. was 2.5; Min. now is 3.0
Max. was 150
Max. now is 180
Not Recommended For New Designs
bq2050
Ordering Information
bq2050
Temperature Range:
blank = Commercial (-20 to +70°C)
Package Option:
SN = 16-pin narrow SOIC
Device:
bq2040 Gas Gauge IC With SMB Interface
17919 Waterview Parkway
Dallas, Texas 75252
Fax: (972) 437-9198
Tel: (972) 437-9195
www.benchmarq.com or www.unitrode.com
Copyright © 1996, Unitrode Corporation All rights reserved. No part of this data sheet may be reproduced in any
form or means, without express permission from Unitrode. Unitrode reserves the right to make changes in its products without notice.
Unitrode assumes no responsibility for use of any products or circuitry described within. No license for use of intellectual property (patents, copyrights, or other rights) owned by Unitrode or other parties is granted or implied.
Unitrode does not authorize the use of its components in life-support systems where failure or malfunction may
cause injury to the user. If Unitrode components are used in life-support systems, the user assumes all responsibilities and indemnifies Unitrode from all liability or damages.
Benchmarq is a registered trademark of Unitrode Corporation.
20
Printed in U.S.A.
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ2050SN-D119
NRND
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
2050
D119
BQ2050SN-D119G4
NRND
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
2050
D119
BQ2050SN-D119TR
NRND
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
2050
D119
BQ2050SN-D119TRG4
NRND
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
2050
D119
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
BQ2050SN-D119TR
Package Package Pins
Type Drawing
SOIC
D
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
16.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
10.3
2.1
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ2050SN-D119TR
SOIC
D
16
2500
367.0
367.0
38.0
Pack Materials-Page 2
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