FEATURES 256 position 10 kΩ, 50 kΩ, 100 kΩ +20 V to +30 V single-supply operation ±10 V to ±15 V dual-supply operation 3-wire SPI®-compatible serial interface Low temperature coefficient 35 ppm/°C typical THD 0.006% typical Midscale preset Compact MSOP-10 package Automotive temperature range: −40°C to +125°C iCMOS™1 process technology APPLICATIONS High voltage DAC Programmable power supply Programmable gain and offset adjustment Programmable filters and delays Actuator control Audio volume control Mechanical potentiometer replacement FUNCTIONAL BLOCK DIAGRAM AD5290 SDO VDD Q A 8-BIT SERIAL REGISTER 8 8-BIT LATCH 8 W SDI D CK B RS CLK CS VSS POR DGND 04716-001 Data Sheet Compact +30 V / ±15 V 256-Position Digital Potentiometer AD5290 Figure 1. GENERAL DESCRIPTION The AD5290 is one of the few high voltage, high performance, and compact digital potentiometers2, 3 in the market at present. This device can be used as a programmable resistor or resistor divider. The AD5290 performs the same electronic adjustment function as mechanical potentiometers, variable resistors, and trimmers, with enhanced resolution, solid-state reliability, and superior temperature stability. With digital rather than manual control, the AD5290 provides layout flexibility and allows closed-loop dynamic controllability. The AD5290 is available in MSOP-10 package and has 10 kΩ, 50 kΩ, and 100 kΩ options. All parts are guaranteed to operate over the −40°C to +125°C extended automotive temperature range. 1 iCMOS™ Process Technology. For analog systems designers who need high performance ICs at higher voltage levels, iCMOS is a technology platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and package size, and increased ac and dc performance. 2 The terms digital potentiometer and RDAC are used interchangeably. 3 The RDAC segmentation is protected by U.S. Patent Number 5,495,245. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2005-2011 Analog Devices, Inc. All rights reserved. AD5290 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Programming the Variable Resistor ......................................... 15 Applications ....................................................................................... 1 Programming the Potentiometer Divider ............................... 16 Functional Block Diagram .............................................................. 1 3-Wire Serial Bus Digital Interface .......................................... 16 General Description ......................................................................... 1 Daisy Chain Operation .............................................................. 16 Revision History ............................................................................... 2 ESD Protection ........................................................................... 17 Specifications..................................................................................... 3 Terminal Voltage Operating Range ......................................... 17 Electrical Characteristics—10 kΩ Version................................ 3 Power-Up and Power-Down Sequences .................................. 17 Electrical Characteristics—50 kΩ, 100 kΩ Versions ............... 5 Layout and Power Supply Biasing ............................................ 17 Interface Timing Characteristics ................................................ 7 Applications..................................................................................... 18 3-Wire Digital Interface ................................................................... 8 High Voltage DAC...................................................................... 18 Absolute Maximum Ratings............................................................ 9 Programmable Power Supply ................................................... 18 ESD Caution .................................................................................. 9 Audio Volume Control .............................................................. 18 Pin Configuration and Descriptions ............................................ 10 Outline Dimensions ....................................................................... 20 Typical Performance Characteristics ........................................... 11 Ordering Guide .......................................................................... 20 Theory of Operation ...................................................................... 15 REVISION HISTORY 11/11—Rev. B to Rev. C Change to Figure 33 ....................................................................... 18 4/10—Rev. A to Rev. B Changes to Figure 29 ...................................................................... 16 Updated Outline Dimensions ....................................................... 20 7/09—Rev. 0 to Rev. A Changes to Features Section ............................................................1 Changes to Ordering Guide .......................................................... 20 12/05—Revision 0: Initial Version Rev. C | Page 2 of 20 Data Sheet AD5290 SPECIFICATIONS ELECTRICAL CHARACTERISTICS—10 kΩ VERSION VDD/VSS = ±15 V ± 10%, VA = VDD, VB = VSS or 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential NL 2 Resistor Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient 3 Wiper Resistance DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Integral Nonlinearity 4 Differential Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range 5 Capacitance 6 A, B Capacitance6 Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High (CS, CLK, SDI) Input Logic Low (CS, CLK, SDI) Output Logic High (SDO) Output Logic Low (SDO) Input Current Input Capacitance6 POWER SUPPLIES Positive Supply Current Symbol Conditions Min Typ 1 Max Unit R-DNL R-INL ∆RAB (∆RAB/RAB)/∆T×106 RW RWB, VA = NC RWB, VA = NC TA = +25°C VAB = VDD, wiper = no connect −1 −1.5 −30 ±0.3 ±0.7 +1 +1.5 +30 LSB LSB % ppm/°C Ω INL DNL (∆VW/VW)/∆T×106 VWFSE VWZSE VA, B, W CA, B CW ICM VIH VIL VOH VOL IIL CIL IDD Negative Supply Current ISS Power Dissipation 7 PDISS Power Supply Rejection Ratio PSRR 35 50 −1 −1 Code = 0x80 Code = 0xFF Code = 0x00 −6 0 ±0.3 ±0.3 5 −4 +3 VSS f = 1 MHz, measured to GND, code = 0x80 f = 1 MHz, measured to GND, code = 0x80 VA = V B = VW 100 +1 +1 0 +5 VDD 45 V pF 60 pF 1 nA 2.4 0.8 RPull-up = 2.2 kΩ to 5 V IOL = 1.6 mA VIN = 0 V or 5 V 4.9 0.4 ±1 5 VIH = +5 V or VIL = 0 V, VDD/VSS = ±15 V VIH = +5 V or VIL = 0 V, VDD/VSS = ±15 V VIH = +5 V or VIL = 0 V, VDD/VSS = ±15 V ΔVDD/ΔVSS = ±15 V ± 10% Rev. C | Page 3 of 20 −0.15 LSB LSB ppm/°C LSB LSB V V V V µA pF 15 50 μA −0.01 −1 μA 765 μW +0.15 %/% ±0.08 AD5290 Parameter DYNAMIC CHARACTERISTICS6, 8, 9 Bandwidth −3 dB Total Harmonic Distortion VW Settling Time Resistor Noise Voltage Data Sheet Symbol Conditions BW THDW tS Code = 0x80 VA = 1 V rms, VB = 0 V, f = 1 kHz VA = 10 V, VB = 0 V, ±1 LSB error band RWB = 5 kΩ, f = 1 kHz eN_WB Min Typ 1 Max Unit 470 0.006 4 kHz % µs 9 nV/√Hz Typical represents average reading at +25°C, VDD = +15 V, and VSS = −15 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic. 3 All parts have a 35 ppm/°C temperature coefficient. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD × VDD) + abs (ISS × VSS). CMOS logic-level inputs result in minimum power dissipation. 8 Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 9 All dynamic characteristics use VDD = +15 V and VSS = −15 V. 1 2 Rev. C | Page 4 of 20 Data Sheet AD5290 ELECTRICAL CHARACTERISTICS—50 KΩ, 100 KΩ VERSIONS VDD/VSS = ±15 V ± 10%, VA = +VDD, VB = VSS or 0 V, −40°C < TA < +125°C, unless otherwise noted. Table 2. Parameter DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential NL 2 Resistor Nonlinearity2 Nominal Resistor Tolerance Resistance Temperature Coefficient 3 Wiper Resistance DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Integral Nonlinearity 4 Differential Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range 5 Capacitance 6 A, B Capacitance6 Common-Mode Leakage DIGITAL INPUTS AND OUTPUTS Input Logic High (CS, CLK, SDI) Input Logic Low (CS, CLK, SDI) Output Logic High (SDO) Output Logic Low (SDO) Input Current Input Capacitance6 POWER SUPPLIES Positive Supply Current Symbol Conditions Min Typ 1 Max Unit R-DNL R-INL ∆RAB (∆RAB/RAB)/∆T×106 RW RWB, VA = NC RWB, VA = NC TA = +25°C VAB = VDD, wiper = no connect −0.5 −1 −30 ±0.1 ±0.5 +0.5 +1 +30 LSB LSB % ppm/°C Ω INL DNL (∆VW/VW)/∆T×106 Code = 0x80 VWFSE VWZSE Code = 0xFF Code = 0x00 VA, B, W CA, B CW ICM VIH VIL VOH VOL IIL CIL IDD Negative Supply Current ISS Power Dissipation 7 PDISS Power Supply Rejection Ratio PSRR 35 50 100 −1 −1 ±0.5 ±0.5 5 +1 +1 LSB LSB ppm/°C −2.5 0 −1.6 +0.6 0 +1.5 LSB LSB VDD 45 V pF 60 pF 1 nA VSS f = 1 MHz, measured to GND, code = 0x80 f = 1 MHz, measured to GND, code = 0x80 VA = V B = VW 2.4 0.8 RPull-up = 2.2 kΩ to 5 V IOL = 1.6 mA VIN = 0 V or 5 V 4.9 0.4 ±1 5 VIH = +5 V or VIL = 0 V, VDD/VSS = ±15 V VIH = +5 V or VIL = 0 V, VDD/VSS = ±15 V VIH = +5 V or VIL = 0 V, VDD/VSS = ±15 V ΔVDD/ΔVSS = ±15 V ± 10% Rev. C | Page 5 of 20 −0.05 V V V V µA pF 15 50 μA −0.01 −1 μA 765 μW +0.05 %/% ±0.01 AD5290 Parameter DYNAMIC CHARACTERISTICS6, 8, 9 Bandwidth −3 dB Data Sheet Symbol Conditions BW RAB = 50 kΩ, code = 0x80 RAB = 100 kΩ, code = 0x80 VA = 1 V rms, VB = 0 V, f = 1 kHz VA = 10 V, VB = 0 V, ±1 LSB error band RWB = 25 kΩ, f = 1 kHz Total Harmonic Distortion VW Settling Time THDW tS Resistor Noise Voltage eN_WB Min Typ 1 Max Unit 90 50 0.002 4 kHz kHz % µs 20 nV√Hz Typical represents average reading at +25°C, VDD = +15 V, and VSS = −15 V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from an ideal value measured between successive tap positions. Parts are guaranteed monotonic. 3 All parts have a 35 ppm/°C temperature coefficient. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other. 6 Guaranteed by design and not subject to production test. 7 PDISS is calculated from (IDD × VDD) + abs (ISS × VSS). CMOS logic level inputs result in minimum power dissipation. 8 Bandwidth, noise, and settling times are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 9 All dynamic characteristics use VDD = +15 V and VSS = −15 V. 1 2 Rev. C | Page 6 of 20 Data Sheet AD5290 INTERFACE TIMING CHARACTERISTICS Table 3. Parameter 1, 2 Clock Frequency Input Clock Pulse Width Data Setup Time Data Hold Time CLK to SDO Propagation Delay 3 CS Setup Time CS High Pulse Width CLK Fall to CS Fall Hold Time CLK Rise to CS Rise Hold Time CS Rise to Clock Rise Setup Symbol fCLK tCH, tCL tDS tDH tPD tCSS tCSW tCSH0 tCSH tCS1 Conditions Min Clock level high or low 120 30 20 10 120 150 10 120 120 RPull-up = 2.2 kΩ, CL < 20 pF Typ Max 4 100 Unit MHz ns ns ns ns ns ns ns ns ns See Figure 3 for the location of the measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using VDD = +15 V and VSS = −15 V. 2 Guaranteed by design and not subject to production test. 3 Propagation delay depends on the value of VDD, RPull-up, and CL. 1 Rev. C | Page 7 of 20 AD5290 Data Sheet 3-WIRE DIGITAL INTERFACE Data is loaded MSB first. SDI (DATA IN) Table 4. AD5290 Serial Data-Word Format B7 D7 MSB 27 B6 D6 B5 D5 B4 D4 B3 D3 1 DX DX 0 tDS B2 D2 B1 D1 B0 D0 LSB 20 tDH SDO (DATA OUT) 1 D'X D'X 0 tPD_MAX tCH 1 tCS1 CLK 0 tCSH0 CS VOUT 0 D7 D6 D5 D4 D3 D2 D1 D0 1 CS 1 tCL tCSS tCSH tCSW 0 0 1 0 tS VDD RDAC REGISTER LOAD 1 0 VOUT 0V ±1 LSB ERROR BAND ±1 LSB Figure 2. AD5290 3-Wire Digital Interface Timing Diagram (VA = VDD, VB = 0 V, VW = VOUT) Figure 3. Detail Timing Diagram Rev. C | Page 8 of 20 04716-003 CLK 1 04716-002 SDI Data Sheet AD5290 ABSOLUTE MAXIMUM RATINGS TA = +25°C, unless otherwise noted. Table 5. Parameter VDD to GND VSS to GND VDD to VSS VA, VB, VW to GND Maximum Current IWB, IWA Pulsed IWB Continuous (RWB ≤ 6 kΩ, A Open, VDD/VSS = 30 V/0 V) 1 IWA Continuous (RWA ≤ 6 kΩ, B Open, VDD/VSS = 30 V/0 V)1 Digital Input and Output Voltages to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) 2 Storage Temperature Lead Temperature (Soldering, 10 sec to 30 sec) Thermal Resistance2 θJA: MSOP-10 Rating −0.3 V, +35 V +0.3 V, −16.5 V −0.3 V, +35 V VSS, VDD Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ±20 mA ±5 mA ±5 mA 0 V, +7 V −40°C to +125°C +150°C −65°C to +150°C 245°C 230°C/W The maximum terminal current is bound by the maximum current handling of the switches, maximum power dissipation of the package, and the maximum applied voltage across any two of the following at a given resistance: A terminal, B terminal, and W terminal. 2 Package power dissipation = (TJMAX – TA)/θJA. 1 Rev. C | Page 9 of 20 AD5290 Data Sheet 10 W AD5290 9 VDD TOP VIEW (Not to Scale) 8 SDO A 1 B 2 VSS 3 GND 4 CS 5 7 SDI 6 CLK 04716-004 PIN CONFIGURATION AND DESCRIPTIONS Figure 4. AD5290 Pin Configuration Table 6. AD5290 Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic A B VSS GND CS CLK SDI SDO 9 10 VDD W Description A Terminal. VSS ≤ VA ≤ VDD. B Terminal. VSS ≤ VB ≤ VDD. Negative Supply. Connect to 0 V for single-supply applications. Digital Ground. Chip Select Input; Active Low. When CS returns high, data is loaded into the wiper register. Serial Clock Input. Positive edge triggered. Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first. Serial Data Output Pin. Internal N-Ch FET with open-drain output that requires external pull-up resistor. It shifts out the previous eight SDI bits that allow daisy-chain operation of multiple packages. Positive Power Supply. W Terminal. VSS ≤ VW ≤ VDD. Rev. C | Page 10 of 20 Data Sheet AD5290 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 1.0 VDD = 16.5V VDD = 16.5V 0.8 0.4 0.2 0 –0.2 –0.4 04716-029 –0.6 –0.8 –1.0 0 32 64 96 128 160 192 224 –40°C +25°C +125°C 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 04716-032 –40°C +25°C +125°C 0.6 POTENTIOMETER MODE DNL (LSB) RHEOSTAT MODE INL (LSB) 0.8 –0.8 –1.0 0 256 32 64 CODE (Decimal) 96 128 160 192 224 256 CODE (Decimal) Figure 5. Resistance Step Position Nonlinearity Error vs. Code Figure 8. Potentiometer Divider Differential Nonlinearity Error vs. Code 20 1.0 VDD = 16.5V –40°C +25°C +125°C IDD @ VDD/VSS = 30V/0V 16 SUPPLY CURRENT (µA) 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 IDD @ VDD/VSS = ±15V 12 8 4 ISS @ VDD/VSS = 30V/0V –0.8 –1.0 0 32 64 96 128 160 192 224 04716-005 0 04716-030 RHEOSTAT MODE DNL (LSB) 0.8 ISS @ VDD/VSS = ±15V –4 –40 256 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) CODE (Decimal) Figure 6. Resistance Step Change Differential Nonlinearity Error vs. Code Figure 9. Supply Current IDD vs. Temperature 1.0 VDD = 16.5V 100kΩ 0.4 0.2 0 –0.2 –0.4 –0.6 100 80 60 50kΩ 40 20 –0.8 –1.0 0 32 64 96 128 160 192 224 256 0 –40 10kΩ –20 0 20 40 04716-007 0.6 TOTAL RESISTANCE, RAB (kΩ) –40°C +25°C +125°C 04716-031 POTENTIOMETER MODE INL (LSB) VDD/VSS = ±15V 120 0.8 60 80 100 TEMPERATURE (°C) CODE (Decimal) Figure 7. Potentiometer Divider Nonlinearity Error vs. Code Figure 10. Total Resistance vs. Temperature Rev. C | Page 11 of 20 120 AD5290 Data Sheet 0 –6 10k 50k 100k 60 –12 –18 20 –24 (dB) 40 0 –42 –60 –48 0 32 64 96 128 160 192 224 0x20 0x10 0x04 –40 –80 0x40 0x08 –36 –100 0x80 –30 –20 04716-033 RHEOSTAT MODE TEMPCO (ppm/°C) 80 0x02 0x01 04716-023 100 –54 –60 1k 256 10k 1M Figure 14. 50 kΩ Gain vs. Frequency vs. Code Figure 11. (ΔRWB/RWB)/ΔT Rheostat Mode Tempco 0 100 –6 80 10k 50k 100k 60 –12 –18 20 –24 (dB) 40 0 0x80 0x40 0x20 0x10 0x08 –30 –20 –36 –40 –42 –60 –48 0x04 0x02 –80 –100 0 32 64 96 128 160 192 224 256 0x01 04716-024 04716-034 POTENTIOMETER MODE TEMPCO (ppm/°C) 100k (Hz) CODE (Decimal) –54 –60 1k 10k 100k 1M (Hz) CODE (Decimal) Figure 15. 100 kΩ Gain vs. Frequency vs. Code Figure 12. (ΔVWB/VWB)/ΔT Potentiometer Mode Tempco 0 0x80 –6 –12 0x40 0x20 –18 0x08 –30 0x04 –36 –42 0x02 0x01 –54 –60 1k 04716-035 –48 04716-022 (dB) 0x10 –24 10k 100k 1M (Hz) Figure 16. Midscale Transition Glitch Figure 13. 10 kΩ Gain vs. Frequency vs. Code Rev. C | Page 12 of 20 Data Sheet AD5290 6 CODE = 80H, VDD/VSS = ±15V, VA/VB = ±10V VDD/VSS = 30V/0V VA = VDD VB = 0V THEORETICAL IWB_MAX (mA) 5 –40 +PSRR @ VDD/VSS = ±15V DC ± 10% p-p AC –20 –PSRR @ VDD/VSS = ±15V DC ± 10% p-p AC RAB = 10kΩ 4 3 RAB = 50kΩ 2 0 100 1k 10k RAB = 100kΩ 0 0 1M 100k 04716-027 1 04716-036 POWER SUPPLY REJECTION RATIO (dB) –60 64 128 Figure 17. Power Supply Rejection vs. Frequency 1 Figure 20. Theoretical Maximum Current vs. Code 140 VDD/VSS = ±15V CODE = MIDSCALE VIN = 1VRMS SUPPLY CURRENT IDD (µA) 120 10kΩ THD + N (%) 0.01 100kΩ 50kΩ 0.001 256 192 CODE (Decimal) FREQUENCY (Hz) VDD = +15V VSS = –15V VDIG = +5V 100 80 CODE = AA 60 40 CODE = FF 100 1k 10k 04716-037 04716-009 0.0001 10 20 0 10k 100k 100k FREQUENCY (Hz) 10M 1M FREQUENCY (Hz) Figure 18. Total Harmonic Distortion Plus Noise vs. Frequency Figure 21. Supply Current IDD vs. Frequency 10 1 VDD/VSS = ±15V CODE = MIDSCALE fIN = 1kHz VDD = +15V VSS = –15V VDIG = +5V SUPPLY CURRENT ISS (nA) 8 THD + N (%) 0.1 50kΩ 0.01 10kΩ 6 CODE = AA 4 CODE = FF 2 0.01 0.1 1 10 0 10k 04716-038 0.001 0.001 04716-010 100kΩ 100k 1M FREQUENCY (Hz) AMPLITUDE (V) Figure 22. Supply Current ISS vs. Frequency Figure 19. Total Harmonic Distortion Plus Noise vs. Amplitude Rev. C | Page 13 of 20 10M AD5290 Data Sheet 100 10 0 1 2 3 4 04716-041 04716-039 VDD/VSS = ±16.5V 5 DIGITAL INPUT VOLTAGE VIH (V) Figure 23. Supply Current vs. Digital Input Voltage Figure 25. Large Signal Settling Time, Code = 0x00 to 0xFF 04716-040 SUPPLY CURRENT IDD (µA) 1000 Figure 24. Digital Feedthrough Rev. C | Page 14 of 20 Data Sheet AD5290 THEORY OF OPERATION PROGRAMMING THE VARIABLE RESISTOR where: D is the decimal equivalent of the binary code loaded in the 8-bit RDAC register from 0 to 255. RAB is the end-to-end resistance. RW is one of the wiper resistances contributed by the on resistance of an internal switch. Rheostat Operation The part operates in the rheostat mode when only two terminals are used as a variable resistor. The unused terminal can be floating or tied to the W terminal as shown in Figure 26. A A W B W B 04716-011 W A B Figure 26. Rheostat Mode Configuration The nominal resistance between Terminal A and Terminal B, RAB, is available in 10 kΩ, 50 kΩ, and 100 kΩ with ±30% tolerance and has 256 tap points accessed by the wiper terminal. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Figure 27 shows a simplified RDAC structure. A Assuming that an ideal 10 kΩ part is used, the wiper’s first connection starts at the B terminal for the programming code of 0x00 where SWB is closed. The minimum resistance between Terminal W and Terminal B is, therefore, generally 150 Ω. The second connection is the first tap point, which corresponds to 189 Ω (RWB = 1/256 × RAB + 3RW = 39 Ω + 150 Ω) for code 0x01, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,110 Ω. 4RS 4RS 2RS 4RS RW 2RS RS W RW 8-BIT ADDRESS DECODER RS 2RS RW 4RS The AD5290 wiper switch is designed with the transmission gate CMOS topology and with the gate voltage derived from VDD. The wiper resistance, RW, is a function of VDD and temperature. Contrary to the temperature coefficient of the RAB, which is only 35 ppm/°C, the temperature coefficient of the wiper resistance is significantly higher because the wiper resistance doubles from 25°C to 125°C. As a result, the user must take into consideration the contribution of RW on the desirable resistance. On the other hand, the wiper resistance is insensitive to the tap point potential. As a result, RW remains relatively flat at a given VDD and temperature at various codes. 2RS 4RS 04716-012 B Figure 27. AD5290 Simplified RDAC Circuit. (RS = Step Resistor, RW = Wiper Resistor) In the zero-scale condition, a finite total wiper resistance of 150 Ω is present. Regardless of which setting the part is operating in, care should be taken to limit the current between the A terminal to B terminal, W terminal to A terminal, and W terminal to B terminal, to the maximum dc current of 5 mA or pulse current of 20 mA. Otherwise, degradation, or possible destruction of the internal switch contact, can occur. Similar to the mechanical potentiometer, the resistance of the RDAC between the W terminal and the A terminal also produces a digitally controlled complementary resistance, RWA. RWA starts at the maximum resistance value and decreases as the data loaded into the latch increases. The general equation for this operation is RWA (D) = In order to achieve optimum cost performance, Analog Devices has patented the RDAC segmentation architecture for all the digital potentiometers. In particular, the AD5290 employs a 3-stage segmentation approach as shown in Figure 27. As a result, the general equation determining the digitally programmed output resistance between the W terminal and B terminal is RWB (D) = D × R AB + 3 × RW 256 (1) Rev. C | Page 15 of 20 256 − D × R AB + 3 × RW 256 (2) AD5290 Data Sheet PROGRAMMING THE POTENTIOMETER DIVIDER 3-WIRE SERIAL BUS DIGITAL INTERFACE Voltage Output Operation The AD5290 contains a 3-wire digital interface (CS, CLK, and SDI). The 8-bit serial word must be loaded MSB first. The format of the word is shown in Table 4. The positive edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. When CS is low, the clock loads data into the serial register on each positive clock edge. The digital potentiometer easily generates a voltage divider at wiper to B and wiper to A proportional to the input voltage at A to B. Unlike the polarity of VDD to GND, which must be positive, voltage across A to B, W to A, and W to B can be at either polarity. VI A The data setup and data hold times in the Specifications section determine the valid timing requirements. The AD5290 uses an 8-bit serial input data register word that is transferred to the internal RDAC register when the CS line returns to logic high. Extra MSB bits are ignored. VO B 04716-013 W Figure 28. Potentiometer Mode Configuration If ignoring the effect of the wiper resistance for simplicity, connecting the A terminal to 30 V and the B terminal to ground produces an output voltage at the Wiper W to Terminal B ranging from 0 V to 1 LSB less than 30 V. Each LSB of voltage is equal to the voltage applied across Terminal A and Terminal B, divided by the 256 positions of the potentiometer divider. The general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminal A and Terminal B is VW (D) = D 256 − D × VA + × VB 256 256 (3) Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent mainly on the ratio of the internal resistors RWA and RWB and not the absolute values. Therefore, the temperature drift reduces to 5 ppm/°C. DAISY CHAIN OPERATION SDO shifts out the SDI content in the previous frame; thus it can be used for daisy-chaining multiple devices. The SDO pin contains an open drain N-Ch MOSFET and requires a pullup resistor if the SDO function is used. Users need to tie the SDO pin of one package to the SDI pin of the next package. Users may need to increase the clock period because the pull-up resistor and the capacitive loading at the SDO to SDI interface can induce time delay to the subsequent devices. For example, in Figure 29, if two AD5290s are daisy-chained, a total of 16 bits of data are required for each operation. The first set of eight bits goes to U2, and the second set of eight bits goes to U1. The CS should be kept low until all 16 bits are clocked into their respective serial registers. The CS is then pulled high to complete the operation. +5V AD5290 U1 µC MOSI SDI SDO AD5290 RPU 2.2kΩ U2 SDI SDO SCLK SS CLK CS CLK 04716-014 CS Figure 29. Daisy Chain Configuration Rev. C | Page 16 of 20 Data Sheet AD5290 ESD PROTECTION POWER-UP AND POWER-DOWN SEQUENCES All digital inputs are protected with a series input resistor and a Zener ESD structure, as shown in Figure 30. These structures apply to digital input pins, Pin CS, Pin CLK, Pin SDI, and Pin SDO. Because of the ESD protection diodes that limit the voltage compliance at Terminal A, Terminal B, and Terminal W (Figure 31), it is important to power VDD/VSS before applying any voltage to Terminal A, Terminal B, and Terminal W. Otherwise, the diodes are forward-biased such that VDD/VSS are powered unintentionally and affect the system. Similarly, VDD/VSS should be powered down last. The ideal power-up sequence is as follows: GND, VDD, VSS, digital inputs, and VA/VB/VW. The order of powering VA, VB, VW, and the digital inputs is not important, as long as they are powered after VDD/VSS. 340Ω GND 04716-015 LOGIC Figure 30. Equivalent ESD Protection Circuit All analog terminals are also protected by Zener ESD protection diodes, as shown in Figure 31. VDD It is good practice to use a compact, minimum lead-length layout design. The leads to the input should be as direct as possible, with a minimum conductor length. Ground paths should have low resistance and low inductance. A W Similarly, it is also good practice to bypass the power supplies with quality capacitors. Low equivalent series resistance (ESR), 1 µF to 10 µF tantalum or electrolytic capacitors, should be applied at the supplies to minimize any transient disturbance and to filter low frequency ripple. Figure 32 illustrates the basic supply-bypassing configuration for the AD5290. 04716-016 B VSS LAYOUT AND POWER SUPPLY BIASING Figure 31. Equivalent ESD Protection Analog Pins TERMINAL VOLTAGE OPERATING RANGE The AD5290 VDD and VSS power supplies define the boundary conditions for proper 3-terminal digital potentiometer operation. The AD5290 can operate in single supply from +4.5 V to +33 V or dual supply from ±4.5 V to ±16.5 V. The AD5290 is functional at low supply voltages such as 4.5 V, but the performance parameters are not guaranteed. The ground pin of the AD5290 is a digital ground reference. To minimize the digital ground bounce, the AD5290 digital ground terminal should be joined remotely to the analog ground (Figure 32). C3 10µF C4 VSS VDD + C1 0.1µF AD5290 + C2 10µF 0.1µF VSS GND 04716-017 The voltages present on Terminal A, Terminal B, and Terminal W that are more positive than VDD or more negative than VSS are clamped by the internal forward-biased diodes (Figure 31). VDD Figure 32. Power Supply Bypassing Rev. C | Page 17 of 20 AD5290 Data Sheet APPLICATIONS HIGH VOLTAGE DAC AUDIO VOLUME CONTROL AD5290 can be configured as a high voltage DAC, with output voltage as high as 30 V. The circuit is shown in Figure 33. The output is Because of its good THD performance and high voltage capability, AD5290 can be used as a digital volume control. If AD5290 is used directly as an audio attenuator or gain amplifier, a large step change in the volume level at any arbitrary time can lead to an abrupt discontinuity of the audio signal causing an audible zipper noise. To prevent this, a zerocrossing window detector can be inserted to the CS line to delay the device update until the audio signal crosses the window. Since the input signal can operate on top of any dc level rather than absolute zero volt level, zero-crossing in this case means the signal is ac-coupled, and the dc offset level is the signal zero reference point. VO (D) D R [1.2 V (1 2 )] 256 R1 (4) where D is the decimal code from 0 to 255. VDD VDD RBIAS U1A OP284 D1 ADR512 U2 AD5290 V+ 100kΩ V– B U1B OP284 VOUT R2 04716-018 R1 Figure 33. High Voltage DAC PROGRAMMABLE POWER SUPPLY With a boost regulator, such as ADP1611, AD5290 can be used as the variable resistor at the regulator’s FB pin to provide the programmable power supply (Figure 34). The output is VO 1.23 V [1 (D 256) RAB ] R2 (5) AD5290’s VDD is derived from the output. Initially, L1 acts as a short, and VDD is one diode voltage drop below +5 V. The output slowly establishes the final value. The configuration to reduce zipper noise (Figure 35) and the results of using this configuration are shown in Figure 36. The input is ac-coupled by C1 and attenuated down before feeding into the window comparator formed by U2, U3, and U4B (Figure 35). U6 is used to establish the signal zero reference. The upper limit of the comparator is set above its offset and, therefore, the output pulses high whenever the input falls between 2.502 V and 2.497 V (or 0.005 V window) in this example. This output is AND’ed with the chip select signal such that the AD5290 updates whenever the signal crosses the window. To avoid a constant update of the device, the chip select signal should be programmed as two pulses, rather than as one shown in Figure 36. In Figure 35, the lower trace shows that the volume level changes from a quarter-scale to full-scale when a signal change occurs near the zero-crossing window. U1 C1 0.1F VDD R1 100k A W 5V CIN 10F IN ADP1611 RT B 1.23V R2 8.5k U2 CSS 22nF VOUT SW D1 FB SS L1 4.7H COMP GND COUT 10F RC 220k CC 150pF 04716-019 AD5290 Figure 34. Programmable Power Supply Rev. C | Page 18 of 20 Data Sheet AD5290 VIN C1 5V 1µF U1 R1 100kΩ +15V +5V R2 200Ω R4 90kΩ V+ ADCM371 V– 4 7408 –15V U3 V+ ADCM371 V– 5V U6 R3 100kΩ AD5290 +15V VSS W 100kΩ U4A CS CLK CLK SDI SDI U5 V+ VOUT V– B –15V CS GND 04716-028 V+ AD8541 V– 6 1 7408 2 5 R5 10kΩ A C2 0.1µF U4B +5V VDD C3 0.1µF U2 Figure 35. Audio Volume Control with Zipper Noise Reduction 1 2 04716-021 CHANNEL 1 FREQ = 20.25kHz 1.03V p-p Figure 36. Input (Trace 1) and Output (Trace 2) of the Circuit in Figure 35 (The Command of Volume Change May Occur at Any Time, but the Level Change Occurs Only Near the Zero-Crossing Window) Rev. C | Page 19 of 20 AD5290 Data Sheet OUTLINE DIMENSIONS 3.10 3.00 2.90 10 3.10 3.00 2.90 1 5.15 4.90 4.65 6 5 PIN 1 IDENTIFIER 0.50 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.30 0.15 0.23 0.13 6° 0° 0.70 0.55 0.40 COMPLIANT TO JEDEC STANDARDS MO-187-BA 091709-A 0.15 0.05 COPLANARITY 0.10 Figure 37. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5290YRMZ10 AD5290YRMZ10-R7 AD5290YRMZ50 AD5290YRMZ50-R7 AD5290YRMZ100 AD5290YRMZ100-R7 EVAL-AD5290EBZ 1 RAB (kΩ) 10 10 50 50 100 100 10 Temperature Range –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C –40°C to +125°C Package Description 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP Evaluation Board Z = RoHS Compliant Part. ©2005-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04716-0-11/11(C) Rev. C | Page 20 of 20 Package Option RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 Branding D4U D4U D4T D4T D4V D4V