December 1998 ML6696* 100BASE-X Fiber Physical Layer GENERAL DESCRIPTION FEATURES The ML6696 implements the complete physical layer of the Fast Ethernet 100BASE-X standard for fiber media. The device provides the MII (Media Independent Interface) for interface to upper-layer silicon. The ML6696 integrates the data quantizer and the LED driver, allowing the use of low cost optical PMD components. ■ 100BASE-FX physical layer with MII ■ Optimal 100BASE-SX solution (draft standard) ■ Integrated data quantizer (post-amplifier) ■ Integrated LED driver ■ 125MHz clock generation and recovery ■ 4B/5B encoding/decoding ■ Power-down mode The ML6696 includes 4B/5B encoder/decoder, 125MHz clock recovery/clock generation, LED driver, and a data quantizer. The device also offers a power down mode which results in total power consumption of less than 20mA. The ML6696 is suitable for the current 100BASE-FX IEEE 803.2u standard defined using 1300nm optics, as well as for the proposed 100BASE-SX standard defined using lower cost 820nm optics * Some Packages Are Obsolete BLOCK DIAGRAM CLKREF CLOCK SYNTHESIZER TXCLK TXER TXEN TXD3 TXD2 TXD1 IOUT PCS TRANSMIT STATE MACHINE AND 4B/5B ENCODER IOUT SERIALIZER LED DRIVER NRZ TO NRZI ENCODER RTSET TXD0 MDC MII SERIAL MANAGEMENT INTERFACE MDIO COL CRS ECLK CARRIER & COLLISION LOGIC EDIN INITIALIZATION INTERFACE EDOUT RXCLK RXER RXDV RXD3 RXD2 RXD1 PCS RECEIVE STATE MACHINE AND 4B/5B DECODER DESERIALIZER CLOCK & DATA RECOVERY NRZI TO NRZ ENCODER DATA QUANTIZER VIN+ (POST AMPLIFIER) VIN– LINK100 RXD0 CAPB CAPDC 1 ML6696 PIN CONFIGURATION TXEN TXD0 TXD1 TXD2 TXD3 AGND1 CLKREF AVCC1 EDIN ECLK EDOUT AVCC2 AGND2 ML6696 52-Pin PLCC (Q52) 7 6 5 4 3 2 1 52 51 50 49 48 47 TXER TXCLK RXD3 DGND1 RXD2 DVCC1 RXD1 DGND2 RXD0 RXCLK CRS COL DGND3 8 9 10 11 12 13 14 15 16 17 18 19 20 46 45 44 43 42 41 40 39 38 37 36 35 34 IOUT IOUT AGND3 RTSET AVCC3A AVCC3B AVCC4A AGND4A LINK100 AVCC4B AVCC4B VIN+ VIN– RXDV DVCC2 RXER MDC MDIO DGND4 DVCC5 DGND5 NC NC CAPDC CAPB AGND4B 21 22 23 24 25 26 27 28 29 30 31 32 33 TOP VIEW AGND2 AGND2 AGND2 AVCC2 EDOUT ECLK AVCC1 EDIN CLKREF AGND1 TXD3 TXD2 TXD1 TXD0 TXEN TXER ML6696 64-Pin TQFP (H64-10) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 TXCLK 1 48 IOUT RXD3 2 47 IOUT DGND1 3 46 IOUT DGND1 4 45 IOUT DGND1 5 44 AGND3 RXD2 6 43 AGND3 DVCC1 7 42 RTSET RXD1 8 41 DGND2 9 40 AVCC3A AVCC3B DGND2 10 39 DGND2 11 38 AVCC4A AGND4A RXD0 12 37 LINK100 RXCLK 13 36 CRS 14 35 AVCC4B AVCC4B COL 15 34 VIN+ DGND3 16 33 VIN– TOP VIEW 2 AGND4B AGND4B CAPB CAPDC NC NC DGND5 DGND5 DVCC5 DGND4 MDC MDIO RXER DVCC2 RXDV DGND3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ML6696 PIN DESCRIPTION (Pin Number in Parentheses is for PLCC Version) PIN NAME FUNCTION PIN 1 (9) TXCLK Transmit clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz TX bit clock. Data appearing at TXD<3:0> are clocked into the ML6696 on the rising edge of this clock. 16, 17 (20) DGND3 2 (10) RXD3 3, 4, 5, (11) DGND1 Receive data TTL output. Output is valid on RXCLK’s rising edge. RXD2 Receive data TTL output. Output is valid on RXCLK’s rising edge. 7 (13) DVCC1 Digital positive power supply 8 (14) RXD1 Receive data TTL output. Output is valid on RXCLK’s rising edge. 12 (16) RXD0 13 (17) RXCLK 14 (18) CRS 15 (19) COL Recovered receive clock TTL output. This 25MHz clock is phase-aligned with the internal 125MHz bit clock recovered from the signal received at VIN+/-. Receive data are clocked out at RXD<3:0> on the falling edges of this clock, and should be sampled on rising edges. RXCLK is phasealigned to CLKREF in the absence of a 100BASE-FX signal at VIN+/–. Carrier Sense TTL output. CRS goes high in the presence of nonidle signals at VIN+/-, or when the ML6696 is transmitting. CRS goes low when there is no transmit activity and receive is idle. In repeater or full-duplex mode, CRS goes high in the presence of nonidle signals at VIN+/– only. Collision Detected TTL output. COL goes high upon detection of a collision on the network, and remains high as long as the collision condition persists. COL is low when the ML6696 operates in full-duplex, repeater, or loopback modes. Digital ground Receive data valid TTL output. This output is high when the ML6696 is receiving a data packet. RXDV is valid on RXCLK’s rising edge. 19 (22) DVCC2 Digital positive power supply 20 (23) RXER Receive error TTL output. This output goes high to indicate error or invalid symbols within a packet, or corrupted idle between packets. RXER is valid on RXCLK’s rising edge. 21 (24) MDC MII Serial Management Interface clock TTL input. A clock at this pin clocks serial data into or out of the ML6696’s MII management registers through the MDIO pin. The maximum clock frequency at MDC is 2.5MHz. 22 (25) MDIO MII Serial Management Interface data TTL input/output. Serial data are written to and read from the management registers through this I/O pin. Input data is sampled on the rising edge of MDC. Output data is valid on MDC's rising edge 23 (26) DGND4 Digital ground 24 (27) DVCC5 Digital positive power supply 25, 26 (28) DGND5 Digital ground 27, 28 (29, 30) NC No connect Digital ground Receive data TTL output. Output is valid on RXCLK’s rising edge. FUNCTION 18 (21) RXDV Digital ground 6 (12) 9, 10, 11 (15) DGND2 NAME 29 (31) CAPDC Data quantizer offset-correction loop, offset-storage capacitor input pin. The capacitor tied between this pin and AVCC stores the amplified data quantizer offset voltage and also sets the dominant pole in the offset-correction loop. A 0.1µF surface mount is recommended. 3 ML6696 PIN DESCRIPTION PIN NAME 30 (32) CAPB 31, 32 (33) AGND4B (Pin Number in Parentheses is for PLCC Version) (Continued) FUNCTION PIN Data quantizer input bias bypass capacitor input. The capacitor tied between this pin and AVCC filters the quantizer’s internal input bias reference. A 0.1µF surface-mount capacitor is recommended. 47, 48 (46) IOUT Receive quantizer negative input. This input should be tied to AVCCQ through an AC coupling capacitor. (0.01µF recommended) 34 (35) V IN+ Receive quantizer positive input. This input receives 100BASE-FX signals from the network optical receiver through an AC coupling capacitor. (0.01µF recommended). Analog positive power supply 37 (38) LINK100 100BASE-FX link activity opendrain output. LINK100 pulls low when there is 100BASE-FX activity at VIN+/–. This output is capable of sinking sufficient current to directly drive a status LED in series with a current limiting resistor. 38 (39) AGND4A Analog ground 39 (40) AVCC4A Analog positive power supply 40 (41) AVCC3B Analog positive power supply 41 (42) AVCC3A Analog positive power supply 42 (43) RTSET Transmit level bias resistor. For 100BASE-FX, an external 2.32kW, 1% resistor connected between RTSET and AGND3 sets a precision constant bias current that gives a nominal output "on" current of 75mA at IOUT. 43, 44 (44) AGND3 45, 46 (45) IOUT 4 FUNCTION Transmit LED output. This opencollector current output drives NRZI waveforms into a network LED. 49, 50, 51 (47) AGND2 Analog ground 52 (48) AVCC2 Analog positive power supply 53 (49) EDOUT Initialization Interface data out CMOS input. With EDIN low at power up, EDOUT has no function. With EDIN floating at power up, EDOUT is the serial data input for configuration data from an EEPROM. With EDIN high at power up, EDOUT is the input for configuration data from an external microcontroller. (Table 1) 54 (50) ECLK Initialization Interface clock CMOS input/output. With EDIN low at power up, ECLK is inactive. With EDIN floating at power up, ECLK is the ML6696’s clock output for timing the configuration data from an external EEPROM. With EDIN high at power up, ECLK is the clock input for timing configuration data from an external microcontroller. (Table 1) 55 (51) EDIN Initialization Interface mode select and EEPROM interface data in CMOS input/output. EDIN selects one of three possible interface modes at power up. See the Initialization Interface section for more information. (Table 1) 56 (52) AVCC1 Analog positive power supply 57 (1) CLKREF Transmit clock TTL input. This 25MHz clock is the frequency reference for the internal TX PLL clock synthesizer and logic. This pin should be driven by an external 25MHz clock at TTL levels. 58 (2) AGND1 Analog ground 59 (3) TXD3 Transmit data TTL input. TXD<3:0> inputs accept TX data symbols from the MII. Data appearing at TXD<3:0> are clocked into the ML6696 on the rising edge of TXCLK. Analog ground 33 (34) V IN– 35, 36 (36, 37) AVCC4B NAME Analog ground Transmit LED output. This pin connects through an external 15W resistor to AVCC when the part is used to drive a network LED. ML6696 PIN DESCRIPTION (Pin Number in Parentheses is for PLCC Version) (Continued) PIN NAME FUNCTION PIN NAME FUNCTION 60 (4) TXD2 Transmit data TTL input. TXD<3:0> inputs accept TX data symbols from the MII. Data appearing at TXD<3:0> are clocked into the ML6696 on the rising edge of TXCLK. 63 (7) TXEN Transmit enable TTL input. Driving this input high indicates to the ML6696 that transmit data are present at TXD<3:0>. TXEN edges should be synchronous with TXCLK. 61 (5) TXD1 Transmit data TTL input. TXD<3:0> inputs accept TX data symbols from the MII. Data appearing at TXD<3:0> are clocked into the ML6696 on the rising edge of TXCLK. 64 (8) TXER Transmit error TTL input. Driving this pin high with TXEN also high causes the part to continuously transmit an H symbol (00100). When TXEN is low, TXER has no effect. 62 (6) TXD0 Transmit data TTL input. TXD<3:0> inputs accept TX data symbols from the MII. Data appearing at TXD<3:0> are clocked into the ML6696 on the rising edge of TXCLK. 5 ML6696 ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. Storage Temperature ................................. –65ºC to 150ºC Lead Temperature (Soldering, 10 sec) ..................... 260ºC Thermal Resistance (qJA) TQFP ............................................................... 52°C/W PLCC ............................................................... 40°C/W VCC Supply Voltage Range ............................ –0.3V to 6V Input Voltage Range Digital Inputs ........................................... –0.3V to VCC VIN+, VIN-, CLKREF, CAPB, CAPDC ........ –0.3V to VCC Output Current IOUT, IOUT ........................................................ 90mA All Other Outputs ............................................... 10mA Junction Temperature .................................... 0ºC to 125ºC OPERATING CONDITIONS Temperature Range ....................................... 0ºC to 70ºC RTSET .......................................................... 2.32kW ±1% VCC Supply Voltage .............................. ........... 5V ±5% All VCC supply pins must be within 0.1V of each other. All GND pins must be within 0.1V of each other. DC ELECTRICAL CHARACTERISTICS Unless otherwise specified, VCC = 5V ±5%, TA = Operating Temperature Range (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS TTL INPUTS (TXD<3:0>, CLKREF, MDC, MDIO, TXEN, TXER) VIL Input Low Voltage IIL = –400µA -0.3 0.8 V VIH Input High Voltage IIH = 100µA 2.0 VCC+0.3 V IIL Input Low Current VIN = 0.4V -200 IIH Input High Current VIN = 2.4V µA 100 µA 0.4 V TTL OUTPUTS (RXD<3:0>, RXCLK, RXDV, RXER, CRS, COL, MDIO, TXCLK) VOL Output Low Voltage IOL = 4mA VOH Output High Voltage IOH = –4mA 2.4 V CMOS INPUTS (EDIN, EDOUT, ECLK) V ILC Input Low Voltage V IHC Input High Voltage 0.2 ´ VCC 0.8 ´ VCC V V CMOS OUTPUTS (ECLK) VOLC Output Low Voltage IOL = 2mA V OHC Output High Voltage IOL = –2mA 0.1 ´ VCC 0.9 ´ VCC V V RECEIVER (VIN+, VIN–) 6 V ICM Input Common-Mode Voltage VCC = 5V VID Differential Input Voltage Range 3.5 1600 mVP-P RIDR Differential Input Resistance 500 1000 W V SDA Signal Detect Assertion Threshold 8 12 mVP-P AHYST Input Hysteresis 1.5 2 dB Peak-to-Peak Non-idle Signal Level at VIN+/- 2.5 V ML6696 DC ELECTRICAL CHARACTERISTICS SYMBOL (Continued) PARAMETER CONDITIONS MIN TYP MAX UNITS 67.5 75 82.5 mA 0.1 mA 540 594 µA 200 295 mA 20 mA MAX UNITS 11 ns TRANSMITTER (IOUT, IOUT) ILEDH IOUT High Output Current RTSET = 2.32kW ±1% ILEDL Low Output Current RTSET = 2.32kW ±1% IRT RTSET Input Current RTSET = 2.32kW ±1% 486 POWER SUPPLY CURRENT ICC I CCPD Supply Current, 100BASE-FX, Transmitting Current into All VCC Pins Supply Current, Power-Down Mode Current into All VCC Pins AC ELECTRICAL CHARACTERISTICS Unless otherwise specified, VCC = 5V ±5%, TA = Operating Temperature Range (Note 1) SYMBOL PARAMETER CONDITIONS MIN TYP TRANSMITTER tCLK CLKREF – TXCLK Delay 5 tTXP Transmit Bit Delay Note 2 10.5 bit times tTR/F IOUT Rise /Fall Time Note 3 2 ns t TDC IOUT Output Duty Cycle Disotrtion Note 3 0.5 ns tRXDC Receive Bit Delay (CRS) Note 3 15.5 bit times tRXDR Receive Bit Delay (RXDV) Note 4 25.5 bit times 50 ppm –0.5 RECEIVER MII INTERFACE XNTOL CLKREF Input Clock Frequency Tolerance 25MHz Frequency –50 t TPWH TXCLK Pulse Width High 14 ns t TPWL TXCLK Pulse Width Low 14 ns tRPWH RXCLK Pulse Width High 14 ns tRPWL RXCLK Pulse Width Low 14 ns t TPS Setup Time, TXD<3:0> Data Valid to TXCLK Rising Edge Note 5 5 ns t TPH Hold time, TXD<3:0> Data Valid After TXCLK Rising Edge Note 5 0 ns tRCS Time That RXD<3:0> Data are Valid Before RXCLK Rising Edge Note 6, 7 10 ns tRCH Time That RXD<3:0> Data are Valid After RXCLK Rising Edge Note 6, 7 10 ns tRPCR RXCLK 10%-90% Rise Time 6 ns tRPCF RXCLK 90%-10% Fall Time 6 ns 7 ML6696 AC ELECTRICAL CHARACTERISTICS SYMBOL PARAMETER (Continued) CONDITIONS MIN TYP MAX UNITS MII MANAGEMENT INTERFACE (MDC, MDIO) tSPWS Write Setup Time, MDIO Data Valid to MDC Rising Edge (1.4V Point) 10 ns tSPWH Write Hold Time, MDIO Data Valid After MDC Rising Edge (1.4V Point) 10 ns tSPRS Read Setup Time, MDIO Data Valid to MDC Rising Edge (1.4V Point) 100 ns tSPRH Read Hold Time, MDIO Data Valid After MDC Rising Edge (1.4V Point) 0 ns tCPER Period of MDC 400 ns t CPW Pulsewidth of MDC Positive or Negative Pulses 160 ns EEPROM INTERFACE (ECLK, EDIN, EDOUT) t PW1 ECLK Positive Pulsewidth EDIN Floating (EEPROM Mode) 900 ns t PW2 ECLK Negative Pulsewidth EDIN Floating (EEPROM Mode) 900 ns tPER1 ECLK Period EDIN Floating (EEPROM Mode) 1800 ns t DV1 EDOUT Data Valid Time After ECLK Rising Edge EDIN Floating (EEPROM Mode) tPER2 ECLK Period EDIN High (Microcontroller Mode) 5000 ns t PW3 ECLK Positive Pulsewidth EDIN High (Microcontroller Mode) 2000 ns t PW4 ECLK Negative Pulsewidth EDIN High (Microcontroller Mode) 2000 ns tS1 ECLK Data Setup Time EDIN High (Microcontroller Mode) 10 ns t H1 ECLK Data Hold Time EDIN High (Microcontroller Mode) 10 ns 900 Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions. Note 2: From first rising edge of TXCLK after TXEN goes high, to first bit of J at the MDI. Note 3: From first bit of J at the MDI, to CRS. Note 4: From first bit of J at the MDI, to first rising edge of RXCLK after RXDV goes high. Note 5: Measured between the time that TXD0-3 transition above or below the region 0.8V–2.0V, and the time that TXCLK rises above 0.8V. Note 6: Measured between the time that RXD0-3 transition above or below the region 0.8V–2.0V, and the time that RXCLK rises above 0.8V. Note 7: Measured using a 15pF load to ground. 8 ns ML6696 TXCLKIN tTPWH tTPWL TXCLK TXD<3:0> TXER TXEN tTPS tTPH Figure 1. MII Transmit Timing tRPCR tRPCF RXCLK RXD<3:0> RXER RXDV tRCS tRCH Figure 2. MII Receive Timing MDC MDIO tSPWS tSPWH Figure 3. MII Management Interface Write Timing 9 ML6696 tCPER MDC tSPRH tSPRS tCPW tCPW MDIO Figure 4. MII Management Interface Read Timing tPW1 ECLK (DRIVEN BY ML6696) EDIN (DRIVEN BY ML6696) 01 SB 1 02 OP1 1 03 OP0 0 tPW2 04 A5 0 05 A4 0 06 tPER1 07 A3 0 08 A2 0 A1 0 09 10 11 12 13 26 A0 0 EDOUT (DRIVEN BY EEPROM) D0 D1 D2 D3 D14 tDV1 16 BITS DATA ADDRESS Figure 5. EEPROM Interface Timing tPW3 01 tPER2 02 16 ECLK (INPUT TO ML6696) tS1 tPW4 EDOUT (INPUT TO ML6696) H Figure 6. MII Management Interface Read Timing 10 D15 ML6696 FUNCTIONAL DESCRIPTION FIBER OPTIC TRANSMITTER ML6696 PHY MANAGEMENT FUNCTIONS The on-chip transmit PLL converts a 25MHz TTL-level clock at CLKREF to an internal 125MHz bit clock. TXCLK from the ML6696 clocks transmit data from the MAC into the ML6696’s TXD<3:0> input pins upon assertion of TXEN. Data from the TXD<3:0> inputs are 5-bit encoded and converted from parallel to serial form at the 125MHz clock rate. The ML6696 drives corresponding NRZI data out from its LED driver. The LED driver at IOUT is a current mode switch which develops the output light by sinking current through the network LED into IOUT. RTSET’s value determines the output current: The ML6696 has management functions controlled by the register locations given in Table 3 (page 12). There are two 16-bit management registers, with several unused locations. Register 0 is the basic control register (read/ write). Register 1 is the basic status register (read-only). The ML6696 powers on with all management register bits set to their default values. RTSET = . V 125 IOUT ´ 140W (1) where IOUT is the desired output current. Driving TXEN low will cause the ML6696’s transmitter to enter the idle state and output 62.5MHz idle signal. Driving TXER high when TXEN is high causes the H symbol (00100) to appear in the transmitted data stream. The media access controller asserts TXER synchronously with TXCLK’s rising edge, and the H symbol appears in place of valid symbols in the current frame. FIBER OPTIC RECEIVER The data quantizer accepts data at the VIN+/– pins that is above the internally-set 10mVpp threshold (typical). The ML6696’s status and control register addresses and functions match those described for the MII in IEEE 802.3u section 22. IEEE 802.3u specifies the management data frame structure in section 22.2.4.4. See IEEE 802.3u section 22.2.4 for a discussion of MII management functions and status/control register definitions. INITIALIZATION INTERFACE The ML6696 has an Initialization Interface to allow register programming that is not supported by the MII Management Interface. The intitialization data is loaded at power-up and cannot be changed afterwards. The pin EDIN selects one of three possible programming modes. The Initialization Register bit assignment is shown in Table 2. EEPROM PROGRAMMING The receiver will assert RXER high if it detects errors in the receive data or idle stream. With EDIN floating (set to a high impedance), the ML6696 reads the 16 configuration bits from an external serial EEPROM (93LC46 or similar) using the industrystandard 3-wire serial I/O protocol. After power up, the ML6696 automatically generates the address at EDIN and the clock at ECLK to read out the 16 configuration bits. The EEPROM generates the configuration bit stream at EDOUT, synchronized with ECLK. Interface timing is shown in Figure 5. It is important to note that the ML6696 expects LSBs first, whereas the 93LC46 shifts MSBs out first. Therefore, the data pattern must be reversed before programming it into the EEPROM. COLLISION AND CRS MICROCONTROLLER PROGRAMMING COL goes high to indicate simultaneous 100BASE-FX receive and transmit activity (a collision). CRS goes high whenever there is either receive or transmit activity in default mode, or only when there is receive activity in repeater or full-duplex mode. With EDIN high, the ML6696 expects the 16 configuration bits transfered directly at EDOUT, synchronized with the first 16 clock rising edges provided externally at ECLK after power-up. This mode is useful with a small microcontroller; one controller can program several ML6696 parts by selectively toggling their ECLK pins. Interface timing is shown in Figure 6. The receive PLL extracts clock from the quantizer’s output, providing jitter attenuation, and clocks the signal through the serial-to-parallel converter. The resulting 5-bit symbols are aligned and decoded, and appear at RXD<3:0>. The ML6696 asserts RXDV when it’s ready to present properly decoded receive data at RXD<3:0>. The extracted clock appears at RXCLK. The receiver strips out 62.5MHz idle between data packets. CLOCK INPUT The ML6696 requires an accurate 25MHz reference at CLKREF for internal clock generation (±50ppm, see parameter XNTOL). ML6696 HARD-WIRED DEFAULT With EDIN low, the ML6692 responds to MII PHYAD 00000 only. "ISODIS" bit and "REPEATER" bit are 0. 11 ML6696 FUNCTION OF RELATED PINS EDIN Floating (EEPROM ADDR) High MODE EEPROM Microcontroller Low Hardwired ECLK EDOUT ECLK (Output clock to EEPROM) EDOUT (Input data from EEPROM) ECLK EDOUT (Input clock from Microcontroller) (Input data from Microcontroller) No Effect No Effect Table 1. ML6696 Pin Function BIT(S) NAME DESCRIPTION i.15 i.14 PHY A4 PHY A3 PHY address bit 4 PHY address bit 3 0 0 i.13 PHY A2 PHY address bit 2 0 i.12 PHY A1 PHY address bit 1 0 i.11 PHY A0 PHY address bit 0 0 i.10 - i.8 Not Used i.7 ISODIS i.6 REPEATER i.5 - i.0 Isolate bit disable (bit 0.10) 0 Repeater mode: when set to 1, CRS is only asserted when receiving non-idle signal at IN+/–, and ML6696 is forced to half duplex mode. 0 Not Used Table 2. Initialization Interface Register 12 DEFAULT ML6696 BIT(S) NAME 1.14 100BASE-X Full Duplex 100BASE-X Half Duplex 1.13 1.12-1.3 1.2 Link Status 1.1 - 1.0 0.15 Reset 0.14 Loopback 0.13 Manual Speed Select 0.12 0.11 Power down 0.10 Isolate 0.9 0.8 Duplex mode 0.7 Collision Test 0.6 - 0.0 DESCRIPTION R/W DEFAULT 1=Full duplex 100BASE-X capability 0=No full duplex 100BASE-X capability 1=Half duplex 100BASE-X capability 0=No half duplex 100BASE-X capability Not used 1=One and only one PHY-specific link is up 0=Link is down Not used 1=Reset registers 0 and 1 to default values 0=Normal operation 1=PMD loopback mode 0=Normal operation 1=100Mb/s 0=10Mb/s Not used RO i.6 RO 1 RO RO,LL 0 0 RO R/W, SC 0 0 R/W 0 R/W 1 RO 0 R/W 0 R/W i.7 Not used RO 0 1=Full duplex select 0=Half duplex select 1=Enable COL signal test 0=Normal operation R/W i.6 R/W 0 Not Used RO 0 1=Power down 0=Normal operation 1=Electrically isolate the ML6696 from MII 0=Normal operation Table 3. Management Register Function Bit Locations (Registers 0, 1) 13 ML6696 C3 0.1µF 5V VCC U2 EC1400SJ-TS-25MHz 25MHz OSC 1 4 NC VCC 2 3 GND OUT P1 MII CONNECTOR DGND VCC GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND VCC VCC CRS COL TXD3 TXD2 TXD1 TXD0 TXEN TXCK TXER RXER RXCK RXDV RXD0 RXD1 RXD2 RXD3 MDC MDIO VCC DVCC 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 U6 93LC46B 1 CS VCC 2 SK NC 3 DI NC 4 D0 DGND AVCC 8 7 6 5 C9 0.1µF R6 15Ω C13 0.1µF C10 0.1µF C6, 0.1µF C29, 0.001µF C26, 10µF TXEN TXD0 TXD1 TXD2 TXD3 AGND1 CLKREF AVCC1 EDIN ECLK EDOUT AVCC2 AGND2 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 DVCC TXER TXCLK RXD3 DGND1 RXD2 DVCC1 RXD1 DGND2 RXD0 RXCLK CRS COL DGND3 C17 0.1µF 5V VCC C16 0.1µF DVCC DVCC D3 FX_RCVLED D2 FX_TXLED U3 ML6696CQ C15 0.1µF R7, 3kΩ AGND IOUT IOUT AGND3 RTSET AVCC3A AVCC3B AVCC4A AGND4A LINK100 AVCC4B AVCC4B VIN+ VIN– RXDV DVCC2 RXER MDC MDIO DGND4 DVCC5 DGND5 NC NC CAPDC CAPB AGND4B DVCC C4 0.1µF C12 0.1µF R8* AGND C13 0.1µF C30 0.01µF AGNDQ C5 0.1µF AVCCQ DVCC U4* 1 NC CATHODE 4 NC NC 5 NC ANODE1 8 NC ANODE2 R1 500Ω C14 0.1µF C31 0.01µF U5* 1 2 NC ASIGOUT 4 3 NC GND 5 7 NC GND 8 6 NC VCC R4 470Ω DVCC R4 470Ω R4 100kΩ 1 2 3 4 5 6 7 0.1µF D5 14 13 12 11 10 9 8 U1 74HC04 AVCC AVCCQ D1 LED VCC AGNDQ D4 3 7 2 6 C2 22nF R5 100kΩ C2 22nF AVCCQ FB4 C25 10µF C28 0.01µF C22 0.1µF C20 0.1µF C8 0.1µF FB3 FB1 C25 10µF DGND C28 0.01µF C22 0.1µF C20 0.1µF FB2 AVCC C24 10µF AGND C8 0.1µF U4* U5* R8* AVCCQ C24 10µF 850nm HFBR-1414 HFBR-2416 2.87kW AGNDQ 1300nm HFBR-1312T HFBR-2316T 2.32kW Figure 7. ML6696 Typical Application Schematic 14 ML6696 PHYSICAL DIMENSIONS inches (millimeters) Package: Q52 52-Pin PLCC 0.785 - 0.795 (19.94 - 20.19) 0.042 - 0.056 (1.07 - 1.42) 0.750 - 0.754 (19.05 - 19.15) 0.025 - 0.045 (0.63 - 1.14) (RADIUS) 1 PIN 1 ID 0.042 - 0.048 (1.07 - 1.22) 14 40 0.750 - 0.754 0.785 - 0.795 (19.05 - 19.15) (19.94 - 20.19) 0.600 BSC (15.24 BSC) 0.690 - 0.730 (17.53 - 18.54) 27 0.009 - 0.011 (0.23 - 0.28) 0.050 BSC (1.27 BSC) 0.026 - 0.032 (0.66 - 0.81) 0.013 - 0.021 (0.33 - 0.53) 0.165 - 0.180 (4.06 - 4.57) 0.100 - 0.110 (2.54 - 2.79) 0.148 - 0.156 (3.76 - 3.96) SEATING PLANE Package: H64-10 64-Pin (10 x 10 x 1mm) TQFP 0.472 BSC (12.00 BSC) 0º - 8º 0.394 BSC (10.00 BSC) 0.003 - 0.008 (0.09 - 0.20) 49 1 PIN 1 ID 0.394 BSC (10.00 BSC) 0.472 BSC (12.00 BSC) 33 0.018 - 0.030 (0.45 - 0.75) 17 0.020 BSC (0.50 BSC) 0.007 - 0.011 (0.17 - 0.27) 0.048 MAX (1.20 MAX) SEATING PLANE 0.037 - 0.041 (0.95 - 1.05) 15 ML6696 ORDERING INFORMATION PART NUMBER TEMPERATURE RANGE PACKAGE ML6696CH (Obsolete) 0°C to 70°C 64-Pin TQFP (H64-10) ML6696CQ 0°C to 70°C 52-Pin PLCC (Q52) © Micro Linear 2000. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners. Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223; 5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending. 2092 Concourse Drive San Jose, CA 95131 Tel: (408) 433-5200 Fax: (408) 432-0295 www.microlinear.com 16 DS6696-01