PD -95314A
IRFR5410PbF
IRFU5410PbF
l
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Ultra Low On-Resistance
P-Channel
Surface Mount (IRFR5410)
Straight Lead (IRFU5410)
Advanced Process Technology
Fast Switching
Fully Avalanche Rated
Lead-Free
HEXFET® Power MOSFET
D
VDSS = -100V
RDS(on) = 0.205Ω
G
ID = -13A
S
Description
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
and reliable device for use in a wide variety of applications.
The D-Pak is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU series) is for through-hole mounting
applications. Power dissipation levels up to 1.5 watts are
possible in typical surface mount applications.
D-Pak
TO-252AA
I-Pak
TO-251AA
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
V GS
EAS
IAR
EAR
dv/dt
TJ
TSTG
Parameter
Max.
Continuous Drain Current, VGS @ -10V
Continuous Drain Current, VGS @ -10V
Pulsed Drain Current
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
-13
-8.2
-52
66
0.53
± 20
194
-8.4
6.3
-5.0
-55 to + 150
Units
A
W
W/°C
V
mJ
A
mJ
V/ns
300 (1.6mm from case )
°C
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
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Junction-to-Case
Junction-to-Ambient (PCB mount)**
Junction-to-Ambient
Typ.
Max.
Units
1.9
50
110
°C/W
1
12/13/04
IRFR/U5410PbF
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Min.
-100
-2.0
3.2
Typ.
-0.12
15
58
45
46
LD
Internal Drain Inductance
4.5
LS
Internal Source Inductance
7.5
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
760
260
170
V(BR)DSS
IDSS
IGSS
Drain-to-Source Leakage Current
Max. Units
Conditions
V
VGS = 0V, ID = -250µA
V/°C Reference to 25°C, ID = -1.0mA
0.205
Ω
VGS = -10V, I D = -7.8A
-4.0
V
VDS = VGS, ID = -250µA
S
VDS = -50V, ID = -7.8A
-25
VDS = -100V, VGS = 0V
µA
-250
VDS = -80V, VGS = 0V, TJ = 150°C
100
VGS = 20V
nA
-100
VGS = -20V
58
ID = -8.4A
8.3
nC VDS = -80V
32
VGS = -10V, See Fig. 6 and 13
VDD = 50V
ID = -8.4A
ns
RG = 9.1Ω
RD =6.2Ω, See Fig. 10
D
Between lead,
6mm (0.25in.)
nH
G
from package
and center of die contact
S
VGS = 0V
pF
VDS = -25V
= 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
ISM
V SD
t rr
Qrr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Starting TJ = 25°C, L = 6.4mH
RG = 25Ω, IAS = -7.8A. (See Figure 12)
ISD ≤ -7.8A, di/dt ≤ 200A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
-13
showing the
A
G
integral reverse
-52
p-n junction diode.
S
-1.6
V
TJ = 25°C, IS = -7.8A, VGS = 0V
130 190
ns
TJ = 25°C, IF = -8.4A
650 970
nC di/dt = 100A/µs
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Pulse width ≤ 300µs; duty cycle ≤ 2%.
This is applied for I-PAK, LS of D-PAK is measured between
lead and center of die contact
Uses IRF9530N data and test conditions.
** When mounted on 1" square PCB (FR-4 or G-10 Material ) .
For recommended footprint and soldering techniques refer to application note #AN-994
2
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IRFR/U5410PbF
100
100
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
BOTTOM -4.5V
VGS
-15V
-10V
-8.0V
-7.0V
-6.0V
-5.5V
-5.0V
BOTTOM -4.5V
10
TOP
-I D , Drain-to-Source Current (A)
-I D , Drain-to-Source Current (A)
TOP
1
-4.5V
0.1
10
-4.5V
1
20µs PULSE WIDTH
TJ = 25 °C
0.01
0.1
1
10
0.1
0.1
100
-VDS , Drain-to-Source Voltage (V)
TJ = 150 ° C
1
V DS = 10V
20µs PULSE WIDTH
5
6
7
8
9
10
-VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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RDS(on) , Drain-to-Source On Resistance
(Normalized)
-I D , Drain-to-Source Current (A)
2.5
TJ = 25 ° C
4
10
100
Fig 2. Typical Output Characteristics
100
0.1
1
-VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
10
20µs PULSE WIDTH
TJ = 150 °C
ID = -14A
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
V GS = -10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
IRFR/U5410PbF
2000
1200
-VGS , Gate-to-Source Voltage (V)
1600
C, Capacitance (pF)
20
V GS = 0V,
f = 1MHz
C iss = Cgs + C gd , Cds SHORTED
C rss = C gd
C oss = C ds + C gd
Ciss
800
Coss
Crss
400
ID = -8.4A
15
10
5
FOR TEST CIRCUIT
SEE FIGURE 13
0
0
0
A
1
10
10
100
30
40
50
60
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
100
OPERATION IN THIS AREA LIMITED
BY RDS(on)
TJ = 150 ° C
-II D , Drain Current (A)
-ISD , Reverse Drain Current (A)
20
QG, Total Gate Charge (nC)
-VDS , Drain-to-Source Voltage (V)
10
TJ = 25 °C
1
0.1
0.2
100
10us
100us
10
0.8
1.4
2.0
Fig 7. Typical Source-Drain Diode
Forward Voltage
2.6
1ms
TC = 25° C
TJ = 150° C
Single Pulse
V GS = 0 V
-VSD ,Source-to-Drain Voltage (V)
4
VDS = -80V
VDS = -50V
VDS = -20V
1
1
10ms
10
100
1000
-VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRFR/U5410PbF
15
VGS
12
-ID , Drain Current (A)
RD
VDS
D.U.T.
RG
+
9
VDD
-10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
6
Fig 10a. Switching Time Test Circuit
3
td(on)
tr
t d(off)
tf
VGS
10%
0
25
50
75
100
125
150
TC , Case Temperature ( °C)
90%
VDS
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
1 D = 0.50
0.20
0.10
PDM
0.05
0.1
0.02
0.01
0.01
0.00001
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
IRFR/U5410PbF
L
VDS
- V
V DD
+ DD
D.U.T
RG
A
IAS
-20V
tp
DRIVER
0.01Ω
15V
Fig 12a. Unclamped Inductive Test Circuit
I AS
EAS , Single Pulse Avalanche Energy (mJ)
500
ID
-3.5A
-4.9A
BOTTOM -7.8A
TOP
400
300
200
100
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
tp
V(BR)DSS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
50KΩ
QG
12V
-10V
.2µF
.3µF
QGS
QGD
D.U.T.
+VDS
VGS
VG
-3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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IRFR/U5410PbF
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T*
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
-
-
+
RG
• dv/dt controlled by RG
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
VGS
*
+
-
VDD
Reverse Polarity of D.U.T for P-Channel
Driver Gate Drive
P.W.
Period
D=
P.W.
Period
[VGS=10V ] ***
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
[VDD]
Forward Drop
Inductor Curent
Ripple ≤ 5%
[ISD ]
*** VGS = 5.0V for Logic Level and 3V Drive Devices
Fig 14. For P-Channel HEXFETS
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7
IRFR/U5410PbF
D-Pak (TO-252AA) Package Outline
Dimensions are shown in millimeters (inches)
D-Pak (TO-252AA) Part Marking Information
EXAMPLE: THIS IS AN IRFR120
WITH ASSEMBLY
LOT CODE 1234
ASSEMBLED ON WW 16, 1999
IN THE ASSEMBLY LINE "A"
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
Note: "P" in assembly line position
indicates "Lead-Free"
IRFU120
12
916A
34
ASSEMBLY
LOT CODE
DATE CODE
YEAR 9 = 1999
WEEK 16
LINE A
OR
PART NUMBER
INTERNATIONAL
RECTIFIER
LOGO
IRFU120
12
ASSEMBLY
LOT CODE
8
34
DATE CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
YEAR 9 = 1999
WEEK 16
A = ASSEMBLY SITE CODE
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IRFR/U5410PbF
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
EXAMPLE: T HIS IS AN IRFU120
WIT H AS S EMB LY
LOT CODE 5678
AS S EMBLED ON WW 19, 1999
IN T HE AS S EMB LY LINE "A"
INT ERNAT IONAL
RECT IFIER
LOGO
PART NUMB ER
IRF U120
919A
56
78
ASS EMB LY
LOT CODE
Note: "P" in as sembly line
position indicates "Lead-Free"
DAT E CODE
YEAR 9 = 1999
WEEK 19
L INE A
OR
INTERNAT IONAL
RECTIF IER
LOGO
PART NUMBER
IRFU120
56
AS S EMBLY
LOT CODE
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78
DATE CODE
P = DES IGNATES LEAD-FREE
PRODUCT (OPTIONAL )
YEAR 9 = 1999
WEEK 19
A = AS S EMBL Y S IT E CODE
9
IRFR/U5410PbF
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .476 )
11.9 ( .469 )
FEED DIRECTION
TRL
16.3 ( .641 )
15.7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FEED DIRECTION
NOTES :
1. CONTROLLING DIMENSION : MILLIMETER.
2. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS ( INCHES ).
3. OUTLINE CONFORMS TO EIA-481 & EIA-541.
13 INCH
16 mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.12/04
10
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Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/