Cypress CY2XL11ZXCT 100 mhz lvds clock generator Datasheet

CY2XL11
100 MHz LVDS Clock Generator
Features
Functional Description
■
One LVDS Output Pair
■
Output Frequency: 100 MHz
■
External Crystal Frequency: 25 MHz
■
Low RMS Phase Jitter at 100 MHz, using 25 MHz Crystal
(637 kHz to 10 MHz): 0.53 ps (Typical)
■
Pb-free 8-Pin TSSOP Package
■
Supply Voltage: 3.3V or 2.5V
■
Commercial Temperature Range
The CY2XL11 is a PLL (Phase Locked Loop) based high
performance clock generator with a crystal oscillator interface
and one LVDS output pair. It is optimized to generate PCI
Express, FC, and other high performance clock frequencies. It
also produces an output frequency that is four times the crystal
frequency. It uses Cypress’s low noise VCO technology to
achieve less than 1 ps typical RMS phase jitter, that meets high
performance systems’ jitter requirements.
Logic Block Diagram
XIN
External
Crystal
CRYSTAL
OSCILLATOR
LOW-NOISE
PLL
OUTPUT
DIVIDER
CLK
CLK#
XOUT
OE
Pinouts
Figure 1. Pin Diagram - 8-Pin TSSOP
VDD
VSS
XOUT
XIN
1
2
3
4
8
7
6
5
VDD
CLK
CLK#
OE
Table 1. Pin Definition - 8-Pin TSSOP
Pin Number
Pin Name
I/O Type
1, 8
VDD
Power
3.3V or 2.5V power supply. All supply current flows through pin 1
2
VSS
Power
Ground
3, 4
XOUT, XIN
XTAL output and input
5
OE
CMOS input
Output Enable. When HIGH, the output is enabled. When LOW, the
output is high impedance
6,7
CLK#, CLK
LVDS output
Differential clock output
Cypress Semiconductor Corporation
Document Number: 001-42886 Rev. *D
•
Description
Parallel resonant crystal interface
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 18, 2009
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CY2XL11
Frequency Table
Input Crystal Frequency (MHz)
PLL Multiplier Value
Output Frequency (MHz)
25
4
100
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply Voltage
–0.5
4.4
V
VIN[1]
Input Voltage, DC
Relative to VSS
–0.5
VDD + 0.5
V
Non operating
–65
150
°C
–
135
°C
–
V
TS
Temperature, Storage
TJ
Temperature, Junction
ESDHBM
ESD Protection (Human Body Model)
JEDEC STD 22-A114-B
UL–94
Flammability Rating
At 1/8 in.
V–0
ΘJA[2]
Thermal Resistance, Junction to
Ambient
0 m/s airflow
100
1 m/s airflow
91
2.5 m/s airflow
87
2000
°C/W
Operating Conditions
Parameter
VDD
Min
Max
Unit
3.3V Supply Voltage
Description
3.135
3.465
V
2.5V Supply Voltage
2.375
2.625
V
TA
Ambient Temperature
–5
70
°C
TPU
Power up time for all VDD to reach minimum specified voltage (ensure power
ramps is monotonic)
0.05
500
ms
DC Electrical Characteristics
Parameter
IDD[4]
Description
Test Conditions
Power Supply Current with output VDD = 3.465V, OE = VDD, output terminated
terminated
VDD = 2.625V, OE = VDD, output terminated
VOD[6]
LVDS Differential Output Voltage
ΔVOD[6]
Change in VOD between Comple- VDD = 3.3V or 2.5V, RTERM = 100Ω between
mentary Output States
CLK and CLK#
VOS[7]
LVDS Offset Output Voltage
ΔVOS
Change in VOS between Comple- VDD = 3.3V or 2.5V, RTERM = 100Ω between
mentary Output States
CLK and CLK#
IOZ
Output Leakage Current
VDD = 3.3V or 2.5V, RTERM = 100Ω between
CLK and CLK#
VDD = 3.3V or 2.5V, RTERM = 100Ω between
CLK and CLK#
Three-state output, unterminated, measured
on one pin while floating the other pin, OE =
VSS
Min
Typ
Max
Unit
–
–
120
mA
–
–
115
mA
247
–
454
mV
–
–
50
mV
1.125
–
1.375
V
–
–
50
mV
–35
–
35
μA
Notes
1. The voltage on any input or IO pin cannot exceed the power pin during power up.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metalization. No vias are included in the model.
3. Outputs are terminated with 100Ω between CLK and CLK#. Refer to Figure 8 on page 5.
4. IDD includes ~4 mA of current that is dissipated externally in the output termination resistor.
5. Not 100% tested, guaranteed by design and characterization.
6. Refer to Figure 2 on page 4.
7. Refer to Figure 3 on page 4.
Document Number: 001-42886 Rev. *D
Page 2 of 7
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CY2XL11
DC Electrical Characteristics (continued)
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VIH
Input High Voltage, OE pin
0.7*VDD
–
–
V
VIL
Input Low Voltage, OE pin
–
–
0.3*VDD
V
IIH
Input High Current, OE pin
OE = VDD
–
–
115
µA
IIL
Input Low Current, OE pin
OE = VSS
–50
–
–
µA
CIN
Input Capacitance, OE pin
–
15
–
pF
CINX
Pin Capacitance, XIN & XOUT
–
4.5
–
pF
AC Electrical Characteristics[3]
Parameter
Description
Min
Typ
Max
Unit
–
100
–
MHz
–
0.5
1.0
ns
–
0.53
–
ps
FOUT
Output Frequency
TR, TF[8]
Output Rise or Fall time
20% to 80% of full output swing
TJitter(φ)[11]
RMS Phase Jitter (Random)
FOUT =100 MHz, (637 kHz–10 MHz)
TDC[9]
TOHZ[10]
Duty Cycle
Measured at zero crossing point
45
–
55
%
Output Disable Time
Time from falling edge on OE to
stopped outputs (Asynchronous)
–
–
100
ns
TOE[10]
Output Enable Time
Time from rising edge on OE to
outputs at a valid frequency
(Asynchronous)
–
–
120
ns
TLOCK
Startup Time
Time for CLK to reach valid
frequency measured from the time
VDD = VDD(min.)
–
–
5
ms
Min
Max
Unit
Crystal Characteristics
Parameter
Description
Mode of Oscillation
Fundamental
F
Frequency
25
25
MHz
ESR
Equivalent Series Resistance
–
50
Ω
CS
Shunt Capacitance
–
7
pF
Notes
8. Refer to Figure 4 on page 4.
9. Refer to Figure 5 on page 4.
10. Refer to Figure 6 on page 4.
11. Refer to Figure 7 on page 5.
Document Number: 001-42886 Rev. *D
Page 3 of 7
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CY2XL11
Switching Waveforms
Figure 2. Output Voltage Swing
CLK#
VOD1
VOD2
CLK
ΔVOD = VOD1 - VOD2
Figure 3. Output Offset Voltage
CLK
50Ω
50Ω
CLK#
V OS
Figure 4. Output Rise or Fall Time
CLK#
CLK
80%
80%
20%
20%
TR
TF
Figure 5. Duty Cycle Timing
CLK
TDC =
CLK#
TPW
TPERIOD
TPW
TPERIOD
Figure 6. Output Enable and Disable Timing
OE
VIL
TOHZ
VIH
TOE
CLK
High Impedance
CLK#
Document Number: 001-42886 Rev. *D
Page 4 of 7
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CY2XL11
Figure 7. RMS Phase Jitter
Phase noise
Noise Power
Phase noise mark
Offset Frequency
f1
RMS Jitter =
f2
Area Under the Masked Phase Noise Plot
Termination Circuits
Figure 8. LVDS Termination
CLK
100Ω
CLK#
Document Number: 001-42886 Rev. *D
Page 5 of 7
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CY2XL11
Ordering Information
Part Number
Package Description
Product Flow
CY2XL11ZXC
8-pin TSSOP
Commercial, –5°C to 70°C
CY2XL11ZXCT
8-pin TSSOP - Tape and Reel
Commercial, –5°C to 70°C
Package Drawing and Dimensions
Figure 9. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
6.25[0.246]
6.50[0.256]
4.30[0.169]
4.50[0.177]
8
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
0.05[0.002]
0.15[0.006]
2.90[0.114]
3.10[0.122]
SEATING
PLANE
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85093-*A
Document Number: 001-42886 Rev. *D
Page 6 of 7
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CY2XL11
Document History Page
Document Title: CY2XL11 100 MHz LVDS Clock Generator
Document Number: 001- 42886
REV.
ECN NO.
Submission
Date
Orig. of
Change
**
2117527
See ECN
*A
2669117
03/05/2009
KVM/
AESA
Changed crystal and output frequency
Removed MSL spec
Changed IIL value from -20 uA to -50 uA
Changed IIH value from 20 uA to 115 uA
Changed phase jitter value from 1 to 0.53 ps
Changed junction temp from 125°C to 135°C
Changed IDD from 150 mA to 120 mA
Rise / fall time changed to 350 ps to 500ps
Changed Data Sheet Status to Final
*B
2700242
04/30/2009
KVM/
PYRS
Typo correction
Reformatted AC and DC tables
Added IDD spec for 2.5V
Added CINX and TLOCK specs
Changed CIN from 7pF to 15pF
*C
2718433
06/12/2009
*D
2764787
09/18/2009
Description of Change
WWZ/KVM New data sheet
/AESA
WWZ/HMT No change. Submit to ECN for product launch.
KVM
Add clause to IOZ Test Conditions
Change VOD limits from 250/450 mV to 247/454 mV
Add max limit for TR, TF: 1.0 ns
Change TOE max from 100 ns to 120 ns
Change TLOCK max from 10 ms to 5 ms
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Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-42886 Rev. *D
Revised September 18, 2009
Page 7 of 7
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