MOTOROLA MCM67Q909 512k x 9 bit separate i/o synchronous fast static ram Datasheet

MOTOROLA
Order this document
by MCM67Q909/D
SEMICONDUCTOR TECHNICAL DATA
MCM67Q909
Advance Information
512K x 9 Bit Separate I/O
Synchronous Fast Static RAM
The MCM67Q909 is a 4M–bit static random access memory, organized as
512K words of 9 bits. It features separate TTL input and output buffers, which
drive 3.3 V output levels, and incorporates input and output registers on–board
with high speed SRAM. It also features transparent–write and data pass–through
capabilities.
The synchronous design allows for precise cycle control with the use of an
external single clock (K). The addresses (A0 – A18), data input (D0 – D8), data
output (Q0 – Q8), write–enable (W), chip–enable (E), and output–enable (G), are
registered on the rising edge of clock (K).
The control pins (E, W, G) function differently in comparison to most synchronous SRAMs. This device will not deselect with E high. The RAM remains active
at all times. If E is registered high, the output pins (Q0 – Q8) will be driven if G
is registered low. The transparent write feature allows the output data to track the
input data. E, G, and W must be asserted to perform a transparent write (write
and pass–through). The input data is available at the ouputs on the next rising
edge of clock (K).
The pass–through function is always enabled. E high disables the write to the
array while allowing a pass–through cycle to occur on the next rising edge of
clock (K). Only a registered G high will three–state the outputs.
The MCM67Q909 is available in an 86–bump surface mount PBGA (Plastic
Ball Grid Array) package.
•
•
•
•
•
•
•
•
•
•
•
•
Single 5 V ± 5% Power Supply
Fast Cycle Time: 12 ns Max
Single Clock Operation
TTL Input and Output Levels (Outputs LVTTL Compatible)
Address, Data Input, E, W, and G Registers On–Chip
83 MHz Maximum Clock Cycle Time
Self–Timed Write
Separate Data Input and Output Pins
Transparent–Write and Pass–Through
High Output Drive Capability: 50 pF/Output at Rated Access Time
Boundary Scan Implementation
PBGA Package for High Speed Operation
86 BUMP PBGA
CASE 896A–02
PIN NAMES
A0 – A18 . . . . . . . . . . . . . . . . . Address Input
E . . . . . . . . . . . . . . . . . . . . . . . . . Chip Enable
W . . . . . . . . . . . . . . . . . . . . . . . . Write Enable
G . . . . . . . . . . . . . . . . . . . . . . Output Enable
D0 – D8 . . . . . . . . . . . . . . . . . . . . Data Inputs
Q0 – Q8 . . . . . . . . . . . . . . . . . . Data Outputs
K . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Input
SCK . . . . . . . . . . . . . . . . . . Scan Clock Input
SE . . . . . . . . . . . . . . . . . . . . . . . Scan Enable
SDI . . . . . . . . . . . . . . . . . . . . Scan Data Input
SDO . . . . . . . . . . . . . . . . . Scan Data Output
VCC . . . . . . . . . . . . . . . + 5 V Power Supply
VSS . . . . . . . . . . . . . . . . . . . . . . . . . . Ground
NC . . . . . . . . . . . . . . . . . . . . . No Connection
PIN ASSIGNMENT
1
A
B
2
3
4
E
W
VCC
G
K
A16
A14
C
D7
A15 A17
D
VSS
Q7
D5
VSS VSS
E
F
G
H
J
K
VSS
5
6
SDI SDO
VSS
A6
7
8
9
A4
A0
A2
VSS D8
VSS VSS VSS VSS
Q8
VSS
VSS VSS VSS
Q6
D6
VSS
VSS VSS VSS VSS VSS VCC
VCC
Q5
VSS VSS VSS VSS VSS
D4
Q4
D3
Q3
VSS VSS VSS VSS VSS
D2
Q2
VSS
D1
A18 VSS
D0
VSS
Q1
A12
A10 VSS
A9
A8
A5
A1
Q0
A13
A11 SCK VCC
SE
A7
A3
VSS VSS VSS
TOP VIEW
86–BUMP
Not to Scale
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 3
12/23/97
 Motorola, Inc. 1997
MOTOROLA
FAST SRAM
MCM67Q909
1
BLOCK DIAGRAM
REG
A0 – A18
DECODERS
MEMORY
ARRAY
512K x 9 ARRAY
SH
BSR
SH
BSR
D0 – D8
REG
SENSE AMPS
AND WRITE
DRIVERS
REG
WRITE PULSE
GENERATOR
MUX
2:1
OUTPUT
REGISTER
Q0 – Q8
SH
BSR
E
SH
BSR
REG
G
SH
BSR
REG
W
SH
BSR
K
SE
SH
BSR
1
∧L
*
*
I
I
SDI
LM
SE
I
BYPASS
O
*
0
SCK
SCK
*
LS
SDO
SCK
SCK
NOTES:
1. Bypass mode is entered with SE low and SCK cycled.
2. SH BSR = shadow bypass scan register.
3. 41 bumps used in boundary scan. VSS, VCC, NC, SDI, SDO, SE, and SCK not used in scan path.
4. SDO output sequence: A6, A4, A2, A0, D8, Q8, D6, Q6, D4, Q4, D2, Q2, D0, Q0, A18, A1, A3, A5, A7, A8, A9, A10, A11, A12,
A13, Q1, D1, Q3, D3, Q5, D5, Q7, D7, A15, A16, A14, A17, E, G, W, K.
* Four added test pins.
MCM67Q909
2
MOTOROLA FAST SRAM
TRUTH TABLE
E
(tn)
W
(tn)
L
L
H
X
G
(tn + 1)
Mode
D0 – D8
(tn)
Q0 – Q8
(tn + 1)
VCC
Current
L
Write and
Pass–Through
Valid
D0 – D8 (tn)
ICC
H
Write
Valid
High–Z
ICC
L
Pass–Through
Valid
D0 – D8 (tn)
ICC
H
Pass–Through
Don’t Care
High–Z
ICC
L
Read
Don’t Care
Qout (tn)
ICC
H
Read
Don’t Care
High–Z
ICC
L
H
ABSOLUTE MAXIMUM RATINGS (See Note)
Symbol
Value
Unit
VCC
– 0.5 to + 7.0
V
Vin, Vout
– 0.5 to VCC + 0.5
V
Output Current
Iout
± 30
mA
Power Dissipation
PD
1.7
W
Tbias
– 10 to + 85
°C
TA
0 to + 70
°C
Tstg
– 55 to + 125
°C
Rating
Power Supply Voltage
Voltage Relative to VSS for Any Pin
Except VCC
Temperature Under Bias
Operating Temperature
Storage Temperature — Plastic
This is a synchronous device. All synchronous inputs must meet specified setup and hold
times with stable logic levels for ALL rising
edges of clock (K) while the device is selected.
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to these high–impedance
circuits.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS
Parameter
Symbol
Min
Max
Unit
Supply Voltage (Operating Voltage Range)
VCC
4.75
5.25
V
Input High Voltage
VIH
2.2
VCC + 0.3**
V
Input Low Voltage
VIL
– 0.5*
0.8
V
Input Leakage Current (All Inputs, Vin = 0 to VCC)
Ilkg(I)
—
± 1.0
µA
Output Leakage Current (E = VIH, Vout = 0 to VCC)
Ilkg(O)
—
± 1.0
µA
ICCA
—
230
mA
Output Low Voltage (IOL = + 8.0 mA)
VOL
—
0.4
V
Output High Voltage (IOH = – 4.0 mA)
VOH
2.4
3.3
V
AC Supply Current (Iout = 0 mA) (VCC = max, f = fmax)
MCM67Q909–12 ns
* VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
** VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.
MOTOROLA FAST SRAM
MCM67Q909
3
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 25°C, Periodically Sampled Rather Than 100% Tested)
Symbol
Max
Unit
Address and Data Input Capacitance
Parameter
Cin
6
pF
Control Pin Input Capacitance
Cin
6
pF
Cout
8
pF
Output Capacitance
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, 3 and 4)
MCM67Q909–12
P
Parameter
S b l
Symbol
Min
Max
U i
Unit
N
Notes
Cycle Time
tKHKH
12
—
ns
1
Clock Access Time
tKHQV
—
5
ns
2
Clock Low Pulse Width
tKLKH
4
—
ns
Clock High Pulse Width
tKHKL
4
—
ns
Clock High to Data Output Invalid
tKHQX
2
—
ns
Clock High to Data Output High–Z
tKHQZ
—
5
ns
3
Setup Times:
A
W
E
G
D0 – D8
tAVKH
tWVKH
tEVKH
tGVKH
tDVKH
3
—
ns
4
Hold Times:
A
W
E
G
D0 – D8
tKHAX
tKHWX
tKHEX
tKHGX
tKHDX
2
—
ns
4
NOTES:
1. All read and write cycles are referenced from K.
2. Valid data from clock high will be the data stored at the address or the last valid read cycle.
3. Measured at ± 200 mV from steady state.
4. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL rising
edges of clock (K) while the device is selected.
RL = 50 Ω
OUTPUT
Z0 = 50 Ω
VL = 1.5 V
Figure 1. AC Test Load
MCM67Q909
4
MOTOROLA FAST SRAM
MOTOROLA FAST SRAM
MCM67Q909
5
Q
G
E
W
A
K
tEVKH
A (n)
Q (n – 2)
tKHQX
tKHEX
tAVKH
tKHAX
Q (n – 1)
A (n + 1)
tKHWX
tWVKH
tKHKH
tKHQV
tGVKH
Q (n)
tKHQZ
tKHGX
A (n + 2)
tKLKH
READ CYCLE TIMING
tKHQX
A (n + 3)
tKHKL
Q (n + 2)
tKHQZ
A (n + 4)
MCM67Q909
6
MOTOROLA FAST SRAM
D
Q
G
E
W
A
A (n)
tKHQX
t KHAX
t AVKH
K
INITIATE READ
A (n + 1)
D (n + 1)
tKHQV
tGVKH
t WVKH
t KHWX
t KHKH
WRITE D (n + 1)
tKHGX
Q (n)
tKHQZ
tKHQX
t EVKH
A (n + 2)
t KLKH
tKHEX
t DVKH
INITIATE READ
D (n + 3)
A (n + 3)
tKHKL
WRITE D (n + 3)
t KHDX
Q (n + 2)
A (n + 4)
INITIATE READ
COMBINATION READ/WRITE CYCLE TIMING
D (n + 5)
A (n + 5)
WRITE D (n + 5)
Q (n + 4)
A (n + 6)
INITIATE READ
MOTOROLA FAST SRAM
MCM67Q909
7
D
Q
G
E
W
A
K
tDVKH
A (n)
D (n)
Q (n – 2)
tKHQX
tKHDX
tEVKH
tKHEX
tAVKH
tKHAX
D (n + 1)
tKHQV
D (n + 2)
D (n)
tKHQZ
tKHGX
tGVKH
A (n + 2)
tKLKH
WRITE WITH PASS-THROUGH
Q (n – 1)
A (n + 1)
tKHWX
tWVKH
tKHKH
WRITE WITH PASS-THROUGH
A (n + 3)
D (n + 3)
tKHQX
NO WRITE
WRITE
(TRANSPARENT-WRITE
OUTPUTS HIGH-Z)
TRANSPARENT-WRITE AND PASS-THROUGH CYCLE TIMING
tKHKL
NO WRITE
A (n + 4)
D (n + 4)
D (n + 2)
tKHQZ
PASS-THROUGH
(NO WRITE)
BOUNDARY SCAN CYCLE TIMING
MCM67Q909–12
P
Parameter
S b l
Symbol
Min
Max
U i
Unit
N
Notes
Cycle Time
tCHCH2
100
—
ns
Clock High Pulse Width
tCHCL2
40
—
ns
Clock Low Pulse Width
tCLCH2
40
—
ns
Scan Mode Setup Time
tSS
10
—
ns
1
Bypass Mode Setup Time
tBS
10
—
ns
2
Scan Mode Recovery Time
tSR
100
—
ns
3
SCK Low to SE Hold High
tCLMH
10
—
ns
4
SE High to SCK High Setup
tMHCH
10
—
ns
5
SCK High to SE Low Hold Time
tCHML
10
—
ns
6
SDI Valid to SCK High Setup
tIVCH
10
—
ns
SCK High to SDI Don’t Care
tCHIX
10
—
ns
SCK Low to SDO Valid
tCLOV
—
20
ns
NOTES:
1. The minimum delay required between ending normal operation and beginning scan operations.
2. The minimum delay required between ending shift mode and beginning bypass mode.
3. The minimum delay required before restarting normal RAM operation.
4. The minimum delay required before executing a parallel load operation.
5. The minimum delay required between a parallel load operation and a shift.
6. Minimum shift command hold time.
BOUNDARY SCAN
OVERVIEW
Boundary scan is a simple, non–intrusive scheme that
allows verification of electrical continuity for each of a
clocked RAMs logically active inputs and I/Os without adversely affecting RAM performance. Boundary scan allows
the user to monitor the logic levels applied to each signal I/O
on the RAM, and to shift them out in a serial bit stream.
OPERATION
Boundary scan requires four signal pins for implementation: scan data in (SDI), scan data out (SDO), scan clock
(SCK, active high), and scan enable (SE, active high).
MCM67Q909
8
Boundary scan provides three modes of operation: (1) normal RAM operation, (2) scan, and (3) bypass. For normal
RAM operation, SCK and SE must be held low. The RAM will
always return to normal operation immediately after the RAM
receives a rising edge of the RAM input clock (K) with SCK
and SE held low. To enter scan mode, SCK is activated. The
first rising edge of SCK is used to latch in the data on the
scan registers. SE is then driven high to disable additional input data from entering the scan registers. Every falling edge
of SCK serially shifts data through the scan registers and
onto the SDO pin. To enter bypass mode, simply exercise
SCK with SE held low. In this mode, SDI is sampled on the
rising edge of SCK. The level found on SDI is then driven out
on SDO on the next falling edge of SCK.
MOTOROLA FAST SRAM
MOTOROLA FAST SRAM
MCM67Q909
9
t SS
B1
BYPASS
S1
t CHIX
t IVCH
t MHCH
B1
PARALLEL
LOAD
SHIFT
1
S2
t CLOV
A6
t CLMH
SHIFT
2
S3
A4
SHIFT
3
S38
A17
SHIFT
38
E
S39
t CHCL2
SHIFT
39
t CHCH2
G
S40
t CLCH2
SHIFT
40
W
S41
SHIFT
41
Sn
K
SHIFT
n
B2
t CHML
S1
t SR
t BS
B2
NORMAL
BYPASS OPERATION
B1 and B2 = bypass serial data from outside source.
S1 – Sn + 1 = serial scan data from outside source.
S1 – Sn = RAMs input register contents.
Scan order is: A6, A4, A2, A0, D8, Q8, D6, Q6, D4, Q4, D2, Q2, D0, Q0, A18, A1, A3, A5, A7, A8, A9, A10, A11, A12, A13, Q1, D1, Q3, D3, Q5, D5, Q7, D7, A15, A16, A14, A17, E, G, W, K.
NOTES:
SDO
SDI
SE
SCK
K
NORMAL
OPERATION
BOUNDARY SCAN TIMING DIAGRAM
ORDERING INFORMATION
(Order by Full Part Number)
MCM 67Q909 XX
XX
X
Motorola Memory Prefix
Shipping Method (R = Tape and Reel,
Blank = Trays)
Part Number
Speed (12 = 12 ns)
Package (ZP = PBGA)
Full Part Numbers — MCM67Q909ZP12
MCM67Q909ZP12R
PACKAGE DIMENSIONS
ZP PACKAGE
86 PBGA
CASE 896A–02
0.25 (0.010) T
0.15 (0.006) T
B
–W–
CL
A
B
C
D
E
F
G
H
J
K
A
R
–L–
P
N
E
G
C
0.35 (0.014) T
86X
–T–
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
9 8 7 6 5 4 3 2 1
G
DIM
A
B
C
D
E
G
N
P
R
CL
4X
MILLIMETERS
MIN
MAX
17.78 BSC
16.26 BSC
1.84
2.44
0.69
0.81
1.33
1.73
1.524 BSC
13.80
14.20
0.762 BSC
15.29
15.69
INCHES
MIN
MAX
0.700 BSC
0.640 BSC
0.073
0.096
0.028
0.031
0.053
0.068
0.060 BSC
0.544
0.559
0.030 BSC
0.602
0.617
0.20 (0.008)
D
0.30 (0.012)
S
0.10 (0.004)
S
T L
S
W
S
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
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MCM67Q909
10
◊
MCM67Q909/D
MOTOROLA FAST
SRAM
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