Intersil ISL8002B External soft-start programmable Datasheet

DATASHEET
Compact Synchronous Buck Regulator
ISL8002B
Features
The ISL8002B is a highly efficient, monolithic, synchronous
step-down DC/DC converter that can deliver up to 2A of
continuous output current from a 2.7V to 5.5V input supply. It
uses peak current mode control architecture to allow very low
duty cycle operation. ISL8002B operates at a 2MHz switching
frequency, thereby providing superior transient response and
allowing for the use of a small inductor. ISL8002B also has
excellent stability.
• VIN range 2.7V to 5.5V
• IOUT maximum is 2A
• External soft-start programmable
• Output tracking and sequencing
• Switching frequency is 2MHz
• Selectable PFM or PWM operation option
• Overcurrent and short-circuit protection
The ISL8002B integrates very low rDS(ON) MOSFETs in order to
maximize efficiency. In addition, since the high-side MOSFET is a
PMOS, the need for a boot capacitor is eliminated, thereby
reducing external component count.
• Over-temperature/thermal protection
• VIN undervoltage lockout and VOUT overvoltage protection
• Up to 95% peak efficiency
The device can be configured for either PFM (discontinuous
conduction) or PWM (continuous conduction) operation at light
load. PFM provides high efficiency by reducing switching
losses at light loads and PWM for fast transient response,
which helps reduce the output noise and RF interference.
Applications
• General purpose POL
• Industrial, instrumentation and medical equipment
• FPGAs
The device is offered in a space saving 8 Ld 2mmx2mm TDFN
Pb-free package with exposed pad for improved thermal
performance. The complete converter occupies less than
64mm2 area.
• Telecom and networking equipment
• Game console
Related Literature
• For a full list of related documents, visit our website
- ISL8002B product page
GND
+2.7 V … +5.5 V 1
VIN
C1
22µF
2
EN
EN
3
4
PG
FB 6
0.6V
PAD
9
SS/T R 5
+1.8V/2A
100
VOUT
C2
3x10µF
PG ND 7
M ODE
PG
L1
PHASE 8
C3
4.7pF
R1
200k 1%
R2
100k 1%
R3
200k 1%
2.5VOUT
GND
T RACK
R4
100k 1%
90
EFFICIENCY (%)
ISL8002B
VIN
80
1.8VOUT
1.5VOUT
70
1.2VOUT
0.9VOUT
60
0.8VOUT
50
VO
R 1 = R 2  ------------ – 1
 VFB

(EQ. 1)
FIGURE 1. TYPICAL APPLICATION CIRCUIT CONFIGURATION (INTERNAL
COMPENSATION OPTION)
October 28, 2016
FN8690.3
1
40
0.0
0.2
0.4
0.6
0.8 1.0 1.2 1.4
OUTPUT LOAD (A)
1.6
1.8
2.0
FIGURE 2. EFFICIENCY vs LOAD (fSW = 2MHz, VIN = 3.3V),
MODE = PFM, TA = +25°C
CAUTION: The device are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014-2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL8002B
Table of Contents
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Control Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PFM Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Short-Circuit Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Negative Current Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable, Disable and Soft Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
17
17
17
17
17
17
17
Output Tracking and Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Discharge Mode (Soft-Stop) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Derating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
19
19
19
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor and Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
19
19
19
20
20
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
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ISL8002B
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
INTERNAL/
EXTERNAL
COMP
TRACKING/EXTERNAL
SOFT- START
OUTPUT CURRENT
(A)
PG RISING/FALLING
DELAY TIME
NOMINAL SWITCHING
FREQUENCY
(MHz)
ISL8002/A
Yes
No
2
1ms/15µs
1/2
ISL80019/A
Yes
No
1.5
1ms/15µs
1/2
ISL8002B
No
Yes
2
0.1ms/15µs
2
PART NUMBER
TABLE 2. RECOMMENDED COMPONENT VALUE SELECTION TABLE
VOUT
(V)
C1
(µF)
C2 MINIMUM
(µF)
C3
(pF)
L1
(µH)
R1, R3 (Note 1)
(kΩ)
R2, R4 (Note 1)
(kΩ)
0.8
22
3 X10
4.7
0.82
33
100
1.2
22
3 X10
4.7
1.0
100
100
1.5
22
3 X10
4.7
1.0
150
100
1.8
22
3 X10
4.7
1.2
200
100
2.5
22
3 X10
4.7
1.8
316
100
3.3
22
3 X10
4.7
2.2
450
100
NOTE:
1. Populate R3 and R4 if Tracking feature is used. Ratio between R1/R2 should equal R3/R4. Otherwise connect SS/TR to VIN for internal soft-start.
Ordering Information
PART NUMBER
(Notes 2, 3, 4)
PART
MARKING
TAPE AND REEL
(UNITS)
TECHNICAL
SPECIFICATIONS
TEMPERATURE
RANGE
(°C)
PACKAGE
(RoHS COMPLIANT)
PKG.
DWG. #
ISL8002BIRZ-T
02B
1000
2A, 2MHz
-40 to +85
8 Ld TDFN
L8.2x2C
ISL8002BIRZ-T7A
02B
250
2A, 2MHz
-40 to +85
8 Ld TDFN
L8.2x2C
ISL8002BFRZ-T
2BF
1000
2A, 2MHz
-40 to +125
8 Ld TDFN
L8.2x2C
ISL8002BFRZ-T7A
2BF
250
2A, 2MHz
-40 to +125
8 Ld TDFN
L8.2x2C
ISL8002BDEMO1Z
Demonstration Board
NOTES:
2. Please refer to TB347 for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for ISL8002B. For more information on MSL please see techbrief TB363.
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ISL8002B
Pin Configuration
ISL8002B
(8 LD 2x2 TDFN)
TOP VIEW
VIN
1
EN
2
MODE
3
PG
4
EPAD
(GND)
PAD
8
PHASE
7
PGND
6
FB
5
SS/TR
Pin Descriptions
PIN NUMBER
SYMBOL
PIN DESCRIPTION
1
VIN
The input supply for the power stage of the PWM regulator and the source for the internal linear regulator that provides
bias for the IC. Place a minimum of 10µF ceramic capacitance from VIN to GND and as close as possible to the IC for
decoupling.
2
EN
Device enable input. When the voltage on this pin rises above 1.4V, the device is enabled. The device is disabled when
the pin is pulled to ground. When the device is disabled, a 100Ω resistor discharges the output through the PHASE pin.
See Figure 3, “FUNCTIONAL BLOCK DIAGRAM” on page 5 for details.
3
MODE
Mode selection pin. Connect to logic high or input voltage VIN for PWM mode. Connect to logic low or ground for PFM
mode. There is an internal 1MΩ pull-down resistor to prevent an undefined logic state in case the MODE pin is left
floating, however, it is not recommended to leave this pin floating.
4
PG
Power-good output is pulled to ground during the soft-start interval and also when the output voltage is below regulation
limits. There is an internal 5MΩ internal pull-up resistor on this pin.
5
SS/TR
Soft-start pins for regulator. If SS/TR pin is tied to VIN, an internal soft-start of 1ms will be used. A resistor divider from
VIN to SS/TR and a capacitor from the SS/TR pin to ground determines the output ramp rate. Adding a resistive divider
across SS/TR can be used for output tracking. See “Output Tracking and Sequencing” on page 18 for soft-start and
output tracking/sequencing details. Maximum CSS value is 1µF.
6
FB
Feedback pin for the regulator. FB is the negative input to the voltage loop error amplifier. The output voltage is set by
an external resistor divider connected to FB. In addition, the power-good PWM regulator’s power-good and undervoltage
protection circuits use FB to monitor the output voltage.
7
PGND
Power and analog ground connections. Connect directly to the board GND plane.
8
PHASE
Power stage switching node for output voltage regulation. Connect to the output inductor. This pin is discharged by a
100Ω resistor when the device is disabled. See Figure 3, “FUNCTIONAL BLOCK DIAGRAM” on page 5 for details.
-
EPAD
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The exposed pad must be connected to the PGND pin for proper electrical performance.
Place as many vias as possible under the pad connecting to the PGND plane for optimal thermal performance.
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ISL8002B
Functional Block Diagram
SS/TR
MODE
INTERNAL
SS
27pF
HIGH
DETECT
200kΩ
0.6V
CLAMP
BANDGAP
VREF
+
EN
SHUTDOWN
-
SHUTDOWN
VIN
OSCILLATOR
+
COMP
-
EAMP
P
PWM/PFM
LOGIC
CONTROLLER
PROTECTION
HS DRIVER
3pF
+
PHASE
N
PGND
FB
Slope
SLOPE
COMP
6kΩ
+
CSA
OCP
0.85*VREF
UV
VIN
SKIP
5MΩ
PG
0.1ms
DELAY
NEG CURRENT
SENSING
ZERO-CROSS
SENSING
0.3V
SCP
100Ω
SHUTDOWN
FIGURE 3. FUNCTIONAL BLOCK DIAGRAM
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Absolute Maximum Ratings
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V (DC) or 7V (20ms)
PHASE . . . . . . . . . . . . . . -1.5V (100ns)/-0.3V (DC) to 6V (DC) or 7V (20ms)
EN, COMP, PG, MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN + 0.3V
FB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V
ESD Rating
Human Body Model (Tested per JESD22-JS-001) . . . . . . . . . . . . . . . . 4kV
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . . 2kV
Latch-Up (Tested per JESD78D, Class 2, Level A) . . . . ±100mA at +125°C
Thermal Resistance (Typical, Notes 5, 6)
JA (°C/W) JC (°C/W)
2x2 TDFN Package . . . . . . . . . . . . . . . . . . .
71
7
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Junction Temperature Range at 0A . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Recommended Operating Conditions
VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 2A
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379 for details.
6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications TJ = -40°C to +125°C, VIN = 2.7V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply across the operating temperature range,-40°C to +85°C (IRZ) or -40°C to +125°C (FRZ).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
2.5
2.7
V
INPUT SUPPLY
VIN Undervoltage Lockout Threshold
VUVLO
Rising, no load
Falling, no load
Quiescent Supply Current
IVIN
2.2
2.4
V
MODE = PFM (GND), no load at the output
35
60
µA
MODE = PWM (VIN), no load at the output
8
15
mA
ISD
MODE = PFM (GND), VIN = 5.5V, EN = low
20
30
µA
VFB
TJ = -40°C to +85°C
0.595
0.600
0.605
V
TJ = -40°C to +125°C
0.589
0.6
0.605
V
SS/TR = 100mV
0.08
0.100
0.12
V
SS/TR = 500mV
0.490
0.500
0.510
V
VFB = 2.7V. TJ = -40°C to +125°C
-120
50
350
nA
Line Regulation
VIN = VO + 0.5V to 5.5V, nominal = 3.6V
TJ = -40°C to +125°C
-0.32
-0.05
0.28
%/V
Load Regulation
(Note 8)
Soft-Start Ramp Time Cycle
SS/TR = VIN
Shutdown Supply Current
OUTPUT REGULATION
Feedback Voltage
VFB Bias Current
IVFB
< -0.2
%/A
1
ms
PROTECTIONS
Positive Peak Current Limit
IPLIMIT
Peak Skip Limit
ISKIP
2.7
VIN = 3.6V, VOUT = 1.8V (see “Applications
Information” on page 19 for more detail)
Zero Cross Threshold
Negative Current Limit
INLIMIT
3.2
3.7
450
A
mA
-170
-70
30
mA
-2.37
-1.8
-1
A
Thermal Shutdown
Temperature rising
150
°C
Thermal Shutdown Hysteresis
Temperature falling
25
°C
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ISL8002B
Electrical Specifications TJ = -40°C to +125°C, VIN = 2.7V to 5.5V, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply across the operating temperature range,-40°C to +85°C (IRZ) or -40°C to +125°C (FRZ). (Continued)
PARAMETER
SYMBOL
MIN
(Note 7)
TEST CONDITIONS
MAX
(Note 7)
TYP
UNIT
COMPENSATION
Error Amplifier Transconductance
80
Transresistance
RT
0.24
µA/V
0.3
0.40
Ω
PHASE
P-Channel MOSFET ON-Resistance
VIN = 5V, IO = 200mA
117
mΩ
N-Channel MOSFET ON-Resistance
VIN = 5V, IO = 200mA
86
mΩ
OSCILLATOR
Nominal Switching Frequency
fSW
1700
2000
2300
kHz
0.3
V
0.2
ms
PG
Output Low Voltage
1mA sinking current
Delay Time (Rising Edge)
0.1
PGOOD Delay Time (Falling Edge)
5
PG Pin Leakage Current
PG = VIN
UVP PG Rising Threshold
80
µs
0.01
0.1
µA
85
90
%
UVP PG Hysteresis
5
%
EN AND MODE LOGIC
EN Logic Input Low
1
EN Logic Input High
V
1.4
V
MODE Logic Input Low
0.4
MODE Logic Input High
V
1.4
Logic Input Leakage Current
IMODE
Pulled up to 5.5V
V
5.5
8
µA
NOTES:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
8. Not tested in production. Characterized using evaluation board. Refer to Figures 10 through 12 load regulation diagrams. TA +105°C represents near
worst case operating point.
Typical Performance Curves
100
100
2.5VOUT
2.5VOUT
90
80
1.8VOUT
70
1.5VOUT
1.2VOUT
0.9VOUT
60
80
1.8VOUT
70
1.5VOUT
1.2VOUT
0.9VOUT
60
0.8VOUT
0.8VOUT
50
40
0.0
EFFICIENCY (%)
EFFICIENCY (%)
90
50
0.2
0.4
0.6
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
FIGURE 4. EFFICIENCY vs LOAD fSW = 2MHz, VIN = 3.3V,
MODE = PFM, TA = +25°C
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1.8
2.0
40
0.0
0.2
0.4
0.6
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
1.8
2.0
FIGURE 5. EFFICIENCY vs LOAD fSW = 2MHz, VIN = 3.3V,
MODE = PWM, TA = +25°C
FN8690.3
October 28, 2016
ISL8002B
Typical Performance Curves
(Continued)
100
100
3.3VOUT
90
90
80
80
1.8VOUT
2.5VOUT
70
1.5VOUT
EFFICIENCY (%)
EFFICIENCY (%)
3.3VOUT
1.2VOUT
60
0.9VOUT
50
0.2
0.4
0.6
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
1.8
1.5VOUT
1.2VOUT
0.9VOUT
0.2
0.4
0.6
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
1.8
2.0
FIGURE 7. EFFICIENCY vs LOAD fSW = 2MHz, VIN = 5V,
MODE = PWM, TA = +25°C
0.925
1.230
0.920
5VIN PFM
1.225
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.8VOUT
60
40
0.0
2.0
FIGURE 6. EFFICIENCY vs LOAD fSW = 2MHz, VIN = 5V,
MODE = PFM, TA = +25°C
0.915
0.910
0.905
0.2
0.4
5VIN PWM
3.3VIN PFM
0.6
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
1.8
2.0
1.215
1.210
1.200
0.0
FIGURE 8. VOUT REGULATION vs LOAD, fSW = 2MHz, VOUT = 0.9V,
TA = +25°C
1.520
0.2
0.4
0.6
3.3VIN PFM
0.8
1.0
1.2
OUTPUT LOAD (A)
5VIN PWM
1.4
1.6
1.8
2.0
1.810
5VIN PFM
1.805
OUTPUT VOLTAGE (V)
1.510
1.505
1.500
0.2
0.4
0.6
0.8
1.0
1.2
OUTPUT LOAD (A)
5VIN PWM
1.4
1.6
1.8
2.0
FIGURE 10. VOUT REGULATION vs LOAD, fSW = 2MHz, VOUT = 1.5V,
TA = +25°C
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5VIN PFM
1.800
1.795
1.790
1.785
3.3VIN PWM
3.3VIN PFM
1.490
0.0
3.3VIN PWM
FIGURE 9. VOUT REGULATION vs LOAD, fSW = 2MHz, VOUT = 1.2V,
TA = +25°C
1.515
1.495
5VIN PFM
1.220
1.205
3.3VIN PWM
0.895
0.0
OUTPUT VOLTAGE (V)
2.5VOUT
50
40
0.0
0.900
70
8
1.780
0.0
3.3VIN PWM
3.3VIN PFM
0.2
0.4
0.6
0.8
1.0
5VIN PWM
1.2
1.4
1.6
1.8
2.0
OUTPUT LOAD (A)
FIGURE 11. VOUT REGULATION vs LOAD, fSW = 2MHz, VOUT = 1.8V,
TA = +25°C
FN8690.3
October 28, 2016
ISL8002B
Typical Performance Curves
(Continued)
3.335
2.505
3.330
5VIN PFM
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.500
2.495
2.490
2.485
3.3VIN PWM
2.475
0.0
0.2
0.4
0.6
0.8
1.0
1.2
OUTPUT LOAD (A)
3.315
5VIN PFM
5VIN PWM
1.4
1.6
1.8
2.0
FIGURE 12. VOUT REGULATION vs LOAD, fSW = 2MHz, VOUT = 2.5V,
TA = +25°C
EXTERNAL SS PROGRAMMING CSS = 0.1µF
5VIN PWM
3.320
3.310
3.3VIN PFM
2.480
3.325
VEN 5V/DIV
3.305
0.0
0.2
0.4
0.6
0.8
1.0
1.2
OUTPUT LOAD (A)
1.4
1.6
1.8
2.0
FIGURE 13. VOUT REGULATION vs LOAD, fSW = 2MHz, VOUT = 3.3V,
TA = +25°C
EXTERNAL SS PROGRAMMING CSS = 0.1µF
VEN 5V/DIV
VOUT 1V/DIV
VSS 1V/DIV
VOUT 1V/DIV
VSS 1V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 14. START-UP AT NO LOAD fSW = 2MHz, VIN = 5V,
MODE = PWM, TA = +25°C
FIGURE 15. SHUTDOWN AT NO LOAD fSW = 2MHz, VIN = 5V,
MODE = PWM, TA = +25°C
EXTERNAL SS PROGRAMMING CSS = 0.1µF
EXTERNAL SS PROGRAMMING CSS = 0.1µF
VEN 5V/DIV
VEN 5V/DIV
VOUT 1V/DIV
VSS 1V/DIV
VOUT 1V/DIV
VSS 1V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
FIGURE 16. START-UP AT 2A LOAD fSW = 2MHz, VIN = 5V,
MODE = PWM, TA = +25°C
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100µs/DIV
FIGURE 17. SHUTDOWN AT 2A LOAD fSW = 2MHz, VIN = 5V,
MODE = PWM, TA = +25°C
FN8690.3
October 28, 2016
ISL8002B
Typical Performance Curves
(Continued)
VEN 5V/DIV
VEN 5V/DIV
VOUT 1V/DIV
VOUT2 1V/DIV
VOUT 1V/DIV
PG 2V/DIV
VOUT2 1V/DIV
PG 2V/DIV
500µs/DIV
2ms/DIV
FIGURE 18. COINCIDENTAL VOLTAGE TRACKING START-UP AT NO
LOAD, VIN = 5V, MODE = PWM, TA = +25°C
FIGURE 19. COINCIDENTAL VOLTAGE TRACKING SHUTDOWN AT NO
LOAD, VIN = 5V, MODE = PWM, TA = +25°C
VEN 5V/DIV
VEN 5V/DIV
VOUT 1V/DIV
VOUT2 1V/DIV
VOUT 1V/DIV
PG 2V/DIV
VOUT2 1V/DIV
PG 2V/DIV
500µs/DIV
100µs/DIV
FIGURE 20. COINCIDENTAL VOLTAGE TRACKING START-UP AT FULL
LOAD, VIN = 5V, MODE = PWM, TA = +25°C
FIGURE 21. COINCIDENTAL VOLTAGE TRACKING SHUTDOWN AT FULL
LOAD, VIN = 5V, MODE = PWM, TA = +25°C
VEN 5V/DIV
VEN 5V/DIV
PG1 EN2 5V/DIV
PG1 EN2 5V/DIV
VOUT 1V/DIV
VOUT2 1V/DIV
VOUT 1V/DIV
VOUT2 1V/DIV
500µs/DIV
FIGURE 22. SEQUENTIAL START-UP USING EN AND PG AT NO LOAD,
VIN = 5V, MODE = PWM, TA = +25°C
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500µs/DIV
FIGURE 23. SEQUENTIAL SHUTDOWN USING EN AND PG AT NO LOAD,
VIN = 5V, MODE = PWM, TA = +25°C
FN8690.3
October 28, 2016
ISL8002B
Typical Performance Curves
(Continued)
VEN 5V/DIV
VEN 5V/DIV
PG1 EN2 5V/DIV
PG1 EN2 5V/DIV
VOUT 1V/DIV
VOUT2 1V/DIV
VOUT 1V/DIV
VOUT2 1V/DIV
500µs/DIV
100µs/DIV
FIGURE 24. SEQUENTIAL START-UP USING EN AND PG AT FULL
LOAD, VIN = 5V, MODE = PWM, TA = +25°C
FIGURE 25. SEQUENTIAL SHUTDOWN USING EN AND PG AT FULL
LOAD, VIN = 5V, MODE = PWM, TA = +25°C
VEN1 5V/DIV
VEN1 5V/DIV
SS1 2V/DIV
SS1 2V/DIV
VOUT1 1V/DIV
VOUT2 1V/DIV
VOUT1 1V/DIV
VOUT2 1V/DIV
1ms/DIV
1ms/DIV
FIGURE 26. RATIOMETRIC START-UP WITH VOUT1 LEADING VOUT2 AT
NO LOAD, VIN = 5V, MODE = PWM, TA = +25°C
FIGURE 27. RATIOMETRIC SHUTDOWN WITH VOUT1 LEADING VOUT2
AT NO LOAD, VIN = 5V, MODE = PWM, TA = +25°C
VEN1 5V/DIV
VEN1 5V/DIV
SS1 2V/DIV
SS1 2V/DIV
VOUT1 1V/DIV
VOUT2 1V/DIV
VOUT1 1V/DIV
VOUT2 1V/DIV
1ms/DIV
FIGURE 28. RATIOMETRIC START-UP WITH VOUT1 LEADING VOUT2 AT
FULL LOAD, VIN = 5V, MODE = PWM, TA = +25°C
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11
1ms/DIV
FIGURE 29. RATIOMETRIC SHUTDOWN WITH VOUT1 LEADING VOUT2
AT FULL LOAD, VIN = 5V, MODE = PWM, TA = +25°C
FN8690.3
October 28, 2016
ISL8002B
Typical Performance Curves
(Continued)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 5V/DIV
VEN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 30. START-UP AT NO LOAD, VIN = 5V, MODE = PFM,
TA = +25°C
FIGURE 31. START-UP AT NO LOAD, VIN = 5V, MODE = PWM,
TA = +25°C
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 5V/DIV
VEN 5V/DIV
PG 5V/DIV
PG 5V/DIV
1ms/DIV
1ms/DIV
FIGURE 32. SHUTDOWN AT NO LOAD, VIN = 5V, MODE = PFM,
TA = +25°C
FIGURE 33. SHUTDOWN AT NO LOAD, VIN = 5V, MODE = PWM,
TA = +25°C
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 5V/DIV
VEN 5V/DIV
PG 5V/DIV
500µs/DIV
FIGURE 34. START-UP AT 2A LOAD, VIN = 5V, MODE = PWM,
TA = +25°C
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12
PG 5V/DIV
100µs/DIV
FIGURE 35. SHUTDOWN AT 2A LOAD, VIN = 5V, MODE = PWM,
TA = +25°C
FN8690.3
October 28, 2016
ISL8002B
Typical Performance Curves
(Continued)
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VEN 5V/DIV
VEN 5V/DIV
PG 5V/DIV
PG 5V/DIV
100µs/DIV
500µs/DIV
FIGURE 36. START-UP AT 2A LOAD, VIN = 5V, MODE = PFM,
TA = +25°C
FIGURE 37. SHUTDOWN AT 2A LOAD, VIN = 5V, MODE = PFM,
TA = +25°C
VIN 5V/DIV
VIN 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IOUT 1A/DIV
IOUT 1A/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
500µs/DIV
FIGURE 38. START-UP VIN AT 2A LOAD, VIN = 5V, MODE = PFM,
TA = +25°C
FIGURE 39. START-UP VIN AT 2A LOAD, VIN = 5V, MODE = PWM,
TA = +25°C
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
VIN 5V/DIV
VIN 5V/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
FIGURE 40. START-UP VIN AT NO LOAD, VIN = 5V, MODE = PFM,
TA = +25°C
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500µs/DIV
FIGURE 41. START-UP VIN AT NO LOAD, VIN = 5V, MODE = PWM,
TA = +25°C
FN8690.3
October 28, 2016
ISL8002B
Typical Performance Curves
(Continued)
PHASE 1V/DIV
PHASE 1V/DIV
10ns/DIV
20ns/DIV
FIGURE 42. JITTER AT NO LOAD PWM, VIN = 5V, MODE = PWM,
TA = +25°C
FIGURE 43. JITTER AT FULL LOAD PWM, VIN = 5V, MODE = PWM,
TA = +25°C
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 20mV/DIV
VOUT 10mV/DIV
IL 0.5A/DIV
IL 0.5A/DIV
500ns/DIV
50ms/DIV
FIGURE 44. STEADY STATE AT NO LOAD, VIN = 5V, MODE = PWM,
TA = +25°C
FIGURE 45. STEADY STATE AT NO LOAD, VIN = 5V, MODE = PFM,
TA = +25°C
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 10mV/DIV
VOUT 10mV/DIV
IL 1A/DIV
IL 1A/DIV
500ns/DIV
FIGURE 46. STEADY STATE AT 2A LOAD, VIN = 5V, MODE = PWM,
TA = +25°C
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500ns/DIV
FIGURE 47. STEADY STATE AT 2A LOAD, VIN = 5V, MODE = PFM,
TA = +25°C
FN8690.3
October 28, 2016
ISL8002B
Typical Performance Curves
(Continued)
VOUT RIPPLE 50mV/DIV
VOUT RIPPLE 50mV/DIV
IL 1A/DIV
IL 1A/DIV
200µs/DIV
200µs/DIV
FIGURE 48. LOAD TRANSIENT, VIN = 5V, MODE = PWM, TA = +25°C
FIGURE 49. LOAD TRANSIENT, VIN = 5V, MODE = PFM, TA = +25°C
PHASE 5V/DIV
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 2A/DIV
IL 2A/DIV
PG 5V/DIV
PG 5V/DIV
500µs/DIV
10µs/DIV
FIGURE 50. OUTPUT SHORT CIRCUIT, VIN = 5V, MODE = PWM,
TA = +25°C
375mA Mode Transition, completely
enter to PWM at 400mA.
PHASE 5V/DIV
PHASE 5V/DIV
VOUT1 RIPPLE 20mV/DIV
VOUT1 RIPPLE 20mV/DIV
Back to PFM at 15mA
FIGURE 52. PFM TO PWM TRANSITION, VIN = 5V, MODE = PFM,
TA = +25°C
15
IL 1A/DIV
IL 1A/DIV
5µs/DIV
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FIGURE 51. OVERCURRENT PROTECTION, VIN = 5V, MODE = PWM,
TA = +25°C
20µs/DIV
FIGURE 53. PWM TO PFM TRANSITION, VIN = 5V, MODE = PFM,
TA = +25°C
FN8690.3
October 28, 2016
ISL8002B
Typical Performance Curves
(Continued)
PHASE 5V/DIV
VOUT 1V/DIV
VOUT 1V/DIV
IL 2A/DIV
PG 2V/DIV
PG 5V/DIV
500µs/DIV
200µs/DIV
FIGURE 54. OVERVOLTAGE PROTECTION, VIN = 5V, MODE = PWM,
TA = +25°C
Theory of Operation
The device is a step-down switching regulator optimized for
battery powered applications. It operates at a high switching
frequency, which enables the use of smaller inductors resulting
in small form factor, while also providing excellent efficiency.
Further, at light loads while in PFM mode, the regulator reduces
the switching frequency, thereby minimizing the switching loss
and maximizing battery life. The quiescent current, when the
output is not loaded, is typically only 35µA. The supply current is
typically only 20µA when the regulator is shut down.
PWM Control Scheme
Pulling the MODE pin HI (>2.5V) forces the converter into PWM
mode, regardless of output current. The device employs the
current-mode Pulse-Width Modulation (PWM) control scheme for
fast transient response and pulse-by-pulse current limiting. Refer
to the “Functional Block Diagram” on page 5. The current loop
consists of the oscillator, the PWM comparator, current sensing
circuit and the slope compensation for the current loop stability.
The slope compensation is 900mV/Ts, which changes with
frequency. The gain for the current sensing circuit is typically
300mV/A. The control reference for the current loops comes
from the error amplifier's (EAMP) output.
FIGURE 55. OVER-TEMPERATURE PROTECTION, VIN = 5V,
MODE = PWM, TA = +159°C
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
FIGURE 56. PWM OPERATION WAVEFORMS
The reference voltage is 0.6V, which is used by feedback to
adjust the output of the error amplifier, VEAMP. The error
amplifier is a transconductance amplifier that converts the
voltage error signal to a current output. The voltage loop is
internally compensated with the 27pF and 200kΩ RC network.
The maximum EAMP voltage output is precisely clamped to 1.6V.
The PWM operation is initialized by the clock from the oscillator.
The P-channel MOSFET is turned on at the beginning of a PWM
cycle and the current in the MOSFET starts to ramp-up. When the
sum of the current amplifier, CSA, and the slope compensation
reaches the control reference of the current loop, the PWM
comparator COMP sends a signal to the PWM logic to turn off the
P-FET and turn on the N-channel MOSFET. The N-FET stays on
until the end of the PWM cycle. Figure 56 shows the typical
operating waveforms during the PWM operation. The dotted lines
illustrate the sum of the slope compensation ramp and the
current-sense amplifier’s CSA output. To ensure proper PWM
control, minimum on time need to be greater than 90ns.
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FN8690.3
October 28, 2016
ISL8002B
PFM Mode
Short-Circuit Protection
Pulling the MODE pin LO (<0.4V) forces the converter into PFM
mode. The device enters a Pulse-skipping mode at light load to
minimize the switching loss by reducing the switching frequency.
Figure 57 illustrates the Skip mode operation. A zero-cross
sensing circuit shown in Figure 57 monitors the N-FET current for
zero crossing. When 16 consecutive cycles of the inductor current
crossing zero are detected, the regulator enters the Skip mode.
During the sixteen detecting cycles, the current in the inductor is
allowed to become negative. The counter is reset to zero when
the current in any cycle does not cross zero.
The Short-Circuit Protection (SCP) comparator monitors the VFB
pin voltage for output short-circuit protection. When the VFB is
lower than 0.3V, the SCP comparator forces the PWM oscillator
frequency to drop to 1/3 of the normal operation value. This
comparator is effective during start-up or an output short-circuit
event.
Once the Skip mode is entered, the pulse modulation starts
being controlled by the SKIP comparator shown in the
“Functional Block Diagram” on page 5. Each pulse cycle is still
synchronized by the PWM clock. The P-FET is turned on at the
clock's rising edge and turned off when the output is higher than
1.5% of the nominal regulation or when its current reaches the
peak skip current limit value. Then the inductor current is
discharging to 0A and stays at zero. The internal clock is
disabled. The output voltage reduces gradually due to the load
current discharging the output capacitor. When the output
voltage drops to the nominal voltage, the P-FET will be turned on
again at the rising edge of the internal clock as it repeats the
previous operations.
The regulator resumes normal PWM mode operation when the
output voltage drops 1.5% below the nominal voltage.
Overcurrent Protection
The overcurrent protection is realized by monitoring the CSA
output with the OCP comparator, as shown in the “Functional
Block Diagram” on page 5. The current sensing circuit has a gain
of 300mV/A, from the P-FET current to the CSA output. When the
CSA output reaches a threshold, the OCP comparator is tripped to
turn off the P-FET immediately. The overcurrent function protects
the switching converter from a shorted output by monitoring the
current flowing through the upper MOSFET.
Upon detection of an overcurrent condition, the upper MOSFET
will be immediately turned off and will not be turned on again
until the next switching cycle. If the overcurrent condition goes
away, the output will resume back into regulation point.
PWM
Negative Current Protection
Similar to the overcurrent, the negative current protection is
realized by monitoring the current across the low-side N-FET, as
shown in the “Functional Block Diagram” on page 5. When the
valley point of the inductor current reaches -1.8A for 2 consecutive
cycles, both P-FET and N-FET shut off. The 100Ω in parallel to the
N-FET will activate discharging the output into regulation. The
control will begin to switch when output is within regulation. The
regulator will be in PFM for 20µs before switching to PWM if
necessary.
PG
PG is an output of a comparator that continuously monitors the
buck regulator output voltage. PG is actively held low when EN is low
and during the buck regulator soft-start period. After 0.1ms delay of
the soft-start period, PG becomes high impedance as long as the
output voltage is within nominal regulation voltage set by VFB.
When VFB drops 15% below the nominal regulation voltage, the
device pulls PG low. Any fault condition forces PG low until the fault
condition is cleared by attempts to soft-start. There is an internal
5MΩ pull-up resistor to fit most applications. An external resistor can
be added from PG to VIN for more pull-up strength.
UVLO
When the input voltage is below the Undervoltage Lockout
(UVLO) threshold, the regulator is disabled.
Enable, Disable and Soft Start-Up
After the VIN pin exceeds its rising POR trip point (nominal 2.7V),
the device begins operation. If the EN pin is held low externally,
nothing happens until this pin is released. Once the EN is
released and above the logic threshold, the internal default
soft-start time is 1ms if SS/TR is tied high above 0.6V.
PFM
PWM
CLOCK
16 CYCLES
PFM CURRENT LIMIT
IL
LOAD CURRENT
0
NOMINAL +1.5%
VOUT
NOMINAL
NOMINAL -1.5%
FIGURE 57. SKIP MODE OPERATION WAVEFORMS
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FN8690.3
October 28, 2016
ISL8002B
Output Tracking and Sequencing
Output soft-start programming, tracking and sequencing
between multiple regulators can be implemented by using the
SS/TR pin. Independent programming soft-start for each channel
is shown in Figure 58. The output ramp time for each channel
(tSS) is set by the soft-start capacitor (CSS). Maximum CSS value
is 1µF and the SS time should be greater than 1ms.
Figures 59, 60, and 61 show several configurations for output
tracking/sequencing for a 3.3V and 1.8V application.
Ratiometric tracking is achieved in Figure 59 by connecting
SS/TR on each channel. The measurement is shown in
Figures 26 through 29.
By connecting a feedback network from VOUT1 to the SS/TR2 pin
with the same ratio that sets VOUT2 voltage, absolute tracking
shown in Figure 60 is implemented. The measurement is shown
in Figures 18 through 21. If the output of Channel 1 is shorted to
GND, it will enter overcurrent mode, SS/TR2 will be pulled low
through the added resistor between VOUT1 and SS2 and this will
force Channel 2 into being low as well.
Figure 61 illustrates output sequencing. When EN1 is
transitioned high, VOUT1 comes up first and VOUT2 won't start
until OUT1 > 85% of its regulation point. The measurement is
shown in Figures 22 through 25.
VIN
VOUT1
SS/TR1
VIN
Rss
Css
ISL8002B
Rss
ISL8002B
VOUT
SS/TR
C3
3.3V
C2
Rss
VOUT2
SS/TR2
Css
1.7  V IN  T SS
C SS = -------------------------------------R SS
Rss
1.8V
C3
ISL8002B
VOUT
VOUT1
VOUT2
TSS
FIGURE 58. PROGRAMMING SOFT-START
VOUT1
FIGURE 59. RATIOMETRIC START-UP
3.3V
C2
ISL8002B
VOUT2
SS/TR2
VOUT1
EN1
1.8V
PG
ISL8002B
C3
ISL8002B
VOUT2
EN2
R4
100k
R3
200k
1.8V
C3
ISL8002B
VOUT1
VOUT2
FIGURE 60. COINCIDENTAL VOLTAGE TRACKING
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3.3V
C2
18
VOUT1
VOUT2
FIGURE 61. OUTPUT SEQUENCING
FN8690.3
October 28, 2016
ISL8002B
Discharge Mode (Soft-Stop)
Applications Information
When a transition to shutdown mode occurs or the VIN UVLO is set,
the outputs discharge to GND through an internal 100Ω switch.
Output Inductor and Capacitor Selection
Thermal Shutdown
The device has built-in thermal protection. When the internal
temperature reaches +150°C, the regulator is completely shut
down. As the temperature drops to +125°C, the device resumes
operation by stepping through the soft-start.
Power Derating Characteristics
To prevent the ISL8002B from exceeding the maximum junction
temperature, some thermal analysis is required. The
temperature rise is given by Equation 2:
(EQ. 2)
T RISE =  PD    JA 
where PD is the power dissipated by the regulator and θJA is the
thermal resistance from the junction of the die to the ambient
temperature. The junction temperature, TJ, is given by
Equation 3:
(EQ. 3)
T J =  T A + T RISE 
where TA is the ambient temperature. For the DFN package, the
θJA is +71°C/W.
The actual junction temperature should not exceed the absolute
maximum junction temperature of +125°C when considering
the thermal design.
The ISL8002B delivers full current at ambient temperatures up
to +85°C. If the thermal impedance from the thermal pad
maintains the junction temperature below the thermal shutdown
level, (depending on the input voltage/output voltage
combination and the switching frequency) the device power
dissipation must be reduced to maintain the junction
temperature at or below the thermal shutdown level. Figure 62
illustrates the approximate output current derating versus
ambient temperature for the ISL8002DEMO1Z kit.
OUTPUT CURRENT (V)
2.5
2.0
1V
1.5
(EQ. 4)
The inductor’s saturation current rating needs to be at least
larger than the peak current.
The device uses an internal compensation network and the
output capacitor value is dependent on the output voltage. The
ceramic capacitor is recommended to be X5R or X7R.
Output Voltage Selection
The output voltage of the regulator can be programmed (from
0.6V up to 80% of VIN) via an external resistor divider that is used
to scale the output voltage relative to the internal reference
voltage and feed it back to the inverting input of the error
amplifier.
The output voltage programming resistor, R2, will depend on the
value chosen for the feedback resistor and the desired output
voltage of the regulator. The value for the feedback resistor is
typically between 10kΩ and 100kΩ, as shown in Equation 5.
VO
R 1 = R 2  ------------ – 1
 VFB

(EQ. 5)
If the output voltage desired is 0.6V, then R2 is left unpopulated
and R1 is shorted. There is a leakage current from VIN to PHASE.
It is recommended to preload the output with 10µA minimum.
For better performance, add 4.7pF in parallel with R1. Check
loop analysis before use in application.
The main functions for the input capacitor are to provide
decoupling of the parasitic inductance and to provide filtering
function to prevent the switching current flowing back to the
battery rail. At least two 22µF X5R or X7R ceramic capacitors are
a good starting point for the input capacitor selection.
2.5V
3.3V
0.5
VIN = 5V, OLFM
0
50
60
70
VO 

V O   1 – ---------
V IN

I = --------------------------------------L  f SW
Input Capacitor Selection
1.5V
1.0
To consider steady state and transient operations, the ISL8002B
typically requires a 1.2µH inductor. Higher or lower inductor value
can be used to optimize the total converter system performance.
For example, for higher output voltage 3.3V application, in order
to decrease the inductor ripple current and output voltage ripple,
the output inductor value can be increased. It is recommended to
set the inductor ripple current to be approximately 30% of the
maximum output current for optimized performance. The
inductor ripple current can be expressed as shown in Equation 4:
80
90
100
TEMPERATURE (°C)
110
120
130
FIGURE 62. DERATING CURVE vs TEMPERATURE
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ISL8002B
Output Capacitor Selection
Layout Considerations
An output capacitor is required to filter the inductor current.
Output ripple voltage and transient response are two critical
factors when considering output capacitance choice. The current
mode control loop allows for the use of low ESR ceramic
capacitors and thus smaller board layout. Electrolytic and
polymer capacitors may also be used.
The PCB layout is a very important converter design step to make
sure the designed converter works well. The power loop is
composed of the output inductor L’s, the output capacitor COUT,
the PHASE’s pins and the PGND pin. It is necessary to make the
power loop as small as possible and the connecting traces
among them should be direct, short, and wide. The switching
node of the converter, the PHASE pins, and the traces connected
to the node are very noisy, so keep the voltage feedback trace
away from these noisy traces. The input capacitor should be
placed as close as possible to the VIN pin and the ground of the
input and output capacitors should be connected as close as
possible. The heat of the IC is mainly dissipated through the
thermal pad. Maximizing the copper area connected to the
thermal pad is preferable. In addition, a solid ground plane is
helpful for better EMI performance. It is recommended to add at
least four vias ground connection within the pad for the best
thermal relief.
Additional consideration applies to ceramic capacitors. While
they offer excellent overall performance and reliability, the actual
in-circuit capacitance must be considered. Ceramic capacitors
are rated using large peak-to-peak voltage swings and with no DC
bias. In the DC/DC converter application, these conditions do not
reflect reality. As a result, the actual capacitance may be
considerably lower than the advertised value. Consult the
manufacturers datasheet to determine the actual in-application
capacitance. Most manufacturers publish capacitance vs DC bias
so that this effect can be easily accommodated. The effects of
AC voltage are not frequently published, but an assumption of
~20% further reduction will generally suffice. The result of these
considerations can easily result in an effective capacitance 50%
lower than the rated value. Nonetheless, they are a very good
choice in many applications due to their reliability and extremely
low ESR.
Equations 6 and 7 allow calculation of the required capacitance
to meet a desired ripple voltage level. Additional capacitance
may be used.
For the ceramic capacitors (low ESR) =
I
V OUTripple = ------------------------------------8 f SW C OUT
(EQ. 6)
where I is the inductor’s peak-to-peak ripple current, fSW is the
switching frequency and COUT is the output capacitor.
If using electrolytic capacitors then:
V OUTripple = I*ESR
(EQ. 7)
Regarding transient response needs, a good starting point is to
determine the allowable overshoot in VOUT if the load is suddenly
removed. In this case, energy stored in the inductor will be
transferred to COUT causing its voltage to rise. After calculating
capacitance required for both ripple and transient needs, choose
the larger of the calculated values. Equation 8 determines the
required output capacitor value in order to achieve a desired
overshoot relative to the regulated voltage.
I OUT 2 * L
C OUT = -------------------------------------------------------------------------------------------V OUT 2 *  V OUTMAX  V OUT  2 – 1 
(EQ. 8)
where VOUTMAX/VOUT is the relative maximum overshoot
allowed during the removal of the load. For an overshoot of 5%,
Equation 8 becomes Equation 9
I OUT 2 * L
C OUT = ----------------------------------------------------V OUT 2 *  1.05 2 – 1 
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(EQ. 9)
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ISL8002B
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
October 28, 2016
June 5, 2015
February 20, 2015
November 10, 2014
REVISION
CHANGE
FN8690.3 Updated Related Literature section on page 1.
Added ISL8002BFRZ-T and ISL8002BFRZ-T7A information to ordering information table on page 3.
Updated EC table boldface statement.
Added Test condition for 1st line of Feedback Voltage specification.
Bolded the -40°C to +125°C min/max values.
FN8690.2 Figure 13 on page 9 changed the color of the curve: blue changed to pink and pink one changed to blue.
POD on page 22 updated, changes since rev0:
Tiebar Note updated
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
FN8690.1 Added ISL8002BIRZ-T7A to Ordering Information table on page 3.
Added ESD Ratings and Latch-up on page 6.
Clarified Application section on page 19.
FN8690.0 Initial Release.
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ISL8002B
Package Outline Drawing
For the most recent package outline drawing, see L8.2x2C.
L8.2x2C
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE (TDFN) WITH E-PAD
Rev 1, 5/15
2.00
6
PIN #1 INDEX AREA
A
B
6
PIN 1
INDEX AREA
8
1
0.50
2.00
1.45±0.050
Exp.DAP
(4X)
0.15
0.25
0.10 M C A B
( 8x0.30 )
TOP VIEW
0.80±0.050
Exp.DAP
BOTTOM VIEW
( 8x0.20 )
Package Outline
( 8x0.30 )
SEE DETAIL "X"
( 6x0.50 )
1.45
2.00
0.10 C
0 . 75 ( 0 . 80 max)
C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
( 8x0.25 )
0.80
2.00
TYPICAL RECOMMENDED LAND PATTERN
C
0 . 2 REF
0 . 00 MIN.
0 . 05 MAX.
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature and may
be located on any of the 4 sides (or ends).
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
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22
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October 28, 2016