® LY611024 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.6 REVISION HISTORY Revision Rev. 1.0 Rev. 1.1 Rev. 1.2 Rev. 1.3 Rev. 1.5 Description Initial Issue Delete Icc1 Spec. Add E/I grade Revised VTERM to VT1 and VT2 Revised Test Condition of ISB1/IDR Added LL Spec. Revised Test Condition of ICC/ISB Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Added packing type in ORDERING INFORMATION Revised PACKAGE OUTLINE DIMENSION in page 9/10 Rev. 1.6 Revised ORDERING INFORMATION in page 11 Rev. 1.4 Revised PACKAGE OUTLINE DIMENSION in page 8 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0 Issue Date Jul.25.2004 Sep.21.2004 Apr.7.2005 Feb.2.2009 Apr.17.2009 May.7.2010 Aug.25.2010 ® LY611024 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.6 FEATURES GENERAL DESCRIPTION Fast access time : 12/15ns Low power consumption: Operating current : 50/40mA (TYP.) Standby current : 1mA (TYP.) 2μA (TYP.) LL -version Single 4.5V ~ 5.5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 2.0V (MIN.) Green package available Package : 32-pin 300 mil SOJ 32-pin 8mm x 20mm TSOP-I 32-pin 8mm x 13.4mm STSOP The LY611024 is a 1,048,576-bit low power CMOS static random access memory organized as 131,072 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY611024 is well designed for very high speed system applications, and particularly well suited for battery back-up nonvolatile memory application. The LY611024 operates from a single power supply of 4.5V ~ 5.5V and all inputs and outputs are fully TTL compatible PRODUCT FAMILY Product Family LY611024 LY611024(E) LY611024(I) LY611024(LL) LY611024(LLE) LY611024(LLI) Operating Temperature 0 ~ 70℃ -20 ~ 80℃ -40 ~ 85℃ 0 ~ 70℃ -20 ~ 80℃ -40 ~ 85℃ Vcc Range Speed 4.5 ~ 5.5V 4.5 ~ 5.5V 4.5 ~ 5.5V 4.5 ~ 5.5V 4.5 ~ 5.5V 4.5 ~ 5.5V 12/15ns 12/15ns 12/15ns 12/15ns 12/15ns 12/15ns FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION Vcc Vss A0-A16 DECODER DQ0-DQ7 I/O DATA CIRCUIT CE# CE2 WE# OE# CONTROL CIRCUIT Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 1mA 50/40mA 1mA 50/40mA 1mA 50/40mA 2µA 50/40mA 2µA 50/40mA 2µA 50/40mA 128Kx8 MEMORY ARRAY SYMBOL DESCRIPTION A0 - A16 Address Inputs DQ0 – DQ7 Data Inputs/Outputs CE#, CE2 Chip Enable Inputs WE# Write Enable Input OE# Output Enable Input VCC Power Supply VSS Ground NC No Connection COLUMN I/O Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1 ® LY611024 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.6 PIN CONFIGURATION 1 32 Vcc 2 31 A15 A14 3 30 CE2 A12 4 29 WE# A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 A3 9 A2 10 A1 11 22 CE# A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 Vss 16 17 DQ3 LY611024 NC A16 25 A11 24 OE# 23 A10 A11 A9 A8 A13 WE# CE2 A15 Vcc NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 LY611024 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3 TSOP-I/STSOP SOJ ABSOLUTE MAXIMUN RATINGS* PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS SYMBOL VT1 VT2 Operating Temperature TA Storage Temperature Power Dissipation DC Output Current TSTG PD IOUT RATING -0.5 to 6.5 -0.5 to VCC+0.5 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V ℃ ℃ ℃ ℃ W mA *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability. TRUTH TABLE MODE Standby Output Disable Read Write Note: CE# CE2 OE# WE# H X L L L X L H H H X X H L X X X H H L I/O OPERATION High-Z High-Z High-Z DOUT DIN H = VIH, L = VIL, X = Don't care. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2 SUPPLY CURRENT ISB,ISB1 ISB,ISB1 ICC ICC ICC ® LY611024 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.6 DC ELECTRICAL CHARACTERISTICS SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current VCC ≧ VIN ≧ VSS ILI Output Leakage VCC ≧ VOUT ≧ VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -4mA Output Low Voltage VOL IOL = 8mA Cycle time = Min. Average Operating CE# = VIL and CE2 = VIH, ICC Power supply Current II/O = 0mA Others at VIL or VIH CE# = VIH or CE2 = VIL ISB Others at VIL or VIH CE# ≧VCC-0.2V Standby Power or CE2≦0.2V Supply Current ISB1 CE# ≧VCC-0.2V or CE2≦0.2V Others at 0.2V or VCC-0.2V MIN. 4.5 2.4 - 0.5 -1 TYP. 5.0 - *4 MAX. 5.5 VCC+0.5 0.8 1 UNIT V V V µA -1 - 1 µA 2.4 - - 0.4 V V - 12 - 50 80 mA - 15 - 40 65 mA - 3 20 mA Normal - 1 5 mA LL - 2 50 µA Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25℃ CAPACITANCE (TA = 25℃, f = 1.0MHz) PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN. - MAX 6 8 Note : These parameters are guaranteed by device characterization, but not production tested. AC TEST CONDITIONS Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -4mA/8mA Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3 UNIT pF pF ® LY611024 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.6 AC ELECTRICAL CHARACTERISTICS (1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ* LY611024-12 MIN. MAX. 12 12 12 6 3 0 6 6 3 - LY611024-15 MIN. MAX. 15 15 15 7 4 0 7 7 3 - UNIT LY611024-12 MIN. MAX. 12 10 10 0 9 0 7 0 3 7 LY611024-15 MIN. MAX. 15 12 12 0 10 0 8 0 4 8 UNIT *These parameters are guaranteed by device characterization, but not production tested. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ® LY611024 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.6 TIMING WAVEFORMS READ CYCLE 1 (Address Controlled) (1,2) tRC Address tAA Dout tOH Previous Data Valid Data Valid READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5) tRC Address tAA CE# tACE CE2 OE# tOE tOH tOHZ tCHZ tOLZ tCLZ Dout High-Z Data Valid High-Z Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low., CE2 = high. 3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5 ® LY611024 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.6 WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6) tWC Address tAW CE# tCW CE2 tAS tWP tWR WE# tWHZ Dout TOW High-Z (4) tDW Din (4) tDH Data Valid WRITE CYCLE 2 (CE# and CE2 Controlled) (1,2,5,6) tWC Address tAW CE# tAS tWR tCW CE2 tWP WE# tWHZ Dout High-Z (4) tDW Din tDH Data Valid Notes : 1.WE#, CE# must be high or CE2 must be low during all address transitions. 2.A write occurs during the overlap of a low CE#, high CE2, low WE#. 3.During a WE#controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE#low transition and CE2 high transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6 ® LY611024 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.6 DATA RETENTION CHARACTERISTICS PARAMETER SYMBOL VCC for Data Retention VDR Data Retention Current IDR Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time tCDR TEST CONDITION CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V VCC = 2.0V CE# ≧ VCC - 0.2V Normal or CE2 ≦ 0.2V VCC = 2.0V CE# ≧ VCC - 0.2V LL or CE2 ≦ 0.2V others at 0.2V or VCC-0.2V See Data Retention Waveforms (below) tR MIN. TYP. MAX. UNIT 2.0 - 5.5 V - 0.01 3 mA - 0.5 30 µA 0 - - ns tRC* - - ns DATA RETENTION WAVEFORM Low Vcc Data Retention Waveform (1) (CE# controlled) VDR ≧ 2.0V Vcc Vcc(min.) Vcc(min.) tCDR CE# VIH tR CE# ≧ Vcc-0.2V VIH Low Vcc Data Retention Waveform (2) (CE2 controlled) VDR ≧ 2.0V Vcc Vcc(min.) Vcc(min.) tCDR CE2 tR CE2 ≦ 0.2V VIL VIL Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7 ® LY611024 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.6 PACKAGE OUTLINE DIMENSION 32 pin 300mil SOJ Package Outline Dimension UNIT SYMBOL A A1 A2 B D E E1 e L y INCH(BASE) MM(REF) 0.148(MAX) 0.025(MIN) 0.123(MAX) 0.018(TYP) 0.825±0.005 0.335(TYP) 0.300±0.005 0.050(TYP) 0.086±0.010 0.003(MAX) 3.759(MAX) 0.635(MIN) 3.124(MAX) 0.457(TYP) 20.955±0.127 8.509(TYP) 7.620±0.127 1.270(TYP) 2.184±0.254 0.076(MAX) Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8 ® LY611024 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.6 32 pin 8mm x 20mm TSOP-I Package Outline Dimension UNIT SYM. A A1 A2 b c D E e HD L L1 y Θ INCH(BASE) 0.047 (MAX) 0.004 ±0.002 0.039 ±0.002 0.009 ±0.002 0.006 ±0.002 0.724 ±0.008 0.315 ±0.008 0.020 (TYP) 0.787 ±0.008 0.024 ±0.004 0.0315 ±0.004 0.003 (MAX) o o 0 ～5 MM(REF) 1.20 (MAX) 0.10 ±0.05 1.00 ±0.05 0.22 ±0.05 0.155 ±0.055 18.40 ±0.20 8.00 ±0.20 0.50 (TYP) 20.00 ±0.20 0.60 ±0.10 0.08 ±0.10 0.08 (MAX) o o 0 ～5 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9 ® LY611024 128K X 8 BIT HIGH SPEED CMOS SRAM Rev. 1.6 32 pin 8mm x 13.4mm STSOP Package Outline Dimension HD cL 12° (2x) 32 16 17 12° (2x) b E e 1 "A" Seating Plane D y 12° (2X) 16 17 0.254 A2 c A GAUGE PLANE A1 0 SEATING PLANE "A" DATAIL VIEW 32 1 UNIT SYM. A A1 A2 b c D E e HD L L1 y Θ INCH(BASE) 0.049 (MAX) 0.004 ±0.002 0.039 ±0.002 0.009 ±0.002 0.006 ±0.002 0.465 ±0.008 0.315 ±0.008 0.020 (TYP) 0.528±0.008 0.02 ±0.008 0.031 ±0.005 0.003 (MAX) o o 0 ～5 MM(REF) 1.25 (MAX) 0.10 ±0.05 1.00 ±0.05 0.22 ±0.05 0.155 ±0.055 11.80 ±0.20 8.00 ±0.20 0.50 (TYP) 13.40 ±0.20. 0.50 ±0.20 0.8 ±0.125 0.076 (MAX) o o 0 ～5 Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10 L 12° (2X) L1 ® LY611024 Rev. 1.6 128K X 8 BIT HIGH SPEED CMOS SRAM ORDERING INFORMATION Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 11 ® LY611024 Rev. 1.6 128K X 8 BIT HIGH SPEED CMOS SRAM THIS PAGE IS LEFT BLANK INTENTIONALLY. Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 12