ESD7481MUT5G Transient Voltage Suppressors Micro−Packaged Diodes for ESD Protection The ESD7481 is designed to protect voltage sensitive components that require ultra−low capacitance from ESD and transient voltage events. Excellent clamping capability, low capacitance, low leakage, and fast response time, make these parts ideal for ESD protection on designs where board space is at a premium. Because of its low capacitance, the part is well suited for use in high frequency designs such as USB 2.0 high speed and antenna line applications. http://onsemi.com 1 Cathode 2 Anode Features Ultra−Low Capacitance 0.25 pF Low Clamping Voltage Small Body Outline Dimensions: 0.60 mm x 0.30 mm Low Body Height: 0.3 mm Stand−off Voltage: 5.0 V Low Leakage Insertion Loss: 0.030 dBm Response Time is < 1 ns Low Dynamic Resistance < 1 W IEC61000−4−2 Level 4 ESD Protection These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant MARKING DIAGRAM PIN 1 X3DFN2 CASE 152AF F M M = Specific Device Code (Rotated 90° clockwise) = Date Code ORDERING INFORMATION Device Package Shipping† ESD7481MUT5G X3DFN2 (Pb−Free) 5000/Tape & Reel Typical Applications • RF Signal ESD Protection • RF Switching, PA, and Antenna ESD Protection • Near Field Communications F • • • • • • • • • • • †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. MAXIMUM RATINGS Rating IEC 61000−4−2 (ESD) Symbol Contact Air Value Unit ±20 ±20 kV Total Power Dissipation on FR−5 Board (Note 1) @ TA = 25°C Thermal Resistance, Junction−to−Ambient °PD° 250 mW RqJA 400 °C/W Junction and Storage Temperature Range TJ, Tstg −40 to +125 °C TL 260 °C Lead Solder Temperature − Maximum (10 Second Duration) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. FR−5 = 1.0 x 0.75 x 0.62 in. See Application Note AND8308/D for further description of survivability specs. © Semiconductor Components Industries, LLC, 2012 September, 2012 − Rev. 2 1 Publication Order Number: ESD7481/D ESD7481MUT5G ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Parameter Symbol IPP Maximum Reverse Peak Pulse Current VC Clamping Voltage @ IPP VRWM IR VBR IT I IPP IT VC VBR VRWM IR IR VRWM VBR VC IT Working Peak Reverse Voltage V Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT IPP Test Current Bi−Directional TVS *See Application Note AND8308/D for detailed explanations of datasheet parameters. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified) Parameter Reverse Working Voltage Breakdown Voltage (Note 2) Symbol Conditions Min Typ Max Unit 3.3 V VRWM VBR IT = 1 mA 6.0 V Reverse Leakage Current IR VRWM = 3.3 V Clamping Voltage (Note 3) VC IPP = 1 A Clamping Voltage (Note 3) VC IPP = 3 A ESD Clamping Voltage VC Per IEC61000−4−2 See Figures 1 and 2 Junction Capacitance CJ VR = 0 V, f = 1 Mhz VR = 0 V, f < 1 GHz 0.25 0.15 Dynamic Resistance RDYN TLP Pulse 0.60 W f = 1 Mhz f = 8.5 GHz 0.030 0.234 dB Insertion Loss < 1.0 50 nA 10 V 12 V 0.40 0.30 pF 2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1. 3. Non−repetitive current pulse at TA = 25°C, per IEC61000−4−5 waveform. Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000−4−2 Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000−4−2 http://onsemi.com 2 ESD7481MUT5G 1.E−02 2.0 1.E−03 1.8 1.E−04 1.6 1.4 1.E−05 I1 (A) C (pF) 1.E−06 1.E−07 1.E−08 1.2 1.0 0.8 0.6 1.E−09 0.4 1.E−10 0.2 1.E−11 −8 −6 −4 −2 0 2 4 6 0 −5 8 −4 −3 −2 −1 V1 (V) 0 1 2 3 4 5 VBias (V) Figure 3. IV Characteristics Figure 4. CV Characteristics 0.6 1 0 0.5 −1 CAPACITANCE (pF) −2 dB −3 −4 −5 −6 −7 −8 0.4 0.3 0.2 0.1 5V 0V −9 −10 1.E+06 1.E+07 1.E+08 1.E+09 0.0 0.E+00 1.E+10 5.E+08 1.E+09 0 18 −2 16 −4 14 −6 CURRENT (A) CURRENT (A) Figure 6. Capacitance over Frequency 20 12 10 8 6 −8 −10 −12 −14 4 −16 2 −18 5 10 15 2.E+09 3.E+09 3.E+09 FREQUENCY FREQUENCY (Hz) Figure 5. RF Insertion Loss 0 0 2.E+09 20 −20 −25 25 −20 −15 −10 −5 VOLTAGE (V) VOLTAGE (V) Figure 7. Positive TLP I−V Curve Figure 8. Negative TLP I−V Curve http://onsemi.com 3 0 ESD7481MUT5G IEC61000−4−2 Waveform IEC 61000−4−2 Spec. Ipeak Level Test Voltage (kV) First Peak Current (A) Current at 30 ns (A) Current at 60 ns (A) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 100% 90% I @ 30 ns I @ 60 ns 10% tP = 0.7 ns to 1 ns Figure 9. IEC61000−4−2 Spec ESD Gun Oscilloscope TVS 50 W Cable 50 W Figure 10. Diagram of ESD Test Setup ESD Voltage Clamping at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D. For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000−4−2 waveform. Since the IEC61000−4−2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage % OF PEAK PULSE CURRENT 100 PEAK VALUE IRSM @ 8 ms tr 90 PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms 80 70 60 HALF VALUE IRSM/2 @ 20 ms 50 40 30 tP 20 10 0 0 20 40 t, TIME (ms) 60 Figure 11. 8 X 20 ms Pulse Waveform http://onsemi.com 4 80 ESD7481MUT5G PACKAGE DIMENSIONS X3DFN2, 0.62x0.32, 0.355P, (0201) CASE 152AF ISSUE O PIN 1 INDICATOR (OPTIONAL) 2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. A B D 0.035 C 2X DIM A A1 b D E e L E 0.035 C TOP VIEW 0.05 C A 2X 0.05 C A1 SIDE VIEW 1 0.05 M RECOMMENDED MOUNTING FOOTPRINT* SEATING PLANE 0.74 2X 0.30 1 e 2X C MILLIMETERS MIN MAX 0.25 0.33 −−− 0.05 0.22 0.28 0.62 BSC 0.32 BSC 0.355 BSC 0.17 0.23 2 2X b 2X 0.05 L M C A B BOTTOM VIEW 0.31 DIMENSIONS: MILLIMETERS C A B See Application Note AND8398/D for more mounting details *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 http://onsemi.com 5 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative ESD7481/D