CY7C131E, CY7C131AE CY7C136E, CY7C136AE 1 K / 2 K × 8 Dual-port Static RAM 1 K / 2 K × 8 Dual-port Static RAM Features Functional Description ■ True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K / 2 K × 8 organization ■ 0.35 micron complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ High speed access: 15 ns ■ Low operating power: ICC = 110 mA (typical), Standby: ISB3 = 0.05 mA (typical) CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are high-speed, low-power CMOS 1 K / 2 K × 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C131E / CY7C131AE / CY7C136E / CY7C136AE can be used as a standalone dual-port static RAM. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs. ■ Fully asynchronous operation ■ Automatic power-down ■ BUSY output flag to indicate access to the same location by both ports ■ INT flag for port-to-port communication ■ Available in 52-pin plastic leaded chip carrier (PLCC), 52-pin plastic quad flat package (PQFP) ■ Pb-free packages available Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). Two flags are provided on each port, BUSY and INT. The BUSY flag signals that the port is trying to access the same location, which is currently being accessed by the other port. The INT is an interrupt flag indicating that data is placed in a unique location[1]. The BUSY and INT flags are push pull outputs. An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins. The CY7C131E / CY7C131AE / CY7C136E / CY7C136AE are available in 52-pin Pb-free PLCC and 52-pin Pb-free PQFP. Logic Block Diagram R/WL CEL R/WR CER OEL OER I/O7L I/O CONTROL I/O0L [2] BUSYL I/O CONTROL I/O7R I/O0R [2] BUSYR A 9/10L [4] A 0L ADDR DECODER CEL OEL MEMORY ARRAY ADDR DECODER 7C131E/7C131AE/ ARBITRATION 7C136E/7C136AE LOGIC ARBITRATION (7C130/7C131 LOGIC ONLY) A 9/10R [4] A 0R CER AND INTERRUPT LOGIC OER INTERRUPT LOGIC R/WL R/WR [3] INTL [3] INTR Notes 1. Unique location used by interrupt flag: 1 K × 8: Left port reads from 3FE, Right port reads from 3FF; 2 K × 8: Left port reads from 7FE, Right port reads from 7FF. 2. BUSY is a push-pull output. No pull-up resistor required. 3. INT: push-pull output. No pull-up resistor required. 4. 1 K × 8: A0–A9, 2 K × 8: A0–A10, address lines are for both left and right ports. Cypress Semiconductor Corporation Document Number: 001-64231 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 15, 2013 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Contents Pin Configurations ........................................................... 3 Pin Definitions .................................................................. 3 Selection Guide ................................................................ 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance[10] ................................................................ 5 AC Test Loads and Waveforms ....................................... 5 Switching Characteristics ................................................ 6 Switching Characteristics ................................................ 8 Switching Waveforms .................................................... 10 Ordering Information ...................................................... 15 Ordering Code Definitions ......................................... 15 Package Diagrams .......................................................... 16 Acronyms ........................................................................ 17 Document Number: 001-64231 Rev. *E Document Conventions ................................................. 17 Units of Measure ....................................................... 17 Appendix: Silicon Errata for CY7C131E/131AE/136E/136AE 1K/2K × 8 Dual Port Static RAM ...................................................... 18 Part Numbers Affected .............................................. 18 CY7C131E/131AE/136E/136AE Qualification Status ........................................................... 18 CY7C131E/131AE/136E/136AE Errata Summary ............................................................... 18 Document History Page ................................................. 19 Sales, Solutions, and Legal Information ...................... 20 Worldwide Sales and Design Support ....................... 20 Products .................................................................... 20 PSoC Solutions ......................................................... 20 Page 2 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Pin Configurations Figure 1. Pin Diagram - 52-pin PLCC (Top View) [5] I/O5R I/O6R A6R A7R A8R A9R NC I/O7R CER R/WR BUSYL R/W L CEL VCC A0L OEL NC/A10L INTL OER A0R A1R A2R A3R A4R A5R BUSYR INTR NC/A10R [5] [5] BUSYR INTR NC/A10R 52 51 50 49 48 47 46 45 44 43 42 41 40 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 1 2 3 4 5 6 7 8 9 10 11 12 13 OER A0R A1R A2R A3R A4R A5R 39 38 37 36 35 34 33 32 31 30 29 28 27 7C131E/7C131AE 7C136E/7C131AE A6R A7R A8R A9R NC I/O7R I/O5R I/O6R I/O2R I/O3R I/O4R NC GND I/O0R I/O1R I/O 4L I/O 5L 14 15 16 17 18 19 20 21 22 23 24 25 26 I/O 6L I/O 7L CER R/WR I/O2R I/O3R I/O4R I/O0R I/O1R NC GND I/O 6L I/O 7L 7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C131E/7C131AE 40 7C136E/7C136AE 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 I/O 4L I/O 5L 8 9 10 11 12 13 14 15 16 17 18 19 20 BUSYL R/W L CEL VCC A0L OEL NC/A10L INTL [5] A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L Figure 2. Pin Diagram - 52-pin PQFP (Top View) Pin Definitions Left Port Right Port Description CEL CER Chip Enable R/WL R/WR Read/Write Enable OER Output Enable A0R–A9/10R[5] Address I/O0L–I/O7L I/O0R–I/O7R Data Bus Input/Output INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag OEL A0L–A9/10L [5] VCC Power GND Ground Selection Guide Parameter 7C131E-15 7C131AE-15 7C131E-25 7C136E-25 7C131E-55 7C136E-55 7C136AE-55 Unit Maximum Access Time 15 25 55 ns Typical Operating Current 110 100 95 mA Typical Standby Current for ISB1 (both ports TTL level) Typical Standby Current for ISB3 (Both ports CMOS level) 50 45 45 mA 0.05 0.05 0.05 mA Note 5. 1 K × 8: A0–A9, 2 K × 8: A0–A10, address lines are for both left and right ports. Document Number: 001-64231 Rev. *E Page 3 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE DC input voltage[8] .......................................–0.5 V to +7.0 V Maximum Ratings Exceeding maximum ratings [6] may shorten the useful life of the device. User guidelines are not tested. Output current into outputs (LOW) ............................. 20 mA Static discharge voltage .......................................... >1100 V Storage temperature ................................ –65 C to +150 C Latch up current ..................................................... >200 mA Ambient temperature with power applied .......................................... –55 C to +125 C Operating Range Supply voltage to ground potential ..............–0.3 V to +7.0 V Range Commercial Industrial DC voltage applied to outputs in High Z State .............................................–0.5 V to +7.0 V Ambient Temperature 0C to +70 C –40 C to +85 C VCC 5 V ± 10% 5 V ± 10% Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IOZ ICC ISB1 ISB2 ISB3 ISB4 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Output Leakage Current VCC Operating Supply Current Standby Current, Both Ports, TTL Inputs Standby Current, One Port, TTL Inputs Standby Current, Both Ports, CMOS Inputs Standby Current, One Port, CMOS Inputs Test Conditions VCC = Min, IOH = –4.0 mA VCC = Min, IOL = 4.0 mA GND < VO < VCC, Output disabled 7C131E-55 7C136E-55 Unit 7C136AE-55 Min Typ[9] Max Min Typ[9] Max Min Typ[9] Max 2.4 – – 2.4 – – 2.4 – V 7C131E-15 7C131AE-15 7C131E-25 7C136E-25 – – 0.4 – 0.4 – – 2.2 – – – – 2.2 – – – 0.8 – 0.8 – – 0.8 V –20 – +20 –20 – +20 –20 – +20 A 110 115 50 65 190 200 70 95 – 95 105 45 65 160 170 65 95 mA VCC = Max, IOUT = 0 mA Outputs disabled CEL and CER > VIH, f = fMAX[7] Commercial Industrial Commercial Industrial – CEL or CER > VIH, Active Port Outputs Open, f = fMAX[7] Both Ports CEL and CER > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0 One Port CEL or CER > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, Active Port Outputs Open, f = fMAX[7] Commercial Industrial – 120 135 180 205 Commercial Industrial – 0.05 0.05 Commercial Industrial – 110 125 – 2.2 0.4 V V 100 110 45 65 170 180 65 95 – – 110 135 160 205 – 110 135 160 205 mA 0.5 0.5 – 0.05 0.05 0.5 0.5 – 0.05 0.05 0.5 0.5 mA 160 175 – 100 125 140 175 – 100 125 140 175 mA – – mA Notes 6. The voltage on any I/O pin cannot exceed the power pin during power-up. 7. At f = fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3 V. 8. Pulse width < 20 ns. 9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25 °C. Document Number: 001-64231 Rev. *E Page 4 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Capacitance[10] Parameter Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 5.0 V Max Unit 15 pF 10 pF AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms 5V 5V R1 = 893 OUTPUT C = 30 pF OUTPUT R2 = 347 RTH = 250 R1 = 893 OUTPUT C = 30 pF C = 5 pF VTH = 1.4 V (a) Normal Load (Load 1) ALL INPUT PULSES 3.0 V GND 10% 90% 5 ns (b) Thévenin Equivalent (Load 1) R2 = 347 (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, and tLZWE including scope and jig) (CY7C131E/CY7C131AE ONLY) 90% 10% 5ns Note 10. Tested initially and after any design or process changes that may affect these parameters. Document Number: 001-64231 Rev. *E Page 5 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Switching Characteristics Over the Operating Range Parameter [11] Description 7C131E-15/7C131AE-15 Min 7C131E-25/7C136E-25 Max Min Max Unit Read Cycle tRC Read cycle time 15 – 25 – ns tAA Address to data valid [12] – 15 – 25 ns tOHA Data hold from Address change 3 – 3 – ns CE LOW to data valid [12] – 15 – 25 ns tDOE OE LOW to data valid [12] – 10 – 15 ns tLZOE OE LOW to Low Z [13, 14, 15] 3 – 3 – ns – 10 – 15 ns 3 – 5 – ns – 10 – 15 ns 0 – 0 – ns – 15 – 25 ns tACE OE HIGH to High Z tHZOE CE LOW to Low Z tLZCE [13, 14, 15] [13, 14, 15] [13, 14, 15] tHZCE CE HIGH to High Z tPU CE LOW to power-up [13] CE HIGH to power-down tPD Write Cycle [13] [16] tWC Write cycle time 15 – 25 – ns tSCE CE LOW to write end 12 – 20 – ns tAW Address setup to write end 12 – 20 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE R/W pulse width 10 – 12 – ns tSD Data setup to write end 10 – 15 – ns tHD Data hold from write end tHZWE[13] tLZWE[13] 0 – 0 – ns [15] – 10 – 15 ns R/W HIGH to Low Z [15] 3 – 3 – ns R/W LOW to High Z Notes 11. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V and output loading of the specified IOL/IOH, and 30 pF load capacitance. 12. AC Test Conditions use VOH = 1.6 V and VOL = 1.4 V. 13. This parameter is guaranteed but not tested. 14. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 15. Parameters tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5 pF as in part (c) of Figure 3 on page 5. Transition is measured ±500 mV from steady state voltage. 16. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate Document Number: 001-64231 Rev. *E Page 6 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Switching Characteristics (continued) Over the Operating Range Parameter [11] 7C131E-15/7C131AE-15 Description 7C131E-25/7C136E-25 Unit Min Max Min Max – 15 – 20 ns – 15 – 20 ns Busy/Interrupt Timing[17] tBLA BUSY LOW from Address match [18] tBHA BUSY HIGH from Address mismatch tBLC BUSY LOW from CE LOW – 15 – 20 ns tBHC BUSY HIGH from CE HIGH [18] – 15 – 20 ns tPS Port setup for priority 5 – 5 – ns tBDD BUSY HIGH to valid data – 15 – 25 ns [19] tDDD Write data valid to read data valid – 25 – 30 ns tWDD Write pulse to data delay [19] – 30 – 45 ns tWINS R/W to INTERRUPT set time – 15 – 25 ns tEINS CE to INTERRUPT set time – 15 – 25 ns tINS Address to INTERRUPT set time – 15 – 25 ns OE to INTERRUPT reset time [18] – 15 – 25 ns CE to INTERRUPT reset time [18] – 15 – 25 ns – 15 – 25 ns Interrupt Timing tOINR tEINR tINR Address to INTERRUPT reset time [18] Notes 17. Test conditions used are Load 2. 18. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state. 19. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B’s address toggled. CE for Port B is toggled. Document Number: 001-64231 Rev. *E Page 7 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Switching Characteristics Over the Operating Range Parameter Description 7C131E-55 7C136E-55 7C136AE-55 Min Max Unit Read Cycle tRC tAA tOHA tACE tDOE tLZOE Read cycle time Address to data valid [21] Data hold from Address change CE LOW to data valid [21] OE LOW to data valid [21] 55 – 3 – – – 55 – 55 25 ns ns ns ns ns OE LOW to Low Z [21, 22, 23] OE HIGH to High Z [21, 22, 23] CE LOW to Low Z [21, 22, 23] CE HIGH to High Z [21, 22, 23] CE LOW to power-up [22] CE HIGH to power-down [22] 3 – 5 – 0 – – 25 – 25 – 35 ns ns ns ns ns ns 55 40 40 2 0 30 20 0 – 3 – – – – – – – – 25 – ns ns ns ns ns ns ns ns ns ns – – – – 5 – 30 30 30 30 – 45 ns ns ns ns ns ns tHZOE tLZCE tHZCE tPU tPD Write Cycle tWC Write cycle time tSCE CE LOW to write end tAW Address setup to write end tHA Address hold from write end tSA Address setup to write start tPWE R/W pulse width tSD Data setup to write end tHD Data hold from write end tHZWE R/W LOW to High Z [24] R/W HIGH to Low Z [24] tLZWE Busy/Interrupt Timing[20] tBLA BUSY LOW from Address match tBHA BUSY HIGH from Address mismatch [25] tBLC BUSY LOW from CE LOW tBHC BUSY HIGH from CE HIGH [25] tPS Port setup for priority tBDD BUSY HIGH to valid data Notes 20. Test conditions used are Load 2. 21. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. 22. AC Test Conditions use VOH = 1.6 V and VOL = 1.4 V. 23. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state. 24. Parameters tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with C = 5 pF as in part (b) of Figure 3 on page 5. Transition is measured ±500 mV from steady state voltage. 25. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B’s address toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read. Document Number: 001-64231 Rev. *E Page 8 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Switching Characteristics (continued) Over the Operating Range Parameter Description tDDD Write data valid to read data valid [26] tWDD Write pulse to data delay [26] Interrupt Timing tWINS R/W to INTERRUPT set time tEINS CE to INTERRUPT set time tINS Address to INTERRUPT set time tOINR OE to INTERRUPT reset time [27] tEINR CE to INTERRUPT reset time [27] tINR Address to INTERRUPT reset time [27] 7C131E-55 7C136E-55 7C136AE-55 Min Max – 30 – 45 Unit ns ns – – – – 45 45 45 45 ns ns ns ns – – 45 45 ns ns Notes 26. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B’s address toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read. 27. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state. Document Number: 001-64231 Rev. *E Page 9 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Switching Waveforms Figure 4. Read Cycle No. 1 [28, 29] Either Port ADDR Access tRC ADDR tAA tOHA DATA OUT PREVIOUS DATAVALID DATA VALID Figure 5. Read Cycle No. 2 [28, 30] Either Port CE/OE Access CE tHZCE tACE OE tLZOE tHZOE tDOE tLZCE DATA VALID DATA OUT tPU tPD ICC ISB Figure 6. Write Cycle No. 1 (OE Three-States Data I/Os – Either Port) [31, 32] Either Port tWC ADDR tSCE CE tSA tAW tPWE tHA R/W tSD DATAIN tHD DATA VALID OE tHZOE HIGH IMPEDANCE DOUT Notes 28. R/W is HIGH for read cycle. 29. Device is continuously selected, CE = VIL and OE = VIL. 30. Address valid prior to or coincident with CE transition LOW. 31. The internal write time of the memory is defined by the overlap of CE LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input setup and hold timing must be referenced to the rising edge of the signal that terminates the write. 32. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data to be placed on the bus for the required tSD. Document Number: 001-64231 Rev. *E Page 10 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Switching Waveforms (continued) Figure 7. Write Cycle No. 2 (R/W Three-States Data I/Os – Either Port) [33, 34] tWC ADDR tSCE tHA CE tAW tSA tPWE[36] R/W tSD DATAIN tHD DATA VALID tLZWE [37] tHZWE HIGH IMPEDANCE DATAOUT Figure 8. Read Cycle No. 3 [35] Read with BUSY tRC ADDR R ADDR MATCH tPWE R/WR tHD DINR VALID ADDR MATCH ADDR L tPS tBHA BUSYL tBLA tBDD DOUTL VALID tWDD tDDD Notes 33. These parameters are measured from the input signal changing, until the output pin goes to a high impedance state. 34. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in a high impedance state. 35. CEL = CER = LOW. 36. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during a R/Wn controlled write cycle, this requirements does not apply and the write pulse can be as short as the specified tPWE. 37. Transition is measured ±500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested. Document Number: 001-64231 Rev. *E Page 11 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Switching Waveforms (continued) Figure 9. Busy Timing Diagram No. 1 (CE Arbitration)[38] CEL Valid First: ADDR L,R ADDR MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRL,R ADDR MATCH CER tPS CEL tBLC tBHC BUSYL Figure 10. Busy Timing Diagram No. 2 (ADDR Arbitration)[38] Left ADDR Valid First: tRC or tWC ADDR MATCH ADDRL ADDR MISMATCH tPS ADDR R tBLA tBHA BUSYR Right Address Valid First: tRC or tWC ADDR MATCH ADDRR ADDR MISMATCH tPS ADDRL tBLA tBHA BUSYL Note 38. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted. Document Number: 001-64231 Rev. *E Page 12 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Switching Waveforms (continued) Figure 11. Interrupt Timing Diagrams Left Side Sets INTR tWC ADDR L WRITE 3FF/7FF [40] [39] tINS tHA CEL tEINS R/WL tSA tWINS INTR Right Side Clears INTR tRC ADDRR READ 3FF/7FF [40] tHA [39] tINR CER tEINR R/WR OER tOINR INTR Notes 39. Parameter tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. 40. Parameter tHA depends on which enable pin (CEL or R/WL) is deasserted first. Document Number: 001-64231 Rev. *E Page 13 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Switching Waveforms (continued) Figure 12. Interrupt Timing Diagrams Right Side Sets INTL t WC ADDRR WRITE 3FE/7FE [41] tHA[42] tINS CER tEINS R/WR tSA tWINS INTL Left Side Clears INTL tRC ADDR R READ 3FE/7FE [42] tHA [41] tINR CEL tEINR R/WL OEL tOINR INTL Notes 41. Parameter tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. 42. Parameter tHA depends on which enable pin (CEL or R/WL) is deasserted first. Document Number: 001-64231 Rev. *E Page 14 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Ordering Information Speed (ns) Ordering Code Package Name Package Type Operating Range 1 K × 8 Dual-port SRAM 15 25 55 CY7C131AE-15JXI 51-85004 52-pin Pb-free Plastic Leaded Chip Carrier CY7C131E-15NXI 51-85042 52-pin Pb-free Plastic Quad Flatpack Industrial CY7C131E-25JXC 51-85004 52-pin Pb-free Plastic Leaded Chip Carrier CY7C131E-25NXC 51-85042 52-pin Pb-free Plastic Quad Flatpack CY7C131E-55JXC 51-85004 52-pin Pb-free Plastic Leaded Chip Carrier CY7C131E-55NXC 51-85042 52-pin Pb-free Plastic Quad Flatpack CY7C131E-55JXI 51-85004 52-pin Pb-free Plastic Leaded Chip Carrier CY7C131E-55NXI 51-85042 52-pin Pb-free Plastic Quad Flatpack CY7C136E-25JXC 51-85004 52-pin Pb-free Plastic Leaded Chip Carrier CY7C136E-25NXC 51-85042 52-pin Pb-free Plastic Quad Flatpack CY7C136E-25JXI 51-85004 52-pin Pb-free Plastic Leaded Chip Carrier Industrial CY7C136E-55JXC 51-85004 52-pin Pb-free Plastic Leaded Chip Carrier Commercial CY7C136E-55NXC 51-85042 52-pin Pb-free Plastic Quad Flatpack CY7C136AE-55JXI 51-85004 52-pin Pb-free Plastic Leaded Chip Carrier CY7C136AE-55NXI 51-85042 52-pin Pb-free Plastic Quad Flatpack Commercial Commercial Industrial 2 K × 8 Dual-port SRAM 25 55 Commercial Industrial Ordering Code Definitions CY 7 C 13X X E - XX X X X Temperature Grade: X = I or C I = Industrial; C = Commercial Pb-free Package Type: X = J or N J = 52-pin PLCC; N = 52-pin PQFP Speed Grade: XX = 15 ns or 25 ns or 55 ns Process Version R4 = E X = A or blank Part Identifier: 13X = 131 or 136 Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-64231 Rev. *E Page 15 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Package Diagrams Figure 13. 52-pin PLCC (0.756 × 0.756 Inches) J52 Package Outline, 51-85004 51-85004 *D Figure 14. 52-pin PQFP (10 × 10 × 2.0 mm) N5210 Package Outline, 51-85042 51-85042 *D Document Number: 001-64231 Rev. *E Page 16 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Acronyms Acronym Document Conventions Description Units of Measure CE Chip Enable CMOS Complementary Metal Oxide Semiconductor °C degree Celsius I/O Input/Output µA microampere OE Output Enable mA milliampere PLCC Plastic Leaded Chip Carrier mV millivolt PQFP Plastic Quad Flat Package ns nanosecond SRAM Static Random Access Memory ohm TTL Transistor-Transistor Logic % percent WE Write Enable pF picofarad V volt W watt Document Number: 001-64231 Rev. *E Symbol Unit of Measure Page 17 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Appendix: Silicon Errata for CY7C131E/131AE/136E/136AE 1K/2K × 8 Dual Port Static RAM This section describes the errata for the 1K/2K × 8 Dual Port Static RAM, CY7C131E/131AE/136E/136AE. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. Part Numbers Affected Part Number Device Characteristics CY7C131E/AE All Speed Grades CY7C136E/AE All Speed Grades CY7C131E/131AE/136E/136AE Qualification Status Product Status: In Production CY7C131E/131AE/136E/136AE Errata Summary This table defines the errata applicability to available CY7C131E/131AE/136E/136AE family devices. An "X" indicates that the errata pertains to the selected device. Note Errata items, in the table below, are hyperlinked. Click on any item entry to jump to its description. Items [1] Chip Disable Issue Part Number Silicon Revision CY7C131E/131AE/136E/13 6AE [X] Fix Status Fix in progress. Fixed samples to be available from early April 2012. 1. Chip Disable Issue ■ ■ ■ ■ ■ ■ Problem Definition Chip Enable pin (CE) does not tristate I/Os of the Dual Port RAM under certain input conditions. Parameters Affected tHZCE (CE HIGH to High Z). CE HIGH does not tristate the I/Os. Trigger Condition(s) Output Enable pin (OE) held LOW, R/W held HIGH and when chip is disabled (CE pin held HIGH). Scope of Impact Bus contention in shared bus architectures where data and control lines are shared. There is no impact of this issue in standalone architectures where data and control lines are not shared. Workaround Solutions to prevent bus contention: 1. The OE signal should be held HIGH when CE is disabled. This will ensure the data lines are tri-stated. 2. The R/W signal can be LOW(write mode) when CE is disabled. This prevents the Dual Port RAM from driving the data lines. Since CE is disabled, the memory is not corrupted. If these workarounds are not suitable for your application, Cypress will provide fixed samples that do not exhibit the chip disable issue. The timeline for this is mentioned in the Fix Status section. Fix Status This chip disable issue will be fixed in the new samples and will be available by early April 2012. Support for older parts (CY7C131/131A/136/136A) will be continued until early April 2012. Document Number: 001-64231 Rev. *E Page 18 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Document History Page Document Title: CY7C131E/CY7C131AE/CY7C136E/CY7C136AE, 1 K / 2 K × 8 Dual-port Static RAM Document Number: 001-64231 Rev. ECN No. Orig. of Change Submission Date ** 3038037 ADMU 09/24/2010 New data sheet *A 3394800 ADMU 10/04/2011 Changed status from Preliminary to Final. Updated Maximum Ratings (Removed (Pin 48 to Pin 24)). Updated Electrical Characteristics (changed minimum value of IOZ parameter from –10 µA to –20 µA, changed maximum value of IOZ parameter from +10 µA to +20 µA and changed maximum value of ISB3 from 0.5 mA to 15 mA for both Commercial and Industrial temperature ranges). Updated Package Diagrams (Updated revision of 51-85004 from *B to *C and revision of 51-85042 from *A to *C). Updated in new template. *B 3403147 ADMU 10/12/2011 No technical updates. *C 3435230 ADMU 11/17/2011 Updated Features (Removed a feature “Expandable data bus width to 16 bits or more using Master/Slave chip select when using more than one device.” and updated another feature to read as “BUSY output flag to indicate access to the same location by both ports.”. Updated Functional Description (Updated the sentence in the first paragraph to read as “The CY7C131E / CY7C131AE / CY7C136E / CY7C136AE can be used as a standalone dual-port static RAM.”. Updated Note 2 to read as “BUSY is a push-pull output. No pull-up resistor required.”. Updated Note 3 to read as “Interrupt: push-pull output. No pull-up resistor required.”. Updated Maximum Ratings (Removed “(per MIL-STD-883, Method 3015)”). Updated Electrical Characteristics (Removed the Note “See the last page of this specification for Group A subgroup testing information.” and its reference in Parameter column.). Updated Capacitance[10] (Changed maximum value of CIN parameter from 10 pF to 15 pF). Updated AC Test Loads and Waveforms. Updated Switching Characteristics (Removed the Note “See the last page of this specification for Group A subgroup testing information.” and its reference in Parameter column.). Updated Switching Characteristics (Changed the minimum value of tOHA from 0 ns to 3 ns). Removed the section “Typical DC and AC Characteristics”. Removed the section “Reference Documents”. *D 3620277 ADMU 06/15/2012 Added footnotes 9, 13, 17, 20, 36, 37, 39, 40, 41, and 42. Missing overbars updated. Removed “Slave Diagrams”. Updated Figure 3 with value 5 ns. Updated Maximum Ratings (updated Static discharge voltage from 2001 V to 1100 V). Corrected the typo in Electrical Characteristics. Updated Package Diagrams (51-85042 from Rev *C to *D). Updated ICC parameters in Electrical Characteristics table. Updated Typical Operating Current parameters in Selection Guide. *E 3997575 ADMU 05/15/2013 Updated Package Diagrams: spec 51-85004 – Changed revision from *C TO *D. Description of Change Added Appendix: Silicon Errata for CY7C131E/131AE/136E/136AE 1K/2K × 8 Dual Port Static RAM. Document Number: 001-64231 Rev. *E Page 19 of 20 CY7C131E, CY7C131AE CY7C136E, CY7C136AE Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2010-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-64231 Rev. *E Revised May 15, 2013 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 20 of 20