HUF75925P3, HUF75925D3ST
Data Sheet
December 2001
11A, 200V, 0.275 Ohm, N-Channel,
UltraFET® Power MOSFETs
Packaging
Features
JEDEC TO-220AB
JEDEC TO-252AA
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
GATE
SOURCE
DRAIN
(FLANGE)
HUF75925P3
HUF75925D3ST
• Ultra Low On-Resistance
- rDS(ON) = 0.275Ω, VGS = 10V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
Symbol
Ordering Information
D
PART NUMBER
G
BRAND
HUF75925P3
TO-220AB
75925P
HUF75925D3ST
TO-252AA
75925D
NOTE: When ordering, use the entire part number.
S
Absolute Maximum Ratings
PACKAGE
TC = 25oC, Unless Otherwise Specified
HUF75925P3,
HUF75925D3ST
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
200
V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
200
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±20
V
Drain Current
Continuous (TC= 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC= 100oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
11
8
Figure 4
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Figures 6, 14, 15
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
1.5
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 175
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
300
260
oC
oC
NOTE:
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
©2001 Fairchild Semiconductor Corporation
HUF75925P3, HUF75925D3ST Rev. B
HUF75925P3, HUF75925D3ST
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
200
-
-
V
VDS = 190V, VGS = 0V
-
-
1
µA
VDS = 180V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±20V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 11)
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
2
-
4
V
Drain to Source On Resistance
rDS(ON)
ID = 11A, VGS = 10V (Figure 9)
-
0.220
0.275
¾
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
TO-220
-
-
1.5
oC/W
Thermal Resistance Junction to
Ambient
RθJA
TO-220
-
-
62
oC/W
TO-252
-
-
100
oC/W
VDD = 100V, ID = 11A
VGS = 10V,
RGS = 12Ω
(Figures 18, 19)
-
-
45
ns
-
9
-
ns
-
21
-
ns
td(OFF)
-
60
-
ns
tf
-
27
-
ns
tOFF
-
-
130
ns
-
59
78
nC
-
32
42
nC
-
2.0
3.2
nC
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
tON
td(ON)
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
Qg(TOT)
VGS = 0V to 20V
Gate Charge at 10V
Qg(10)
VGS = 0V to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0V to 2V
Total Gate Charge
VDD = 100V,
ID = 11A,
Ig(REF) = 1.0mA
(Figures 13, 16, 17)
Gate to Source Gate Charge
Qgs
-
4.0
-
nC
Gate to Drain "Miller" Charge
Qgd
-
11
-
nC
-
1030
-
pF
-
120
-
pF
-
15
-
pF
MIN
TYP
MAX
UNITS
ISD = 11A
-
-
1.25
V
ISD = 5A
-
-
1.00
V
trr
ISD = 11A, dISD/dt = 100A/µs
-
-
190
ns
QRR
ISD = 11A, dISD/dt = 100A/µs
-
-
940
nC
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 12)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
©2001 Fairchild Semiconductor Corporation
SYMBOL
VSD
TEST CONDITIONS
HUF75925P3, HUF75925D3ST Rev. B
HUF75925P3, HUF75925D3ST
Typical Performance Curves
12
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
9
VGS = 10V
6
3
0.2
0
0
0
25
50
75
100
150
125
25
175
50
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
0.1
PDM
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
t1
t2
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
200
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
100
175 - TC
I = I25
150
VGS = 10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-5
10-4
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILIT Y
©2001 Fairchild Semiconductor Corporation
HUF75925P3, HUF75925D3ST Rev. B
HUF75925P3, HUF75925D3ST
Typical Performance Curves
(Continued)
100
10
100µs
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
1ms
10ms
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
0.1
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
100
1
100
10
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
STARTING TJ = 25oC
10
STARTING TJ = 150oC
1
0.001
500
0.01
0.1
1
10
tAV, TIME IN AVALANCHE (ms)
VDS , DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
20
20
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
15
10
TJ = 175oC
5
TJ = -55oC
15
VGS = 10V
VGS = 5V
10
5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
TJ = 25oC
0
0
2
3
4
VGS, GATE TO SOURCE VOLTAGE (V)
0
5
2
3
4
5
FIGURE 8. SATURATION CHARACTERISTICS
1.2
3.5
VGS = VDS, ID = 250µA
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
NORMALIZED GATE
THRESHOLD VOLTAGE
3.0
1
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
VGS = 4.5V
2.5
2.0
1.5
1.0
1.0
0.8
0.5
VGS = 10V, ID = 11A
0.0
-80
-40
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
200
0.6
-80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
HUF75925P3, HUF75925D3ST Rev. B
HUF75925P3, HUF75925D3ST
Typical Performance Curves
(Continued)
3000
VGS = 0V, f = 1MHz
ID = 250µA
1000
C, CAPACITANCE (pF)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
1.3
1.2
1.1
1.0
CISS = CGS + CGD
COSS ≅ CDS + CGD
100
CRSS = CGD
0.9
-80
-40
0
40
80
120
160
10
0.1
200
TJ , JUNCTION TEMPERATURE (oC)
10
100
200
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
VGS , GATE TO SOURCE VOLTAGE (V)
1
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10
VDD = 100V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 11A
ID = 5A
2
0
0
5
10
15
20
25
30
35
Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
VARY tP TO OBTAIN
REQUIRED PEAK IAS
tP
+
RG
-
VGS
VDS
IAS
VDD
VDD
DUT
0V
tP
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
©2001 Fairchild Semiconductor Corporation
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
HUF75925P3, HUF75925D3ST Rev. B
HUF75925P3, HUF75925D3ST
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
-
VDD
VGS = 10V
VGS
DUT
VGS = 2V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
-
VDD
10%
0
10%
DUT
90%
RGS
VGS
VGS
0
FIGURE 18. SWITCHING TIME TEST CIRCUIT
©2001 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 19. SWITCHING TIME WAVEFORM
HUF75925P3, HUF75925D3ST Rev. B
HUF75925P3, HUF75925D3ST
PSPICE Electrical Model
.SUBCKT HUF75925 2 1 3 ;
rev 19 October 2000
CA 12 8 1.6e-9
CB 15 14 1.75e-9
CIN 6 8 9.3e-8
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
5
51
ESLC
11
-
RDRAIN
6
8
EVTHRES
+ 19 8
+
LGATE
GATE
1
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
50
-
IT 8 17 1
EVTEMP
RGATE + 18 22
9
20
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.98e-1
RGATE 9 20 1.61
RLDRAIN 2 5 10
RLGATE 1 9 51.2
RLSOURCE 3 7 42.4
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
ESG
LDRAIN 2 5 1e-9
LGATE 1 9 5.12e-9
LSOURCE 3 7 4.24e-9
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 227
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RLSOURCE
S1A
12
S2A
14
13
13
8
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
RBREAK
15
VBAT
5
8
EDS
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*19),2.5))}
.MODEL DBODYMOD D (IS = 1e-12 N=1.02 RS = 7.75e-3 TRS1 = 2.5e-3 TRS2 = 2e-5 CJO = 8.5e-10 TT = 9.6e-6 M = 0.61 XTI=5.5)
.MODEL DBREAKMOD D (RS = 4. 2TRS1 = 1e- 3TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 1.15e- 9IS = 1e-30 N = 10 M = 0.86)
.MODEL MMEDMOD NMOS (VTO = 3.25 KP = 5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.61)
.MODEL MSTROMOD NMOS (VTO = 3.65 KP = 28 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 2.8 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 16.1 RS=.1)
.MODEL RBREAKMOD RES (TC1 =1.3e- 3TC2 = 2e-6)
.MODEL RDRAINMOD RES (TC1 = 1e-2 TC2 = 3.7e-5)
.MODEL RSLCMOD RES (TC1 = 4e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -1.3e-5)
.MODEL RVTEMPMOD RES (TC1 = -3e- 3TC2 = 1.9e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -7.5 VOFF= -.5)
VON = -.5 VOFF= -7.5)
VON = -0.1 VOFF= 0.2)
VON = 0.2 VOFF= -0.1)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
HUF75925P3, HUF75925D3ST Rev. B
HUF75925P3, HUF75925D3ST
SABER Electrical Model
REV 19 October 2000
template huf75925 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 1e-12, rs = 7.75e-3, xti = 5.5, trs1 = 2.5e-3, trs2 = 2e-5, cjo = 8.5e-10, tt = 9.6e-6, m = 0.61)
dp..model dbreakmod = (rs = 4.2, trs1 = 1e-3, trs2 = -8.9e-6)
dp..model dplcapmod = (cjo = 1.15e-9, isl = 10e-30, nl=10, m = 0.86)
m..model mmedmod = (type=_n, vto = 3.25, kp = 5, isl = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 3.65, kp = 28, isl = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 2.8, kp = 0.05, isl = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -7.5, voff = -.5)
DPLCAP 5
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -.5, voff = -7.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.1, voff = 0.2)
10
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.1)
DRAIN
2
RLDRAIN
RSLC1
51
c.ca n12 n8 = 1.6e-9
c.cb n15 n14 = 1.75e-9
c.cin n6 n8 = 9.3e-8
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
i.it n8 n17 = 1
LGATE
GATE
1
EVTHRES
+ 19 8
EVTEMP
RGATE + 18 22
9
20
21
11
DBODY
16
MWEAK
6
EBREAK
+
17
18
MMED
MSTRO
RLGATE
CIN
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1 = 1.3e-3, tc2 = 2e-6
res.rdrain n50 n16 = 1.98e-5, tc1 = 1e-2, tc2 =3.7e-5
res.rgate n9 n20 = 1.61
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 51.2
res.rlsource n3 n7 = 42.4
res.rslc1 n5 n51= 1e-6, tc1 = 4e-3, tc2 = -1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 10e-3, tc1 = 1e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -2e-3, tc2 = -1.3e-5
res.rvthres n22 n8 = 1, tc1 = -3e-3, tc2 = 1.9e-6
DBREAK
50
+
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 5.12e-9
l.lsource n3 n7 = 4.24e-9
LDRAIN
-
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
12
S2A
S1B
CA
RBREAK
15
14
13
13
8
17
18
RVTEMP
S2B
13
CB
+
+
6
8
EGS
-
19
-
IT
14
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 227
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6*19))** 2.5))
}
}
©2001 Fairchild Semiconductor Corporation
HUF75925P3, HUF75925D3ST Rev. B
HUF75925P3, HUF75925D3ST
SPICE Thermal Model
th
REV 19 October 2000
JUNCTION
HUF75925T
CTHERM1 th 6 8.0e-4
CTHERM2 6 5 2.6e-3
CTHERM3 5 4 3.5e-3
CTHERM4 4 3 5.2e-3
CTHERM5 3 2 7.0e-3
CTHERM6 2 tl 3.3e-2
RTHERM1 th 6 1.0e-3
RTHERM2 6 5 4.5e-3
RTHERM3 5 4 4.2e-2
RTHERM4 4 3 2.5e-1
RTHERM5 3 2 3.9e-1
RTHERM6 2 tl 5.0e-1
SABER Thermal Model
CTHERM1
RTHERM1
6
CTHERM2
RTHERM2
5
CTHERM3
RTHERM3
SABER thermal model HUF75925T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 8.0e-4
ctherm.ctherm2 6 5 = 2.6e-3
ctherm.ctherm3 5 4 = 3.5e-3
ctherm.ctherm4 4 3 = 5.2e-3
ctherm.ctherm5 3 2 = 7.0e-3
ctherm.ctherm6 2 tl = 3.3e-2
rtherm.rtherm1 th 6 = 1.0e-3
rtherm.rtherm2 6 5 = 4.5e-3
rtherm.rtherm3 5 4 = 4.2e-2
rtherm.rtherm4 4 3 = 2.5e-1
rtherm.rtherm5 3 2 = 3.9e-1
rtherm.rtherm6 2 tl = 5.0e-1
}
4
CTHERM4
RTHERM4
3
CTHERM5
RTHERM5
2
CTHERM6
RTHERM6
tl
©2001 Fairchild Semiconductor Corporation
CASE
HUF75925P3, HUF75925D3ST Rev. B
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Rev. H4