ISL84782 ® Data Sheet November 17, 2004 FN6097.3 Ultra Low ON-Resistance, Low-Voltage, Single Supply, Differential 4 to 1 Analog Multiplexer Features The Intersil ISL84782 device contains precision, bidirectional, analog switches configured as a differential 4-channel multiplexer/demultiplexer. It is designed to operate from a single +1.6V to +3.6V supply. The device has an inhibit pin to simultaneously open all signal paths. • ON Resistance (RON) - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5Ω - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.62Ω ON resistance is 0.5Ω with a +3V supply and 0.62Ω with a single +1.8V supply. Each switch can handle rail to rail analog signals. The off-leakage current is only 4nA max at +25°C and 30nA max at +85°C with a +3.3V supply. All digital inputs are 1.8V logic-compatible when using a single +3V supply. The ISL84782 is a differential 4 to 1 multiplexer device that is offered in a 16 Ld TSSOP package and a 16 Ld thin QFN package. • Pin Compatible Replacement for the MAX4782 and MAX4618 • RON Matching Between Channels. . . . . . . . . . . . . . . . 0.12Ω • RON Flatness Across Signal Range . . . . . . . . . . . . . .0.056Ω • Single Supply Operation. . . . . . . . . . . . . . . . . +1.6V to +3.6V • Low Power Consumption (PD). . . . . . . . . . . . . . . . . . <0.2µW • Fast Switching Action (VS = +3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13ns • Guaranteed Break-Before-Make • High Current Handling Capacity (300mA Continuous) • Available in 16 Ld 3x3 Thin QFN and 16 Ld TSSOP Table 1 summarizes the performance of this family. TABLE 1. FEATURES AT A GLANCE • 1.8V CMOS-Logic Compatible (+3V Supply) ISL84782 • Pb-Free Available (RoHS Compliant) (see Ordering Info) Configuration Diff 4:1 Mux 3V RON 0.5Ω 3V tON/tOFF 16ns/13ns 1.8V RON 0.62Ω 1.8V tON/tOFF 24ns/16ns Packages 16 Ld TSSOP, 16 Ld 3x3 Thin QFN • ISL84782IR Replaces the ISL43L740IR. Applications • Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops • Portable Test and Measurement Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Medical Equipment • Audio and Video Switching • Application Note AN557 “Recommended Test Procedures for Analog Switches” 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL84782 (Note 1) COMA 3 14 B1 B2 15 B2 V+ 16 V+ A2 2 A0 A0 1 ISL84782IR (3x3 THIN QFN) TOP VIEW A2 ISL84782IV (TSSOP) TOP VIEW 16 15 14 13 COMA 1 12 B1 A3 4 13 COMB A3 2 11 COMB A1 5 12 B0 A1 3 10 B0 INH 6 11 B3 INH 4 9 B3 6 7 8 ADD1 5 ADD0 9 ADD0 GND 8 GND 10 ADD1 LOGIC N.C. 7 N.C. Pinouts NOTE: 1. Switches Shown for Logic “0” Inputs. Truth Table Ordering Information ISL84782 INH ADD0 ADD1 SWITCH ON 1 X X None 0 0 0 A0, B0 0 0 1 A1, B1 0 1 0 A2, B2 0 1 1 A3, B3 PART NO. TEMP. RANGE (°C) PACKAGE PKG. DWG. # ISL84782IV -40 to 85 16 Ld TSSOP M16.173 ISL84782IV-T -40 to 85 16 Ld TSSOP Tape & Reel M16.173 ISL84782IR -40 to 85 16 Ld 3x3 Thin QFN L16.3x3A ISL84782IR-T -40 to 85 16 Ld 3x3 Thin QFN L16.3x3A Tape & Reel NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V, with a 3V supply. X = Don’t Care. ISL84782IVZ (See Note) -40 to 85 16 Ld TSSOP (Pb-free) M16.173 Pin Descriptions ISL84782IVZ-T (See Note) -40 to 85 16 Ld TSSOP Tape and Reel (Pb-free) M16.173 ISL84782IRZ (See Note) -40 to 85 16 Ld 3x3 Thin QFN L16.3x3A (Pb-free) ISL84782IRZ-T (See Note) -40 to 85 16 Ld 3x3 Thin QFN L16.3x3A Tape and Reel (Pb-free) PIN V+ FUNCTION System Power Supply Input (1.6V to 3.6V) N.C. No Connect. Not internally connected. GND Ground Connection INH Digital Control Input. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. COMA Analog Switch Channel A Output COMB Analog Switch Channel B Output A0-A3 Analog Switch Channel A Input B0-B3 Analog Switch Channel B Input ADDx Address Input Pin 2 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. FN6097.3 November 17, 2004 ISL84782 Absolute Maximum Ratings Thermal Information V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V Input Voltages INH, Ax, Bx, ADDx (Note 2) . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V Output Voltages COMx (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V Continuous Current NO or COM . . . . . . . . . . . . . . . . . . . . . ±300mA Peak Current NO or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA ESD Rating HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kV Thermal Resistance (Typical, Note 3) θJA (°C/W) 16 Ld TSSOP Package . . . . . . . . . . . . . . . . . . . . . . 150 16 Ld 3x3 QFN Thin Package . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. Signals on Ax, Bx, COMx, ADDx, or INH exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications - 3V Supply Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 8), Unless Otherwise Specified TEMP (°C) (NOTE 5) MIN TYP Full 0 - V+ V 25 - 0.5 0.75 Ω Full - - 0.8 Ω 25 - 0.12 0.2 Ω Full - - 0.2 Ω 25 - 0.056 0.15 Ω Full - - 0.15 Ω 25 -4 - 4 nA Full -30 - 30 nA 25 -8 - 8 nA Full -60 - 60 nA Input Voltage High, VINH, VADDH Full 1.4 - - V Input Voltage Low, VINL, VADDL Full - - 0.5 V Input Current, IINH, IINL, IADDH, IADDL V+ = 3.6V, VINH = VADD = 0V or V+ (Note 10) Full -0.5 - 0.5 µA 25 - 16 25 ns Full - - 27 ns 25 - 14 23 ns Full - - 25 ns 25 - 19 28 ns Full - - 30 ns 25 - 4 - ns Full 1 - - ns PARAMETER TEST CONDITIONS (NOTE 5) MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG V+ = 2.7V, ICOM = 100mA, VAX or VBX = 0V to V+, (See Figure 5) ON Resistance, RON RON Matching Between Channels, ∆RON V+ = 2.7V, ICOM = 100mA, VAX or VBX = Voltage at max RON, (Note 6) RON Flatness, RFLAT(ON) V+ = 2.7V, ICOM = 100mA, VAX or VBX = 0V to V+, (Note 7) Ax or Bx OFF Leakage Current, IAx(OFF) or IBx(OFF) V+ = 3.3V, VCOM = 0.3V, 3V, VAX or VBX = 3V, 0.3V COM ON Leakage Current, ICOM(ON) V+ = 3.3V, VCOM = VAX or VBX = 0.3V, 3V DIGITAL INPUT CHARACTERISTICS DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON V+ = 2.7V, VAx or VBx = 1.5V, RL = 50Ω, CL = 35pF, (See Figure 1, Note 10) Inhibit Turn-OFF Time, tOFF V+ = 2.7V, VAx or VBx = 1.5V, RL = 50Ω, CL = 35pF, (See Figure 1, Note 10) Address Transition Time, tTRANS Break-Before-Make Time, tBBM V+ = 2.7V, VAX or VBX = 1.5V, RL = 50Ω, CL = 35pF, (See Figure 1, Note 10) V+ = 3.3V, VAX or VBX = 1.5V, RL = 50Ω, CL = 35pF, (See Figure 3, Note 10) 3 FN6097.3 November 17, 2004 ISL84782 Electrical Specifications - 3V Supply Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 8), Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP (°C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - -65 - pC Input OFF Capacitance, COFF f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) 25 - 62 - pF COM OFF Capacitance, COFF f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) 25 - 218 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) 25 - 232 - pF OFF Isolation RL = 50Ω, CL = 35pF, f = 100kHz, (See Figures 4 and 6) 25 - 65 - dB 25 - -100 - dB f = 20Hz to 20kHz, 0.5Vp-p, RL = 32Ω 25 - 0.02 - % Full 1.6 - 3.6 V 25 - - 0.05 µA Full - - 0.9 µA Crosstalk, (Note 9) Total Harmonic Distortion (THD) POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 3.6V, VINH, VADD = 0V or V+, Switch On or Off NOTES: 4. VIN = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. RON matching between channels is calculated by subtracting the channel with the highest max Ron value from the channel with lowest max Ron value. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation. 9. Between any two switches. 10. Guaranteed but not tested. Electrical Specifications: 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Notes 4, 8), Unless Otherwise Specified TEMP (°C) MIN (NOTE 5) TYP Full 0 - V+ V 25 - 0.63 0.85 Ω Full - - 0.9 Ω 25 - 0.12 - Ω Full - 0.12 - Ω 25 - 0.14 - Ω Full - 0.14 - Ω Input Voltage High, VINH, VADDH Full 1 - - V Input Voltage Low, VINL, VADDL Full - - 0.4 V V+ = 1.8V, VINH, VADD = 0V or V+ (Note 10) Full -0.5 - 0.5 µA V+ = 1.8V, VAx or VBx = 1.0V, RL = 50Ω, CL = 35pF, (See Figure 1, Note 10) 25 - 24 33 ns Full - - 35 ns PARAMETER TEST CONDITIONS MAX (NOTE 5) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG V+ = 1.8V, ICOM = 10.0mA, VAX or VBX = 1.0V, (See Figure 5) ON Resistance, RON RON Matching Between Channels, ∆RON) V+ = 1.8V, ICOM = 10.0mA, VAX or VBX = 1.0V, (See Figure 5) RON Flatness, RFLAT(ON) V+ = 1.8V, ICOM = 10.0mA, VAX or VBX = 0V, 0.9V, 1.6V, (See Figure 5) DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON 4 FN6097.3 November 17, 2004 ISL84782 Electrical Specifications: 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Notes 4, 8), Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS Inhibit Turn-OFF Time, tOFF V+ = 1.8V, VAx or VBx = 1.0V, RL = 50Ω, CL = 35pF, (See Figure 1, Note 10) Address Transition Time, tTRANS V+ = 1.8V, VAX or VBX = 1.0V, RL = 50Ω, CL = 35pF, (See Figure 1, Note 10) TEMP (°C) MIN (NOTE 5) TYP MAX (NOTE 5) UNITS 25 - 16 25 ns Full - - 27 ns 25 - 25 34 ns Full - - 36 ns Break-Before-Make Time, tBBM V+ = 1.8V, VAX or VBX = 1.0V, RL = 50Ω, CL = 35pF, (See Figure 3, Note 10) 25 - 9 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - -39 - pC Test Circuits and Waveforms V+ LOGIC INPUT tr < 5ns tf < 5ns 50% VA0, VB0 90% V+ VOUT A0, B0 A1,A2,B1, B2,A3,B3 90% Logic input waveform is inverted for switches that have the opposite logic sense. GND ADD0-1 C 0V RL 50Ω CL 35pF FIGURE 1B. INHIBIT tON/tOFF TEST CIRCUIT tr < 5ns tf < 5ns 50% VOUT Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1A. INHIBIT tON/tOFF MEASUREMENT POINTS V+ COMA COMB INH LOGIC INPUT 0V tOFF LOGIC INPUT C 0V tON SWITCH OUTPUT V+ C V+ C tTRANS V+ VOUT VA0, VB0 A0, B0 90% SWITCH OUTPUT COMA, COMB ADD0-1 GND INH 0V VOUT RL 50Ω LOGIC INPUT 10% VA3, VB3 A1,A2,B1, B2,A3,B3 CL 35pF tTRANS Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for other switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R +R L FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS ( ON ) FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT FIGURE 1. SWITCHING TIMES 5 FN6097.3 November 17, 2004 ISL84782 Test Circuits and Waveforms (Continued) V+ C V+ LOGIC INPUT OFF OFF VOUT RG ON Ax, Bx 0V COMA, COMB 0Ω SWITCH OUTPUT VOUT ∆VOUT ADD1 ADD0 VG CHANNEL SELECT GND INH CL 1000pF LOGIC INPUT Q = ∆VOUT x CL Repeat test for other switches. FIGURE 2B. Q TEST CIRCUIT FIGURE 2A. Q MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION V+ C C tr < 5ns tf < 5ns V+ A0-A3 B0-B3 V+ LOGIC INPUT VOUT 90% 0V tBBM CL 35pF RL 50Ω ADD0-1 0V SWITCH OUTPUT VOUT COMA COMB LOGIC INPUT GND INH Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3A. tBBM MEASUREMENT POINTS FIGURE 3B. tBBM TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME V+ 10nF V+ C SIGNAL GENERATOR RON = V1/100mA Ax or Bx Ax or Bx 0V or V+ ADD1 ADD0 ANALYZER COMx GND VX 100mA CHANNEL SELECT V1 ADD1 ADD0 INH COMA or COMB GND RL Off-Isolation is measured between COM and “Off” NO terminal on each switch. Signal direction through switch is reversed and worst case values are recorded. FIGURE 4. OFF ISOLATION TEST CIRCUIT 6 0V or V+ CHANNEL SELECT INH FIGURE 5. RON TEST CIRCUIT FN6097.3 November 17, 2004 ISL84782 Test Circuits and Waveforms (Continued) V+ SIGNAL GENERATOR C V+ 50Ω Ax 0V or V+ CHANNEL SELECT COMA Ax or Bx ADD1 ADD0 COMB ADD1 ADD0 IMPEDANCE ANALYZER Bx ANALYZER C GND N.C. CHANNEL SELECT COMA or COMB GND INH 0V or V+ INH RL Crosstalk is measured between adjacent channels with one channel ON and the other channel OFF. Signal direction through switch is reversed and worst case values are recorded. FIGURE 6. CROSSTALK TEST CIRCUIT Detailed Description The ISL84782 analog multiplexer offers precise switching capability from a single 1.6V to 3.6V supply with low onresistance (0.5Ω) and high speed operation (tON = 16ns, tOFF = 13ns). The device is especially well suited for portable battery powered equipment thanks to the low operating supply voltage (1.6V), low power consumption (0.2µW), low leakage currents (60nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. Supply Sequencing and Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. This method is not applicable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These 7 FIGURE 7. CAPACITANCE TEST CIRCUIT additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch signal range is reduced and the resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION RESISTOR FOR LOGIC INPUTS 1kΩ 1kΩ OPTIONAL PROTECTION DIODE V+ ADDX INH VNOx VCOM GND OPTIONAL PROTECTION DIODE FIGURE 8. OVERVOLTAGE PROTECTION Power-Supply Considerations The ISL84782 construction is typical of most CMOS analog switches, in that it has two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set its analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL84782 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 3.6V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 1.6V but the part will operate with a supply below 1.5V. It is important to note that the input signal range, switching times, and on- FN6097.3 November 17, 2004 ISL84782 resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switched V+ and V- signals to drive the analog switch gate terminals. Logic-Level Thresholds This device is 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2.0V to 3.6V (see Figure 13). At 3.6V the VIH level is about 1.27V. This is still below the 1.8V CMOS guaranteed high output minimum level of 1.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. High-Frequency Performance In 50Ω systems, signal response is reasonably flat even past 10MHz with a -3dB bandwidth of 70MHz (see Figure 17). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch’s input to its output. Off Isolation is the resistance to this feed through, while Crosstalk indicates the amount of feed through from one switch to another. Figure 18 details the high Off Isolation and Crosstalk rejection provided by this family. At 100kHz, Off Isolation is about 65dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND. Typical Performance Curves TA = 25°C, Unless Otherwise Specified 0.75 0.65 V+ = 3V ICOM = 100mA ICOM = 100mA V+ = 1.65V 0.7 0.6 0.65 0.6 RON (Ω) RON (Ω) 0.55 V+ = 1.8V 0.55 V+ = 3V 0.45 0.5 25°C 0.45 V+ = 2.7V 0.5 85°C 0.4 -40°C V+ = 3.6V 0.4 0.35 0 1 2 VCOM (V) 3 FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE 8 4 0 0.5 1 1.5 VCOM (V) 2 2.5 3 FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE FN6097.3 November 17, 2004 ISL84782 Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued) -10 0.75 V+ = 1.8V ICOM = 100mA 0.7 -20 -30 0.65 85°C -50 0.6 0.55 -60 Q (pC) RON (Ω) V+ = 1.8V -40 25°C -70 -80 0.5 V+ = 3V -90 0.45 -100 -40°C 0.4 -110 0 0.5 1 1.5 2 0 0.5 1 VCOM (V) FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE 1.5 VCOM (V) 2 2.5 3 FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE 1.6 60 1.4 1.2 VINH tRANS (ns) VINH AND VINL (V) 50 1 VINL 0.8 40 30 85°C 20 0.6 10 1 1.5 2 2.5 3 3.5 4 4.5 -40°C 1 1.5 2 V+ (V) FIGURE 13. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE 25°C 2.5 3 V+ (V) 3.5 4 4.5 FIGURE 14. ADDRESS TRANS TIME vs SUPPLY VOLTAGE 25 60 50 40 tOFF (ns) tON (ns) 20 30 85°C 25°C 85°C 25°C 15 -40°C 20 10 -40°C 10 1 1.5 2 2.5 3 V+ (V) 3.5 4 4.5 FIGURE 15. INHIBIT TURN - ON TIME vs SUPPLY VOLTAGE 9 1 1.5 2 2.5 3 3.5 4 4.5 V+ (V) FIGURE 16. INHIBIT TURN - OFF TIME vs SUPPLY VOLTAGE FN6097.3 November 17, 2004 ISL84782 0 V+ = 3V GAIN 0 PHASE 20 40 60 80 RL = 50Ω VIN = 0.2VP-P to 2VP-P 0.1 100 1 10 100 FREQUENCY (MHz) FIGURE 17. FREQUENCY RESPONSE CROSSTALK (dB) -10 -10 20 -20 30 -30 40 -40 50 -50 60 ISOLATION -60 70 -70 80 -80 OFF ISOLATION (dB) 0 10 V+ = 3V PHASE (DEGREES) NORMALIZED GAIN (dB) Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued) 90 CROSSTALK -90 -100 1k 100 10k 100k 1M 10M 110 100M 500M FREQUENCY (Hz) FIGURE 18. CROSSTALK AND OFF ISOLATION Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND (QFN Paddle Connection: To Ground or Float) TRANSISTOR COUNT: 228 PROCESS: Submicron CMOS 10 FN6097.3 November 17, 2004 ISL84782 Thin Shrink Small Outline Plastic Packages (TSSOP) M16.173 N 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INDEX AREA E 0.25(0.010) M 2 INCHES E1 GAUGE PLANE -B1 B M MIN MAX MIN MAX NOTES A - 0.043 - 1.10 - 0.05 0.15 - 0.85 0.95 - A2 L 0.05(0.002) -A- SYMBOL A1 3 A D -C- e α c 0.10(0.004) C A M B S 0.002 0.0075 0.012 0.19 0.30 9 0.0035 0.008 0.09 0.20 - D 0.193 0.201 4.90 5.10 3 E1 0.169 0.177 4.30 4.50 4 0.026 BSC E 0.246 L 0.020 α 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 0.037 c N NOTES: 0.006 0.033 b e A2 A1 b 0.10(0.004) M 0.25 0.010 SEATING PLANE MILLIMETERS 0.65 BSC 0.256 6.25 0.028 0.50 16 0o - 6.50 0.70 16 8o 0o 6 7 8o Rev. 1 2/02 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) 11 FN6097.3 November 17, 2004 ISL84782 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP) ) 2X L16.3x3A 0.15 C A D A 16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE 9 MILLIMETERS D/2 D1 D1/2 2X N 6 INDEX AREA 0.15 C B 1 2 3 E1/2 E/2 E1 MIN NOMINAL MAX NOTES A 0.70 0.75 0.80 - A1 - - 0.05 - A2 - - 0.80 9 0.30 5, 8 A3 b E 9 0.20 REF 0.18 D 2X TOP VIEW 0.15 C A D2 B A2 0 A / / 0.10 C C A3 SIDE VIEW 9 5 NX b 4X P E 3.00 BSC - 2.75 BSC 9 1.35 1.50 1.65 7, 8, 10 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 2 8 Nd 4 3 NX k Ne 4 3 D2 2 N 1 (DATUM A) 2 3 6 INDEX AREA E2/2 N e 9 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 5 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. SECTION "C-C" 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. C L L L1 10 L e TERMINAL TIP FOR ODD TERMINAL/SIDE 9 12 3. Nd and Ne refer to the number of terminals on each D and E. A1 e 0.60 - 2. N is the number of terminals. NX b 10 - - 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 8 BOTTOM VIEW C L - θ NOTES: 9 CORNER OPTION 4X (Nd-1)Xe REF. P Rev. 0 6/04 (Ne-1)Xe REF. E2 7 NX L C C 7, 8, 10 16 7 L1 9 1.65 N 4X P 8 1.50 0.10 M C A B D2 (DATUM B) A1 - 2.75 BSC 1.35 e SEATING PLANE 9 E1 E2 0.08 C 0.23 3.00 BSC D1 0.15 C B 2X 4X SYMBOL FOR EVEN TERMINAL/SIDE 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2 and D2 MAX dimension. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN6097.3 November 17, 2004