SUTEX HV2203 Low charge injection, 8-channel high voltage analog switch Datasheet

HV2203
Low Charge Injection, 8-Channel
High Voltage Analog Switch
Features
General Description
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The Supertex HV2203 is a low charge injection 8-channel high
voltage analog switch integrated circuit (IC) intended for use in
applications requiring high voltage switching controlled by low
voltage signals, such as medical ultrasound imaging, piezoelectric
transducer driver, and printers.
HVCMOS technology for high performance
3.3V or 5.0V CMOS input logic level
20MHz data shift clock frequency
Very low quiescent power dissipation - 10µA
Low parasitic capacitance
DC to 10MHz analog signal frequency
-60dB typical off-isolation at 5MHz
CMOS logic circuitry for low power
Excellent noise immunity
Cascadable serial data register with latches
Flexible operating supply voltages
Data is input into an 8-bit shift register that can then be retained
in an 8-bit latch. To reduce any possible clock feed-through noise,
the latch enable bar should be left high until all bits are clocked in.
Data is clocked in during the rising edge of the clock.
Using HVCMOS technology, this device combines high voltage
bilateral DMOS switches and low power CMOS logic to provide
efficient control of high voltage analog signals.
Applications
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The device is suitable for various combinations of high voltage
supplies, e.g., VPP/VNN: +40V/-120V, +80V/-80V, and +120V/-40V.
Medical ultrasound imaging
NDT metal flaw detection
Piezoelectric transducer drivers
Inkjet printer heads
Optical MEMS modules
Block Diagram
LATCHES
CLK
DIN
8-BIT
SHIFT
REGISTER
LEVEL
OUTPUT
SHIFTERS &
SWITCHES
CHARGE CONTROL
D
LE
CLR
SW0
D
LE
CLR
SW1
D
LE
CLR
SW2
D
LE
CLR
SW6
D
LE
CLR
SW7
DOUT
VDD GND
LE
CLR
VNN VPP
HV2203
Pin Configurations
Ordering Information
Device
HV2203
Package Options
25
36
24
37
48-Lead LQFP
28-Lead PLCC
HV2203FG-G
HV2203PJ-G
-G indicates package is RoHS compliant (‘Green’)
13
48
1
12
48-Lead LQFP (FG)
Absolute Maximum Ratings
Parameter
VDD logic supply
Value
-0.5V to +6.5V
VPP-VNN differential supply
VPP positive supply
VNN negative supply
Logic input voltage
170V
-0.5V to VNN+170V
+0.5V to -170V
Analog signal range
VNN to VPP
Peak analog signal current/channel
Storage temperature
1.0A
-65°C to 150°C
Thermal resistance (θja):
48-Lead LQFP (FG)
Top Marking
H V 2203FG
LLLLLLLLL
Bottom Marking
CCCCCCCC
AAA
Operating Conditions
Parameter
Value
VDD
Logic power supply voltage
3.0V to 5.5V
VPP
Positive high voltage supply
40V to VNN +160V
VNN
Negative high voltage supply
VIH
High level input voltage
0.9VDD to VDD
VIL
Low-level input voltage
0V to 0.1VDD
VSIG
Analog signal voltage peak-to-peak
TA
Product Marking
YYWW
61OC/W
Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation under these conditions is not implied. Continuous operation of the device at
the absolute rating level may affect device reliability. All voltages are referenced to device ground.
Sym
28-Lead PLCC (PJ)
-0.5V to VDD +0.3V
-40V to -120V
Operating free air temperature
O
O
0 C to 70 C
Notes:
1. Power up/down sequence is arbitrary except GND must be powered-up first and powereddown last.
2. VSIG must be VNN ≤ VSIG ≤ VPP or floating during power up/down transition.
3. Rise and fall times of power supplies VDD, VPP, and VNN should not be less than 1.0msec.
2
*May be part of top marking
48-Lead LQFP (FG)
Top Marking
YYWW
HV2203PJ
LLLLLLLLLL
VNN +10V to VPP -10V
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin*
A = Assembler ID*
= “Green” Packaging
Bottom Marking
CCCCCCCCCCC
AAA
YY = Year Sealed
WW = Week Sealed
L = Lot Number
C = Country of Origin
A = Assembler ID*
= “Green” Packaging
*May be part of top marking
28-Lead PLCC (PJ)
HV2203
DC Electrical Characteristics
(Over operating conditions unless otherwise specified )
Sym Parameter
0OC
+25OC
+70OC
Units Conditions
Min
Max
Min
Typ
Max
Min
Max
-
-
-
50
60
-
-
ISIG = 5.0mA
-
-
-
42
51
-
-
ISIG = 200mA
-
-
-
40
48
-
-
-
-
-
32
39
-
-
-
-
-
38
46
-
-
ISIG = 5.0mA
-
-
-
29
35
-
-
ISIG = 200mA
Small signal switch
on-resistance matching
-
20
-
5.0
20
-
20
%
ISIG = 5.0mA, VPP = +80V,
VNN = -80V
RONL
Large signal switch
on-resistance
-
-
-
30
-
-
-
Ω
VSIG = VPP -10V, ISIG = 0.5A
ISOL
Switch off leakage per switch
-
5.0
-
1.0
10
-
15
μA
VSIG = VPP -10V, VNN +10V
DC offset switch off
-
300
-
100
300
-
300
DC offset switch on
-
500
-
100
500
-
500
mV
100kΩ load
IPPQ
Quiescent VPP supply current
-
-
-
10
50
-
-
μA
All switches off
INNQ
Quiescent VNN supply current
-
-
-
-10
-50
-
-
μA
All switches off
IPPQ
Quiescent VPP supply current
-
-
-
10
50
-
-
μA
All switches on, ISW = 5.0mA
INNQ
Quiescent VNN supply current
-
-
-
-10
-50
-
-
μA
All switches on, ISW = 5.0mA
ISW
Switch output peak current
-
-
-
1.0
-
-
-
A
VSIG duty cycle < 0.1%, 1.0μs
fSW
Output switching
frequency
-
-
-
-
50
-
-
kHz
-
-
1.0
1.2
1.5
-
-
-
-
1.0
1.2
1.5
-
-
-
-
1.0
1.2
1.5
-
-
VPP = +120V
VNN = -40V
-
-
1.0
1.2
1.5
-
-
VPP = +40V
VNN = -120V
-
-
1.0
1.2
1.5
-
-
-
-
1.0
1.2
1.5
-
-
RONS
ΔRONS
VOS
IPP
INN
Small signal switch
on-resistance
Average VPP supply current
Average VNN supply current
Ω
ISIG = 5.0mA
ISIG = 200mA
mA
VPP = +80V
VNN = -80V
VPP = +120V
VNN = -40V
Duty cycle = 50%
VPP = +40V
VNN = -120V
mA
VPP = +40V
VNN = -120V
VPP = +80V
VNN = -80V
VPP = +80V
VNN = -80V
VPP = +120V
VNN = -40V
All output
switches are
turning on
and off at
50kHz with
no load
All output
switches are
turning on
and off at
50kHz with
no load
IDD
Average VDD supply current
-
4.0
-
-
4.0
-
4.0
mA
fCLK = 5.0MHz, VDD = 5.0V
IDDQ
Quiescent VDD supply current
-
10
-
-
10
-
10
μA
All logic inputs are static
ISOR
Data out source current
0.45
-
0.45
0.70
-
0.40
-
mA
VOUT = VDD -0.7V
ISINK
Data out sink current
0.45
-
0.45
0.70
-
0.40
-
mA
VOUT = 0.7V
CIN
Logic input capacitance
-
10
-
-
10
-
10
pF
---
3
HV2203
AC Electrical Characteristics
(Over recommended operating conditions: VDD = 5.0V, tR = tF ≤5ns, 50% duty cycle, CLOAD = 20pF, unless otherwise specified)
Sym
Parameter
tSD
Set up time before LE rises
tWLE
Time width of LE
tDO
Clock delay time to data out
tWCL
Time width of CLR
tSU
Set up time data to clock
tH
Hold time data from clock
fCLK
Clock frequency
tR, tF
0OC
+25OC
+70OC
Min
Max
Min
Typ
Max
Min
Max
25
-
25
-
-
25
-
56
-
-
56
-
56
-
Conditions
ns
ns
12
-
-
12
-
12
-
50
100
50
78
100
50
100
40
15
30
40
15
40
55
-
55
-
-
55
-
21
-
-
21
-
21
-
-
-
7.0
-
7.0
-
2.0
-
2.0
-
-
2.0
-
-
8.0
-
-
8.0
-
8.0
ns
20
Clock rise and fall times
-
50
tON
Turn on time
-
5.0
tOFF
Turn off time
-
VDD = 3.0V
ns
VDD = 3.0 or 5.0V
VDD = 3.0V
-
20
-
20
-
50
-
50
ns
---
-
-
5.0
-
5.0
μs
VSIG = VPP -10V, RLOAD = 10kΩ
5.0
-
-
5.0
-
5.0
μs
VSIG = VPP -10V, RLOAD = 10kΩ
-
20
-
-
20
-
20
-
20
-
-
20
-
20
-
20
-
-
20
-
20
-30
-
-30
-33
-
-30
-
-58
-
-58
-
-
-58
-
-60
-
-60
-70
-
-60
-
dB
f = 5.0MHz, 50Ω load
Output switch isolation diode
current
-
300
-
-
300
-
300
mA
300ns pulse width,
2.0% duty cycle
CSG(OFF) Off capacitance SW to GND
-
-
-
6.5
-
-
-
pF
0V, f = 1.0MHz
On capacitance SW to GND
-
-
-
21.7
-
-
-
pF
0V, f = 1.0MHz
+VSPK
-
-
-
18
-
-
-
-VSPK
-
-
-
60
-
-
-
-
-
-
30
-
-
-
-
-
-
60
-
-
-
+VSPK
-
-
-
33
-
-
-
-VSPK
-
-
-
60
-
-
-
-
-
-
270
-
-
-
-
-
-
220
-
-
-
-
-
-
152
-
-
-
dv/dt
Maximum VSIG slew rate
KO
Off isolation
KCR
Switch crosstalk
IID
CSG(ON)
+VSPK
-VSPK
QC
Output voltage spike
Charge injection
-
---
VDD = 5.0V
MHz
-
VDD = 3.0V
VDD = 5.0V
ns
7.0
VDD = 3.0V
VDD = 5.0V
ns
15
---
4
VDD = 5.0V
VPP = +40V, VNN = -120V
V/ns
VPP = +80V, VNN = -80V
VPP = +120V, VNN = -40V
dB
f = 5.0MHz, 1.0kΩ/15pF load
f = 5.0MHz, 50Ω load
VPP = +40V, VNN = -120V,
RLOAD = 50Ω
mV
VPP = +80V, VNN = -80V,
RLOAD = 50Ω
VPP = +120V, VNN = -40V,
RLOAD = 50Ω
VPP = +40V, VNN = -120V,
VSIG = 0V
pC
VPP = +80V, VNN = -80V,
VSIG = 0V
VPP = +120V, VNN = -40V,
VSIG = 0V
HV2203
Truth Table
D0
D1
D2
D3
D4
D5
D6
D7
LE
CLR
SW0
SW1
SW2
SW3
SW4
SW5
L
L
L
Off
H
L
L
On
L
L
L
Off
H
L
L
On
L
L
L
Off
H
L
L
On
L
L
L
Off
H
L
L
On
L
L
L
Off
H
L
L
On
L
L
L
Off
H
L
L
On
L
L
L
Off
H
L
L
On
L
L
L
Off
H
L
L
On
X
X
X
X
X
X
X
X
H
L
Hold Previous State
X
X
X
X
X
X
X
X
X
H
All Switches Off
SW6
SW7
Notes:
1. The eight switches operate independently.
2. Serial data is clocked in on the L to H transition of the CLK.
3. The switches go to a state retaining their present condition at the rising edge of LE. When LE is low the shift register data flow through the latch.
4. DOUT is high when data in the shift register 7 is high.
5. Shift register clocking has no effect on the switch states if LE is high.
6. The CLR clear input overrides all other inputs.
5
HV2203
Test Circuits
VPP-10V
VPP -10V
L
PP
VPP
VDD
PP
VDD
PP
PP
VPP
VPP
VPP
VDD
VDD
PP
VPP
VNN
VNN
VNN
PP
VPP
VDD
VNN
VNN
VNN
PP
VPP
VDD
PP
VNN
VPP
VNN
6
VDD
VDD
HV2203
Pin Configuration - 48-Lead LQFP (FG) Pin Configuration - 28-Lead PLCC (PJ)
Pin #
Pin Name
Pin #
Pin Name
Pin #
Pin Name
Pin #
Pin Name
1
SW5
25
VNN
1
SW3
15
NC
2
NC
26
NC
2
SW3
16
DIN
3
SW4
27
NC
3
SW2
17
CLK
4
NC
28
GND
4
SW2
18
LE
5
SW4
29
VDD
5
SW1
19
CLR
6
NC
30
NC
6
SW1
20
DOUT
7
NC
31
NC
7
SW0
21
SW7
8
SW3
32
NC
8
SW0
22
SW7
9
NC
33
DIN
9
NC
23
SW6
10
SW3
34
CLK
10
VPP
24
SW6
11
NC
35
LE
11
NC
25
SW5
12
SW2
36
CLR
12
VNN
26
SW5
13
NC
37
DOUT
13
GND
27
SW4
14
SW2
38
NC
14
VDD
28
SW4
15
NC
39
SW7
16
SW1
40
NC
17
NC
41
SW7
18
SW1
42
NC
19
NC
43
SW6
20
SW0
44
NC
21
NC
45
SW6
22
SW0
46
NC
23
NC
47
SW5
24
VPP
48
NC
Typical Waveforms
DN
D N+1
DATA
IN
5 0%
LE
50%
DN - 1
50%
50%
t WLE
t SD
50%
CLOCK
t SU
50%
th
t DO
DATA
O UT
50%
t OFF
VOUT OFF
(TYP )
90%
1 0%
ON
CLR
t ON
5 0%
5 0%
t WCL
7
HV2203
48-Lead LQFP Package Outline (FG)
7x7mm body, 1.4mm height (min), 0.50mm pitch
D
D1
E
E1
Note 1
(Index Area
D1/4 x E1/4)
Gauge
Plane
L2
48
L
1
Seating
Plane
θ
L1
b
e
Top View
View B
View B
A
A2
Seating
Plane
A1
Side View
Note 1:
A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol
MIN
Dimension
(mm)
A
A1
A2
b
D
D1
E
E1
1.40
0.05
1.35
0.17
8.80
6.80
8.80
6.80
NOM
-
-
1.40
0.22
9.00
7.00
9.00
7.00
MAX
1.60
0.15
1.45
0.27
9.20
7.20
9.20
7.20
JEDEC Registration MS-026, Variation BBC, Issue D, Jan. 2001.
Drawings not to scale.
8
e
L
L1
L2
1.00
REF
0.25
BSC
0O
0.45
0.50
BSC
0.60
0.75
θ
3.5O
7O
HV2203
28-Lead PLCC Package Outline (PJ)
.453x.453in body, .180in height (max.), .050in pitch
.048/.042
x 45O
D
D1
1
4
.056/.042
x 45O
28
.150 MAX
26
Note 1
(Index Area)
.075 MAX
E1
E
.020 MAX
3 Places
Top View
View B
b1
A
Base
Plane
A1 A2
.020 MIN
Seating
Plane
e
b
Side View
View B
Note 1:
A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol
Dimension
(inches)
A
A1
A2
b
b1
D
D1
E
E1
MIN
.165
.090
.062
.013
.026
.485
.450
.485
.450
NOM
.172
.105
-
-
-
.490
.453
.490
.453
MAX
.180
.120
.083
.021
.032
.495
.456
.495
.456
e
.050
BSC
JEDEC Registration MS-018, Variation AB, Issue A, June, 1993.
Drawings not to scale.
(The package drawing (s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV2203
NR112607
9
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