Low Voltage 1.15 V to 5.5 V, Single-Channel Bidirectional Logic Level Translator ADG3301 Bidirectional level translation Operates from 1.15 V to 5.5 V Low quiescent current < 5 µA No direction pin APPLICATIONS FUNCTIONAL BLOCK DIAGRAM VCCA VCCY A Y EN SPI®, MICROWIRE® level translation Low voltage ASIC level translation Smart card readers Cell phones and cell phone cradles Portable communication devices Telecommunications equipment Network switches and routers Storage systems (SAN/NAS) Computing/server applications GPS Portable POS systems Low cost serial interfaces ADG3301 GND 05517-001 FEATURES Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The ADG3301 is a single-channel, bidirectional logic level translator. It can be used in multivoltage digital system applications such as data transfer between a low voltage DSP/controller and a higher voltage device. The internal architecture allows the device to perform bidirectional logic level translation without an additional signal to set the direction in which the translation takes place. 1. Bidirectional level translation. 2. Fully guaranteed over the 1.15 V to 5.5 V supply range. 3. No direction pin. 4. Compact 6-lead SC70 package. The voltage applied to VCCA sets the logic levels on the A side of the device, while VCCY sets the levels on the Y side. For proper operation, VCCA must always be less than VCCY. The VCCAcompatible logic signals applied to the A pin appear as VCCYcompatible levels on the Y pin. Similarly, VCCY-compatible logic levels applied to the Y pin appear as VCCA-compatible logic levels on the A pin. The enable pin (EN) provides three-state operation on both the A pin and the Y pin. When the device enable pin is pulled low, the terminals on both sides of the device are in the high impedance state. The EN pin is referred to the VCCA supply voltage and driven high for normal operation. The ADG3301 is available in a compact 6-lead SC70 package and is guaranteed to operate over the 1.15 V to 5.5 V supply voltage range and extended −40°C to +85°C temperature range. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. ADG3301 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 16 Applications....................................................................................... 1 Level Translator Architecture ................................................... 16 Functional Block Diagram .............................................................. 1 Input Driving Requirements..................................................... 16 General Description ......................................................................... 1 Output Load Requirements ...................................................... 16 Product Highlights ........................................................................... 1 Enable Operation ....................................................................... 16 Specifications..................................................................................... 3 Power Supplies............................................................................ 16 Absolute Maximum Ratings............................................................ 6 Data Rate ..................................................................................... 17 ESD Caution.................................................................................. 6 Applications..................................................................................... 18 Pin Configuration and Function Descriptions............................. 7 Layout Guidelines....................................................................... 18 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 19 Test Circuits..................................................................................... 12 Ordering Guide .......................................................................... 19 Terminology .................................................................................... 15 REVISION HISTORY 12/05—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADG3301 SPECIFICATIONS VCCY = 1.65 V to 5.5 V, VCCA = 1.15 V to VCCY, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted. Table 1. Parameter1 LOGIC INPUTS/OUTPUTS A Side Input High Voltage3 Input Low Voltage3 Output High Voltage Output Low Voltage Capacitance3 Leakage Current Y Side Input High Voltage3 Input Low Voltage3 Output High Voltage Output Low Voltage Capacitance3 Leakage Current Enable (EN) Input High Voltage3 Input Low Voltage3 Leakage Current Capacitance3 Enable Time3 Symbol Conditions Min VIHA VIHA VILA VOHA VOLA CA ILA, HiZ VCCA = 1.15 V VCCA = 1.2 V to 5.5 V VCCA − 0.3 0.65 × VCCA VY = VCCY, IOH = 20 µA, see Figure 27 VY = 0 V, IOL = 20 µA, see Figure 27 f = 1 MHz, EN = 0, see Figure 32 VA = 0 V/VCCA, EN = 0, see Figure 29 VCCA − 0.4 VIHY VILY VOHY VOLY CY ILY, HiZ VIHEN VIHEN VILEN ILEN CEN tEN SWITCHING CHARACTERISTICS3 3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V A→Y Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Part-to-Part Skew Y→A Level Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Part-to-Part Skew 1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Part-to-Part Skew Typ2 Max V 0.35 × VCCA 0.4 9 ±1 0.65 × VCCY 0.35 × VCCY VA = VCCA, IOH = 20 µA, see Figure 28 VA = 0 V, IOL = 20 µA, see Figure 28 f = 1 MHz, EN = 0, see Figure 33 VY = 0 V/VCCY, EN = 0, see Figure 30 VCCY − 0.4 VCCA = 1.15 V VCCA = 1.2 V to 5.5 V VCCA − 0.3 0.65 × VCCA 0.4 6 ±1 0.35 × VCCA ±1 VEN = 0 V/VCCA, VA = 0 V, see Figure 31 RS = RT = 50 Ω, VA = 0 V/VCCA (A→Y), VY = 0 V/VCCY (Y→A), see Figure 34 Unit 3 1 1.8 6 2 2 10 3.5 3.5 V V V pF µA V V V V pF µA V V V µA pF µs RS = RT = 50 Ω, CL = 50 pF, see Figure 35 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tPPSKEW, A→Y 3 ns ns ns Mbps ns 4 1 7 3 ns ns 3 7 ns Mbps ns 50 RS = RT = 50 Ω, CL = 15 pF, see Figure 36 tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tPPSKEW, Y→A 50 2 RS = RT = 50 Ω, CL = 50 pF, see Figure 35 8 2 2 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tPPSKEW, A→Y 11 5 5 50 4 Rev. 0 | Page 3 of 20 ns ns ns Mbps ns ADG3301 Parameter1 Y→A Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Part-to-Part Skew 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Part-to-Part Skew Y→A Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Part-to-Part Skew 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V ± 0.3 V A→Y Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Part-to-Part Skew Y→A Translation Propagation Delay Rise Time Fall Time Maximum Data Rate Part-to-Part Skew 2.5 V ± 0.2 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V A→Y Translation Symbol Conditions RS = RT = 50 Ω, CL = 15 pF, see Figure 36 tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tPPSKEW, Y→A Min Typ2 Max Unit 5 2 2 8 3.5 3.5 ns ns ns Mbps ns 50 3 RS = RT = 50 Ω, CL = 50 pF, see Figure 35 9 3 2 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tPPSKEW, A→Y 18 5 5 40 10 ns ns ns Mbps ns RS = RT = 50 Ω, CL = 15 pF, see Figure 36 5 2 2 tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tPPSKEW, Y→A 9 4 4 40 4 ns ns ns Mbps ns RS = RT = 50 Ω, CL = 50 pF, see Figure 35 12 7 3 tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tPPSKEW, A→Y 25 12 5 25 15 ns ns ns Mbps ns RS = RT = 50 Ω, CL = 15 pF, see Figure 36 14 5 2.5 tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tPPSKEW, Y→A 35 16 6.5 25 23.5 ns ns ns Mbps ns RS = RT = 50 Ω, CL = 50 pF, see Figure 35 Propagation Delay Rise Time Fall Time Maximum Data Rate Part-to-Part Skew Y→A Translation tP, A→Y tR, A→Y tF, A→Y DMAX, A→Y tPPSKEW, A→Y Propagation Delay Rise Time Fall Time Maximum Data Rate Part-to-Part Skew tP, Y→A tR, Y→A tF, Y→A DMAX, Y→A tPPSKEW, Y→A 7 2.5 2 10 4 5 60 4 ns ns ns Mbps ns RS = RT = 50 Ω, CL = 15 pF, see Figure 36 5 1 3 8 4 5 60 3 Rev. 0 | Page 4 of 20 ns ns ns Mbps ns ADG3301 Parameter1 POWER REQUIREMENTS Power Supply Voltages Quiescent Power Supply Current Symbol Conditions Min VCCA VCCY ICCA VCCA ≤ VCCY 1.15 1.65 ICCY Three-State Mode Power Supply Current 1 2 3 IHiZA IHiZY VA = 0 V/VCCA, VY = 0 V/VCCY, VCCA = VCCY = 5.5 V, EN = 1 VA = 0 V/VCCA, VY = 0 V/VCCY, VCCA = VCCY = 5.5 V, EN = 1 VCCA = VCCY = 5.5 V, EN = 0 VCCA = VCCY = 5.5 V, EN = 0 Temperature range for the B version is −40°C to +85°C. All typical values are at TA = 25°C, unless otherwise noted. Guaranteed by design, not subject to production test. Rev. 0 | Page 5 of 20 Typ2 Max Unit 0.17 5.5 5.5 5 V V µA 0.27 5 µA 0.1 0.1 5 5 µA µA ADG3301 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 2. Parameter VCCA to GND VCCY to GND Digital Inputs (A) Digital Inputs (Y) EN to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature θJA Thermal Impedance (4-Layer Board) 6-Lead SC70 Lead Temperature, Soldering (10 sec) IR Reflow, Peak Temperature (< 20 sec) Rating −0.3 V to +7 V VCCA to +7 V −0.3 V to VCCA + 0.3 V −0.3 V to VCCY + 0.3 V −0.3 V to +7 V −40°C to +85°C −65°C to +150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time. 494.1°C/W 300°C 260(+0/−5)°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 20 ADG3301 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VCCA 1 6 VCCY A 2 GND 3 5 Y TOP VIEW (Not to Scale) 4 EN 05517-002 ADG3301 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic VCCA A GND EN Y VCCY Description Power Supply Voltage Input for the A I/O Pin (1.15 V ≤ VCCA ≤ VCCY). Input/Output A. Referenced to VCCA. Ground (0 V). Active High Enable Input. Input/Output Y. Referenced to VCCY. Power Supply Voltage Input for the Y I/O Pin (1.65 V ≤ VCCY ≤ 5.5V). Rev. 0 | Page 7 of 20 ADG3301 TYPICAL PERFORMANCE CHARACTERISTICS 3.0 1.0 TA = 25°C 1 CHANNEL CL = 50pF 0.9 2.5 0.8 VCCA = 3.3V, VCCY = 5V 0.7 2.0 0.6 ICCY (mA) ICCA (mA) TA = 25°C 1 CHANNEL CL = 15pF 0.5 0.4 VCCA = 1.8V, VCCY = 3.3V VCCA = 3.3V, VCCY = 5V 1.5 1.0 0.3 VCCA = 1.8V, VCCY = 3.3V 0.2 0.5 0.1 VCCA = 1.2V, VCCY = 1.8V 5 10 15 20 25 30 35 DATA RATE (Mbps) 40 45 50 VCCA = 1.2V, VCCY = 1.8V 0 0 5 10 15 20 25 30 35 40 45 50 DATA RATE (Mbps) 05517-006 0 05517-003 0 Figure 6. ICCY vs. Data Rate (Y→A Level Translation) Figure 3. ICCA vs. Data Rate (A→Y Level Translation) 1.6 10 TA = 25°C 1 CHANNEL CL = 50pF 9 TA = 25°C 1 CHANNEL VCCA = 1.2V VCCY = 1.8V 1.4 8 20Mbps 1.2 7 ICCY (mA) ICCY (mA) VCCA = 3.3V, VCCY = 5V 6 5 4 1.0 0.8 10Mbps 0.6 VCCA = 1.8V, VCCY = 3.3V 3 0.4 5Mbps 2 VCCA = 1.2V, VCCY = 1.8V 1 0 5 10 15 20 25 30 35 DATA RATE (Mbps) 40 45 50 0 13 23 43 53 63 73 CAPACITIVE LOAD (pF) Figure 4. ICCY vs. Data Rate (A→Y Level Translation) Figure 7. ICCY vs. Capacitive Load at Pin Y for A→Y (1.2 V→1.8 V) Level Translation 3.0 1.0 TA = 25°C 1 CHANNEL CL = 15pF 2.5 TA = 25°C 1 CHANNEL VCCA = 1.2V VCCY =1.8V 0.9 0.8 VCCA = 3.3V, VCCY = 5V 0.7 ICCA (mA) 2.0 1.5 0.6 20Mbps 0.5 0.4 1.0 0.3 VCCA = 1.8V, VCCY = 3.3V VCCA = 1.2V, VCCY = 1.8V 0 5 10 15 20 25 30 35 40 0.1 45 DATA RATE (Mbps) 50 1Mbps 0 13 Figure 5. ICCA vs. Data Rate (Y→A Level Translation) 23 33 43 CAPACITIVE LOAD (pF) Figure 8. ICCA vs. Capacitive Load at Pin A for Y→A (1.8 V→1.2 V) Level Translation Rev. 0 | Page 8 of 20 53 05517-008 0 10Mbps 5Mbps 0.2 0.5 05517-005 ICCA (mA) 33 05517-007 1Mbps 05517-004 0 0.2 ADG3301 9 7 TA = 25°C 1 CHANNEL VCCA = 1.8V VCCY = 3.3V 8 7 TA = 25°C 1 CHANNEL VCCA = 3.3V VCCY = 5V 6 50Mbps 50Mbps 5 ICCA (mA) ICCY (mA) 6 5 30Mbps 4 4 30Mbps 3 20Mbps 3 20Mbps 2 2 10Mbps 10Mbps 1 1 33 43 53 CAPACITIVE LOAD (pF) 63 0 05517-009 23 73 13 4.5 4.0 43 53 Figure 12. ICCA vs. Capacitive Load at Pin A for Y→A (5 V→3.3 V) Level Translation 10 TA = 25°C 9 1 CHANNEL DATA RATE = 50kbps 8 TA = 25°C 1 CHANNEL VCCA = 1.8V VCCY = 3.3V 3.5 VCCA = 1.2V, VCCY = 1.8V 7 RISE TIME (ns) ICCA (mA) 33 CAPACITIVE LOAD (pF) Figure 9. ICCY vs. Capacitive Load at Pin Y for A→Y (1.8 V→3.3 V) Level Translation 5.0 23 05517-012 5Mbps 5Mbps 0 13 50Mbps 3.0 2.5 2.0 30Mbps 1.5 6 5 4 VCCA = 1.8V, VCCY = 3.3V 3 20Mbps 1.0 2 VCCA = 3.3V, VCCY = 5V 10Mbps 0.5 5Mbps 23 33 43 CAPACITIVE LOAD (pF) 53 0 13 05517-010 0 13 23 33 43 53 CAPACITIVE LOAD (pF) 63 73 05517-013 1 Figure 13. Rise Time vs. Capacitive Load at Pin Y (A→Y Level Translation) Figure 10. ICCA vs. Capacitive Load at Pin A for Y→A (3.3 V→1.8 V) Level Translation 4.0 12 TA = 25°C 1 CHANNEL VCCA = 3.3V 10 V CCY = 5V 50Mbps 3.5 TA = 25°C 1 CHANNEL DATA RATE = 50kbps VCCA = 1.2V, VCCY = 1.8V 3.0 FALL TIME (ns) 30Mbps 6 20Mbps 4 2.5 VCCA = 1.8V, VCCY = 3.3V 2.0 1.5 VCCA = 3.3V, VCCY = 5V 1.0 10Mbps 2 0.5 0 13 23 33 43 53 63 CAPACITIVE LOAD (pF) 73 0 13 23 33 43 53 CAPACITIVE LOAD (pF) 63 Figure 14. Fall Time vs. Capacitive Load at Pin Y (A→Y Level Translation) Figure 11. ICCY vs. Capacitive Load at Pin Y for A→Y (3.3 V→5 V) Level Translation Rev. 0 | Page 9 of 20 73 05517-014 5Mbps 05517-011 ICCY (mA) 8 ADG3301 12 10 TA = 25°C 9 1 CHANNEL DATA RATE = 50kbps 8 VCCA = 1.2V, VCCY = 1.8V 6 5 4 VCCA = 1.8V, VCCY = 3.3V 3 2 6 VCCA = 1.8V, VCCY = 3.3V 4 VCCA = 3.3V, VCCY = 5V 23 28 33 38 43 48 0 13 05517-015 18 53 CAPACITIVE LOAD (pF) 23 33 43 53 63 73 CAPACITIVE LOAD (pF) Figure 15. Rise Time vs. Capacitive Load at Pin A (Y→A Level Translation) 05517-018 VCCA = 3.3V, VCCY = 5V 0 13 Figure 18. Propagation Delay (tPHL) vs. Capacitive Load at Pin Y (A→Y Level Translation) 9 4.0 TA = 25°C 1 CHANNEL DATA RATE = 50kbps 8 2.5 VCCA = 1.2V, VCCY = 1.8V 2.0 VCCA = 1.8V, VCCY = 3.3V 1.5 VCCA = 3.3V, VCCY = 5V 1.0 VCCA = 1.2V, VCCY = 1.8V 6 5 4 3 VCCA = 1.8V, VCCY = 3.3V 2 0.5 VCCA = 3.3V, VCCY = 5V 1 18 23 28 33 38 43 CAPACITIVE LOAD (pF) 48 53 0 13 23 28 33 38 43 48 53 CAPACITIVE LOAD (pF) Figure 19. Propagation Delay (tPLH) vs. Capacitive Load at Pin A (Y→A Level Translation) Figure 16. Fall Time vs. Capacitive Load at Pin A (Y→A Level Translation) 9 14 TA = 25°C 1 CHANNEL 8 DATA RATE = 50kbps TA = 25°C 1 CHANNEL 12 DATA RATE = 50kbps PROPAGATION DELAY (ns) VCCA = 1.2V, VCCY = 1.8V 10 8 6 VCCA = 1.8V, VCCY = 3.3V 4 VCCA = 3.3V, VCCY = 5V 2 VCCA = 1.2V, VCCY = 1.8V 7 6 5 4 VCCA = 1.8V, VCCY = 3.3V 3 VCCA = 3.3V, VCCY = 5V 2 1 23 33 43 53 CAPACITIVE LOAD (pF) 63 73 0 05517-017 0 13 18 13 18 23 28 33 38 43 CAPACITIVE LOAD (pF) 48 53 05517-020 13 05517-016 0 05517-019 3.0 TA = 25°C 1 CHANNEL DATA RATE = 50kbps 7 PROPAGATION DELAY (ns) 3.5 FALL TIME (ns) 8 2 1 PROPAGATION DELAY (ns) VCCA = 1.2V, VCCY = 1.8V 10 PROPAGATION DELAY (ns) RISE TIME (ns) 7 DATA RATE = 50kbps TA = 25°C 1 CHANNEL Figure 20. Propagation Delay (tPHL) vs. Capacitive Load at Pin A (Y→A Level Translation) Figure 17. Propagation Delay (tPLH) vs. Capacitive Load at Pin Y (A→Y Level Translation) Rev. 0 | Page 10 of 20 ADG3301 TA = 25°C DATA RATE = 25Mbps CL = 50pF 1 CHANNEL 400mV/DIV Figure 24. Eye Diagram at A Output (3.3 V to 1.8 V Level Translation, 50 Mbps) Figure 21. Eye Diagram at Y Output (1.2 V to 1.8 V Level Translation, 25 Mbps) 5ns/DIV TA = 25°C DATA RATE = 50Mbps CL = 50pF 1 CHANNEL 1V/DIV Figure 22. Eye Diagram at A Output (1.8 V to 1.2 V Level Translation, 25 Mbps) 500mV/DIV Figure 25. Eye Diagram at Y Output (3.3 V to 5 V Level Translation, 50 Mbps) TA = 25°C DATA RATE = 50Mbps CL = 15pF 1 CHANNEL CL = 50pF 1 CHANNEL 3ns/DIV 05517-023 TA = 25°C DATA RATE = 50Mbps 3ns/DIV 05517-025 200mV/DIV CL = 15pF 1 CHANNEL 05517-022 TA = 25°C DATA RATE = 25Mbps 3ns/DIV 800mV/DIV Figure 23. Eye Diagram at Y Output (1.8 V to 3.3 V Level Translation, 50 Mbps) 3ns/DIV Figure 26. Eye Diagram at A Output (5 V to 3.3 V Level Translation, 50 Mbps) Rev. 0 | Page 11 of 20 05517-026 5ns/DIV 05517-024 05517-021 400mV/DIV TA = 25°C DATA RATE = 50Mbps CL = 15pF 1 CHANNEL ADG3301 TEST CIRCUITS EN VCCA ADG3301 VCCY 0.1µF 0.1µF EN ADG3301 VCCA A VCCY Y 0.1µF 0.1µF K2 K1 A GND IOH K Y A IOL Figure 30. Three-State Leakage Current at Pin Y Figure 27. VOH/VOL Voltages at Pin A EN ADG3301 VCCA VCCY 0.1µF 0.1µF VCCA K2 ADG3301 VCCY 0.1µF Y A 05517-030 05517-027 GND 0.1µF K1 Y A GND GND 05517-028 K Figure 28. VOH/VOL Voltages at Pin Y EN VCCA ADG3301 EN A IOL 05517-031 IOH Figure 31. EN Pin Leakage Current EN VCCA VCCY ADG3301 VCCY 0.1µF 0.1µF A A Y A Y K CAPACITANCE METER GND 05517-032 05517-029 GND Figure 29. Three-State Leakage Current at Pin A ADG3301 A VCCY Y GND Figure 33. Capacitance at Pin Y Rev. 0 | Page 12 of 20 CAPACITANCE METER 05517-033 EN VCCA Figure 32. Capacitance at Pin A ADG3301 A→Y DIRECTION VCCA 0.1µF VCCY ADG3301 + 10µF + 10µF 0.1µF 1MΩ A VA K1 Y VY K2 50pF 1MΩ SIGNAL SOURCE EN RS 50Ω Z0 = 50Ω GND VEN RT 50Ω Y→A DIRECTION VCCA 0.1µF VCCY ADG3301 + 10µF + 10µF 0.1µF 1MΩ K1 A VA Y VY K2 15pF 1MΩ SIGNAL SOURCE EN RS 50Ω Z0 = 50Ω GND VEN RT 50Ω VEN tEN1 VCCA 0V VCCA/VCCY VA/VY 0V VCCY/VCCA 90% VY/VA tEN2 VCCA 0V VA/VY VCCA/VCCY 0V VCCY/VCCA VY/VA 10% 0V NOTE: tEN IS THE LARGEST OF tEN1 AND tEN2 IN BOTH A→Y AND Y→A DIRECTIONS. Figure 34. Enable Time Rev. 0 | Page 13 of 20 05517-034 VEN 0V ADG3301 EN VCCY ADG3301 VCCA SIGNAL SOURCE 0.1µF RS 50Ω Z0 = 50Ω VA EN + 10µF 0.1µF + 10µF Y RT 50Ω VY VA 50pF VCCY + 10µF 0.1µF + 10µF 0.1µF A ADG3301 VCCA SIGNAL SOURCE A Y RS Z0 = 50Ω 50Ω RT 50Ω 15pF GND VY GND VA VY 50% 50% tP, A→Y VA 90% 50% 10% tF, A→Y tR, A→Y tP, Y→A tP, Y→A 90% 50% 10% Figure 35. Switching Characteristics (A→Y Level Translation) tF, Y→A tR, Y→A Figure 36. Switching Characteristics (Y→A Level Translation) Rev. 0 | Page 14 of 20 05517-036 tP, A→Y 05517-035 VY ADG3301 TERMINOLOGY VIHA Logic input high voltage at Pin A. tR, A→Y Rise time when translating logic levels in the A→Y direction. VILA Logic input low voltage at Pin A. tF, A→Y Fall time when translating logic levels in the A→Y direction. VOHA Logic output high voltage at Pin A. DMAX, A→Y Guaranteed data rate when translating logic levels in the A→Y direction under the driving and loading conditions specified in Table 1. VOLA Logic output low voltage at Pin A. tPPSKEW, A→Y Difference in propagation delay between any one channel and the same channel on a different part (under same driving/loading conditions) when translating in the A→Y direction. CA Capacitance measured at Pin A (EN = 0). ILA, HiZ Leakage current at Pin A when EN = 0 (Pin A three-stated). tP, Y→A Propagation delay when translating logic levels in the Y→A direction. VIHY Logic input high voltage at Pin Y. VILY Logic input low voltage at Pin Y. tR, Y→A Rise time when translating logic levels in the Y→A direction. VOHY Logic output high voltage at Pin Y. tF, Y→A Fall time when translating logic levels in the Y→ A direction. VOLY Logic output low voltage at Pin Y. DMAX, Y→A Guaranteed data rate when translating logic levels in the Y→A direction under the driving and loading conditions specified in Table 1. CY Capacitance measured at Pin Y (EN = 0). ILY, HiZ Leakage current at pin and when EN = 0 (Pin A three-stated). VIHEN Logic input high voltage at the EN pin. VILEN Logic input low voltage at the EN pin. CEN Capacitance measured at EN pin. ILEN Enable (EN) pin leakage current. tEN Three-state enable time for Pin A and Pin Y. tPPSKEW, Y→A Difference in propagation delay between any one channel and the same channel on a different part (under the same driving/ loading conditions) when translating in the Y→A direction. ICCA VCCA supply current. ICCY VCCY supply current. IHiZA VCCA supply current during three-state mode (EN = 0). IHiZY VCCY supply current during three-state mode (EN = 0). tP, A→Y Propagation delay when translating logic levels in the A→Y direction. Rev. 0 | Page 15 of 20 ADG3301 THEORY OF OPERATION The ADG3301 level translator allows the level shifting necessary for data transfer in a system where multiple supply voltages are used. The device requires two supplies, VCCA and VCCY (VCCA ≤ VCCY). These supplies set the logic levels on each side of the device. When driving the A pin, the device translates the VCCA-compatible logic levels to VCCY-compatible logic levels available at the Y pin. Similarly, because the device is capable of bidirectional translation, when driving the Y pin the VCCY-compatible logic levels are translated to VCCA-compatible logic levels available at the A pin. When EN = 0, the A pin and the Y pin are three-stated. When EN is driven high, the ADG3301 goes into normal operation mode and performs level translation. To ensure correct operation of the ADG3301, the circuit that drives the input of an ADG3301 channel must have an output impedance of less than or equal to 150 Ω and a minimum peak current driving capability of 36 mA. OUTPUT LOAD REQUIREMENTS The ADG3301 level translator is designed to drive CMOScompatible loads. If current driving capability is required, it is recommended to use buffers between the ADG3301 outputs and the load. ENABLE OPERATION LEVEL TRANSLATOR ARCHITECTURE The ADG3301 consists of a single bidirectional channel that can translate logic levels in either the A→Y or the Y→A direction. It uses a one-shot accelerator architecture that ensures excellent switching characteristics. Figure 37 shows a simplified block diagram of the ADG3301 level translator. VCCA INPUT DRIVING REQUIREMENTS VCCY The ADG3301 provides three-state operation at the A I/O pin and Y I/O pin by using the enable (EN) pin as shown in Table 4. Table 4. Truth Table EN 0 1 1 2 T1 T2 P A U2 ONE-SHOT GENERATOR Y N A I/O Pin Hi-Z1 Normal operation2 High impedance state. In normal operation, the ADG3301 performs level translation. While EN = 0, the ADG3301 enters into tri-state mode. In this mode, the current consumption from both the VCCA and VCCY supplies is reduced, allowing the user to save power, which is critical especially on battery-operated systems. The EN input pin can be driven with either VCCA- or VCCY-compatible logic levels. 6kΩ U1 Y I/O Pin Hi-Z1 Normal operation2 POWER SUPPLIES T4 U3 T3 05517-037 6kΩ U4 Figure 37. Simplified Block Diagram of an ADG3301 Channel The logic level translation in the A→Y direction is performed using a level translator (U1) and an inverter (U2), while the translation in the Y→A direction is performed using the inverters U3 and U4. The one-shot generator detects a rising or falling edge present on either the A side or the Y side of the channel. It sends a short pulse that turns on the PMOS transistors (T1 and T2) for a rising edge, or the NMOS transistors (T3 and T4) for a falling edge. This charges/discharges the capacitive load faster, which results in fast rise and fall times. For proper operation of the ADG3301, the voltage applied to the VCCA must be always less than or equal to the voltage applied to VCCY. To meet this condition, the recommended power-up sequence is VCCY first and then VCCA. The ADG3301 operates properly only after both supply voltages reach their nominal values. It is not recommended to use the part in a system where, during power-up, VCCA may be greater than VCCY due to a significant increase in the current taken from the VCCA supply For optimum performance, the VCCA and VCCY pins should be decoupled to GND, and placed as close as possible to the device. Rev. 0 | Page 16 of 20 ADG3301 DATA RATE The maximum data rate at which the device is guaranteed to operate is a function of the VCCA and VCCY supply voltage combination and the load capacitance. It represents the maximum frequency of a square wave that can be applied to the I/O pins, which ensures that the device operates within the datasheet specifications in terms of output voltage (VOL and VOH) and power dissipation (the junction temperature does not exceed the value specified under the Absolute Maximum Ratings section). Table 5 shows the guaranteed data rates at which the ADG3301 can operate in both directions (A→Y or Y→A level translation) for various VCCA and VCCY supply combinations. Table 5. Guaranteed Data Rate (Mbps)1 VCCY VCCA 1.2 V (1.15 V to 1.3 V) 1.8 V (1.65 V to 1.95 V) 2.5 V (2.3 V to 2.7 V) 3.3 V (3.0 V to 3.6 V) 5 V (4.5 V to 5.5 V) 1 1.8 V (1.65 V to 1.95 V) 25 – – – – 2.5 V (2.3 V to 2.7 V) 30 45 – – – 3.3 V (3.0 V to 3.6 V) 40 50 60 – – The load capacitance used is 50 pF when translating in the A→Y direction and 15 pF when translating in the Y→A direction. Rev. 0 | Page 17 of 20 5V (4.5 V to 5.5 V) 40 50 50 50 – ADG3301 APPLICATIONS The ADG3301 is designed for digital circuits that operate at different supply voltages; therefore, logic level translation is required. The lower voltage logic signals are connected to the A pin, and the higher voltage logic signals are connected to the Y pin. The ADG3301 can provide level translation in both directions from A→Y or Y→A, eliminating the need for a level translator IC for each direction. The internal architecture allows the ADG3301 to perform bidirectional level translation without an additional signal to set the direction in which the translation is made. This simplifies the design by eliminating the timing requirements for the direction signal and reduces the number of ICs used for level translation. LAYOUT GUIDELINES As with any high speed digital IC, the printed circuit board layout is important for the overall performance of the circuit. Care should be taken to ensure proper power supply bypass and return paths for the high speed signals. Each VCC pin (VCCA and VCCY) should be bypassed using low effective series resistance (ESR) and effective series inductance (ESI) capacitors placed as close as possible to the VCCA and VCCY pins. The parasitic inductance of the high-speed signal track might cause significant overshoot. This effect can be reduced by keeping the length of the tracks as short as possible. A solid copper plane for the return path (GND) is also recommended. Figure 38 shows an application where a 1.8 V microprocessor transfers data to or from a 3.3 V peripheral device using the ADG3301 level translator. 100nF 1 1.8V VCCA 100nF VCCY 6 3.3V ADG3301 GND 2 A 3 GND Y 5 EN 4 I/OH PERIPHERAL DEVICE GND 05517-038 I/OL MICROPROCESSOR/ MICROCONTROLLER/ DSP Figure 38 1.8 V to 3.3 V Level Translation Circuit Rev. 0 | Page 18 of 20 ADG3301 OUTLINE DIMENSIONS 2.20 2.00 1.80 1.35 1.25 1.15 6 5 4 1 2 3 2.40 2.10 1.80 PIN 1 0.65 BSC 1.30 BSC 1.00 0.90 0.70 0.10 MAX 1.10 0.80 0.30 0.15 SEATING PLANE 0.40 0.10 0.22 0.08 0.30 0.10 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-203-AB Figure 39. 6-Lead Thin Shrink Small Outline Transistor Package [SC70] (KS-6) Dimensions shown in millimeters ORDERING GUIDE Model ADG3301BKSZ-REEL2 ADG3301BKSZ-REEL72 1 2 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 6-Lead Thin Shrink Small Outline Transistor Package 6-Lead Thin Shrink Small Outline Transistor Package Branding on this package is limited to three characters due to space constraints. Z = Pb-free part. Rev. 0 | Page 19 of 20 Branding1 S0H S0H Package Option KS-6 KS-6 ADG3301 NOTES © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05517-0-12/05(0) Rev. 0 | Page 20 of 20