DV2004S1/ES1/HS1 Fast-Charge Development System Control of On-Board P-FET Switch-Mode Regulator Features ä bq2004/E/H fast charge control evaluation and development ä Charge current sourced from an on-board switch-mode regulator (up to 3.0 A) ä Fast charge of 4 to 10 NiCd or NiMH cells and one user-defined selection ä Fast charge termination by delta temperature/delta time (∆T/∆t), negative delta voltage (-∆V) or peak voltage detect, maximum temperature, maximum time, and maximum voltage ä -∆V/peak voltage detect, hold-off, top-off, maximum time, and number of cells are jumper-configurable ä Programmable charge status display ä Discharge-before-charge control with push-button switch or auto discharge-before-charge with jumper ä Inhibit fast charge by logic-level input General Description The DV2004S1/ES1/HS1 Development System provides a development environment for the bq2004/E/H Fast Charge IC. The DV2004S1/ES1/HS1 incorporates a bq2004/E/H and a buck-type switch-mode regulator to provide fast charge control for 4 to 10 NiCd or NiMH cells. Connection Descriptions The fast charge is terminated by any of the following: ∆T/∆t, -∆V or peak voltage detect, maximum temperature, maximum time, maximum voltage, and inhibit command. Jumper settings select the voltage termination mode, the hold-off, top-off, and maximum time limits, and automatic discharge-before-charge. J1 The user provides a power supply and batteries. The user configures the DV2004S1/ES1/HS1 for the number of cells, voltage, charge termination mode, and maximum charge time (with or without top-off), and commands discharge-before-charge with push-button switch S1. THERM Thermistor connection SNS tor Negative battery terminal and thermisconnection Please review the bq2004/E/H data sheet before using the DV2004S1/ES1/HS1 board. SLUU016A - 3/99 revised 8/2002 BAT+ Positive battery terminal and high side of discharge load LOAD Low side of discharge load GND Ground from charger supply DC DC input from charger supply Rev. C Board 1 DV2004S1/ES1/HS1 JP1 INH Inhibit input JP2 DSEL Display select JP3 VSEL Voltage termination select JP4 TM1 TM1 setting JP5 TM2 TM2 setting JP6 NOC Select number of cells JP7 Auto discharge-before-charge select JP8 Auto cycle select Table 1. Lookup Table for D5 Selection +VDC Input (Volts) Motorola Part No. Nominal Zener Voltage Below 15 Shorted 0 15–18 1N749 4.3 18–21 1N755 7.5 21–24 1N758 10 24–27 1N964A 13 27–30 1N966A 16 30–32 1N967A 18 32–35 1N968A 20 Note: Capacitors C2 and C3 must be changed from those shipped with the board for input voltage in excess of 24V. Fixed Configuration The DV2004S1/ES1/HS1 board has the following fixed characteristics: LED1 and LED2 indicate charge status. With the provided NTC thermistor connected between THERM and SNS, values are: LTF = 0°C, HTF = 40°C, and TCO = 60°C. The ∆T/∆t settings at 30°C (T∆T) are: minimum = 0.82°C/minute, typical = 1.10°C/minute. LED3 can replace LED1 and LED2 and provide an optional tri-color LED feature. The thermistor is identified by the serial number suffix as follows: VCC (4.75–5.25V) is regulated on-board from the supply at connector J1 DC. Charge initiates on the later application of the battery or DC, which provides VCC to the bq2004/E/H. Identifier Thermistor Pin DCMD may be tied to ground through JP7 for automatic discharge-before-charge. With JP7 open, a toggle of switch S1 momentarily pulls DCMD low and initiates a discharge-before-charge. The bq2004E output activates FET Q1, allowing current to flow through an external current-limiting load between BAT+ and LOAD on connector J1. K1 Keystone RL0703-5744-103-S1 (blank) Philips 2322-640-63103 F1 Fenwal Type 16, 197-103LA6-A01 O1 Ozhumi 150-108-00(4) S1 Semetic 103AT-2 As shipped from Benchmarq, the DV2004S1/ES1/HS1 buck-type switch-mode regulator is configured to a charging current of 2.25A. This current level is controlled by the value of sense resistor RSNS by the relationship: I CHG = Jumper-Selectable Configuration The DV2004S1/ES1/HS1 must be configured as described below. 0.225V R SNS The value of RSNS at shipment is 0.100Ω. This resistor can be changed depending on the application. Jumper Setting Pin State [12]3 1[23] Disabled (high) Enabled (low) INH (JP1): Enables/disables charge inhibit (see bq2004/E/H data sheet). Th e su g g e s te d m ax i m um ICHG f or the DV2004S1/ES1/HS1 board is 3A. The maximum cell voltage (MCV) setting is 1.8V. Zener diode D5 is used to limit Q4 VGS per a given DC voltage. The board is shipped with D5 shorted. The user can modify this Zener diode for the application. Refer to Table 1 for suggested D5 values for DC voltages. Rev. C Board 2 Jumper Setting Pin State [12]3 1[23] 123 High Low Float DV2004S1/ES1/HS1 AUTO CYCLE SELECT (JP8): Jumping JP8 automatically initiates a continuous discharge-beforecharge/fast-charge cycling for data collection purposes. TM1 and TM2 (JP4 and JP5): Select fast charge safety time/hold-off/top-off (see bq2004/E/H data sheet). Number of Cells (JP6): A resistor-divider network is Closed Jumper Number of Cells RB25 RB24 RB23 RB22 RB21 RB20 User-selectable 10 8 6 5 4 Setup Procedure 1. Configure VSEL, TM1, TM2, DSEL, INH, and number-of-cells (NOC) jumpers. 2. Connect the provided thermistor or a 10KΩ resistor between THERM and SNS. 3. provided to select 4 to 10 cells (the resulting resistor value equals N 2 – 1 cells). RB1 is a 150KΩ resistor, and RB2 (RB20–RB25) is jumper-selected. If using the discharge-before-charge or auto-cycle options, connect a current-limiting discharge load between BAT+ and LOAD. 4. Temperature Disable: Connecting a 10KΩ resistor between THERM and SNS disables temperature control. Attach the battery pack to BAT+ and SNS. For temperature control, the thermistor must contact the cells. 5. Attach DC current source to DC (+) and GND (–) connections in J1. DSEL (JP2): Selects LED1 and LED2 (LED3 optional) display state (see bq2004E data sheet, Table 2, page 5). VSEL (JP3): Selects -∆V or peak-voltage detection, or disables voltage-based termination (see bq2004E data ssheet, page 7). AUTO DIS SELECT (JP7): Jumping JP7 enables automatic discharge-before-charge. Recommended DC Operating Conditions Symbol Description Minimum Typical Maximum Unit IDC Maximum input current - - 2.4 A VDC Maximum input voltage 2.0 + VBAT or 15 - 18 + VBAT or 35 V VBAT BAT input voltage - - 24 V VTHERM THERM input voltage 0 - 5 V IDSCHG Discharge load current - - 2 A Note: Notes Note 1 1. The VDC+ limits consider the appropriate Zener diode at D5. The voltage at D5 is application-specific and limits the VGS of Q4 to a safe enhancement value during Q4 conduction. See Table 1 for recommended D5 selections per VDC+. Rev. C Board 3 DV2004S1/ES1/HS1 DV2004S1 2004s1.eps 3/4/99 Rev. C Board 4 DV2004S1/ES1/HS1 DV2004S1/ES1/HS1 5 6 D4 THERM R13 SNS D8 1N5400 BAT+ LOAD GND DC C2 1N4001 2K Q4 MTP23P06V 1000µF 35V R12 Q3 U2 +5V IN OUT GND C5 C3 100µF 6.3V 100µF 25V 1 2 3 INH JP7 AUTO_DIS. DSEL JP3 VSEL +5V TM1 RT3 JP5 TM2 11.3K 1% RT2 +5V 0.1µF MTP3055VL 4 5 6 8 Q1 RB20 RB21 RB22 RB23 RB24 133K 1% 100K 1% 66.5K 1% 49.9K 1% R9 200K 1% 100K R4 1 2 3 26.1K JP8 1% AUTO_CYCLE 1 2 3 4 5 6 7 8 1 2 3 300K R5 10K 1% C7 0.1µF 12.7K 1% DCMD INH DSEL DIS VSEL MOD TM1 VCC TM2 VSS TCO LED2 TS LED1 BAT SNS 2K R1 1µF bq2004/E/H C8 0.2 1% 1000 pF USER_DEF. 1% Q2 R10 +5V 2N7000 0_OHM R11 100K C4 R6 1K R7 0.1µF 2K 510K R3 RSNS RB25 D9 16 15 14 13 12 11 10 9 U1 C6 10 R8 1N751A R2 C9 3.92K 1N4148 1 2 3 JP4 RT1 S1 DISCHARGE_CMD 1 2 1 2 3 JP2 JP6 NUMBER OF CELLS D6 +5V JP1 C1 1N5821 10µF 35V 2N3904 78L05ACZ RB1 200K 1% D7 6.8K D5 1N4148 L1 100UH 12 10 8 6 4 2 1 2 3 4 11 9 7 5 3 1 J1 1K GRN RED D1 D2 DONE CHARGE D3 GREEN RED BD-9623 1. Use semetec 103AT thermistor. Rev. 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