LINER LTC1596 Serial 16-bit multiplying dac Datasheet

LTC1595/LTC1596/LTC1596-1
Serial 16-Bit
Multiplying DACs
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DESCRIPTION
FEATURES
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SO-8 Package (LTC1595)
DNL and INL: 1LSB Max
Low Glitch Impulse: 1nV-s Typ
Fast Settling to 1LSB: 2µs (with LT1468)
Pin Compatible with Industry Standard
12-Bit DACs: DAC8043 and DAC8143/AD7543
4-Quadrant Multiplication
Low Supply Current: 10µA Max
Power-On Reset
LTC1595/LTC1596: Resets to Zero Scale
LTC1596-1: Resets to Midscale
3-Wire SPI and MICROWIRETM Compatible
Serial Interface
Daisy-Chain Serial Output (LTC1596)
Asynchronous Clear Input
LTC1596: Clears to Zero Scale
LTC1596-1: Clears to Midscale
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APPLICATIONS
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Both are specified over the industrial temperature range.
Sensitivity of INL to op amp VOS is reduced by five times
compared to the industry standard 12-bit DACs, so most
systems can be easily upgraded to true 16-bit resolution
and linearity without requiring more precise op amps.
These DACs include an internal deglitching circuit that
reduces the glitch impulse by more than ten times to less
than 1nV-s typ.
The DACs have a clear input and a power-on reset. The
LTC1595 and LTC1596 reset to zero scale. The LTC1596-1
is a version of the LTC1596 that resets to midscale.
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
Process Control and Industrial Automation
Software Controlled Gain Adjustment
Digitally Controlled Filter and Power Supplies
Automatic Test Equipment
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The LTC®1595/LTC1596/LTC1596-1 are serial input,
16-bit multiplying current output DACs. The LTC1595 is
pin and hardware compatible with the 12-bit DAC8043 and
comes in 8-pin PDIP and SO packages. The LTC1596 is pin
and hardware compatible with the 12-bit DAC8143/AD7543
and comes in 16-pin PDIP and SO wide packages.
TYPICAL APPLICATION
SO-8 Multiplying 16-Bit DAC Has Easy 3-Wire Serial Interface
Integral Nonlinearity
1.0
VIN
5V
DATA
LOAD
7
6
5
8
1
VDD VREF
CLK
SRI
2
RFB
LTC1595
LD
33pF
OUT1
3
–
LT ®1468
GND
4
+
VOUT
1595/96 TA01
INTEGRAL NONLINEARITY (LSB)
CLOCK
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
– 0.8
–1.0
0
49152
16384
32768
DIGITAL INPUT CODE
65535
1595/96 TA02
1
LTC1595/LTC1596/LTC1596-1
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ABSOLUTE MAXIMUM RATINGS
(Note 1)
VDD to AGND .............................................. – 0.5V to 7V
VDD to DGND .............................................. – 0.5V to 7V
AGND to DGND ............................................ VDD + 0.5V
DGND to AGND ............................................. VDD + 0.5V
VREF to AGND, DGND............................................. ± 25V
RFB to AGND, DGND .............................................. ±25V
Digital Inputs to DGND ................ – 0.5V to (VDD + 0.5V)
VOUT1, VOUT2 to AGND ................. – 0.5V to (VDD + 0.5V)
Maximum Junction Temperature .......................... 150°C
Operating Temperature Range
LTC1595C/LTC1596C/LTC1596-1C ........ 0°C to 70°C
LTC1595I/LTC1596I/LTC1596-1I ...... – 40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
TOP VIEW
TOP VIEW
VREF
1
8
VDD
OUT1
1
16 RFB
RFB
2
7
CLK
OUT2
2
15 VREF
OUT1
3
6
SRI
AGND
3
14 VDD
GND
4
5
LD
STB1
4
13 CLR
LD1
5
12 DGND
SRO
6
11 STB4
SRI
7
10 STB3
STB2
8
9
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 150°C, θJA = 130°C/W (N)
TJMAX = 150°C, θJA = 190°C/W (S)
N PACKAGE
16-LEAD PDIP
ORDER PART NUMBER
LTC1595ACN8
LTC1595ACS8
LTC1595BCN8
LTC1595BCS8
LTC1595CCN8
LTC1595CCS8
LTC1595AIN8
LTC1595AIS8
LTC1595BIN8
LTC1595BIS8
LTC1595CIN8
LTC1595CIS8
S8 PART MARKING
1595A
1595B
1595C
1595AI
1595BI
1595CI
LD2
SW PACKAGE
16-LEAD PLASTIC SO WIDE
TJMAX = 150°C, θJA = 100°C/W (N)
TJMAX = 150°C, θJA = 130°C/W (SW)
ORDER PART NUMBER
LTC1596ACN
LTC1596ACSW
LTC1596BCN
LTC1596BCSW
LTC1596CCN
LTC1596CCSW
LTC1596AIN
LTC1596AISW
LTC1596BIN
LTC1596BISW
LTC1596CIN
LTC1596CISW
LTC1596-1ACN
LTC1596-1ACSW
LTC1596-1BCN
LTC1596-1BCSW
LTC1596-1CCN
LTC1596-1CCSW
LTC1596-1AIN
LTC1596-1AISW
LTC1596-1BIN
LTC1596-1BISW
LTC1596-1CIN
LTC1596-1CISW
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
LTC1595A/96A/96-1A
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
LTC1595B/96B/96-1B LTC1595C/96C/96-1C
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
Accuracy
INL
2
Resolution
●
16
16
16
Bits
Monotonicity
●
16
16
15
Bits
Integral Nonlinearity
(Note 2) TA = 25°C
TMIN to TMAX
●
±0.25
±0.35
±1
±1
±2
±2
±4
±4
LSB
LSB
LTC1595/LTC1596/LTC1596-1
ELECTRICAL CHARACTERISTICS
VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
LTC1595A/96A/96-1A
SYMBOL PARAMETER
DNL
GE
CONDITIONS
TYP
MAX
LTC1595B/96B/96-1B LTC1595C/96C/96-1C
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
TA = 25°C
TMIN to TMAX
●
±0.2
±0.2
±1
±1
±1
±1
±2
±2
LSB
LSB
(Note 3) TA = 25°C
TMIN to TMAX
●
2
3
±16
±16
±16
±32
±32
±32
LSB
LSB
Differential
Nonlinearity
Gain Error
MIN
VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL
ILEAKAGE
PARAMETER
CONDITIONS
Gain Temperature Coefficient
(Note 4) ∆Gain/∆Temperature
OUT1 Leakage Current
(Note 5) TA = 25°C
TMIN to TMAX
TA = 25°C
TMIN to TMAX
Zero-Scale Error
PSRR
Power Supply Rejection
MIN
TYP
1
●
MAX
UNITS
2
ppm/°C
●
±3
±15
nA
nA
●
±0.2
±1
LSB
LSB
VDD = 5V ±10%
●
(Note 6)
●
±1
±2
LSB/V
7
10
kΩ
Reference Input
RREF
VREF Input Resistance
5
AC Performance
THD
Output Current Settling Time
(Notes 7, 8)
1
µs
Mid-Scale Glitch Impulse
Using LT1122 Op Amp, CFEEDBACK = 33pF
1
nV-s
Digital-to-Analog Glitch Impulse
Full-Scale Transition, VREF = 0V,
Using LT1122 Op Amp, CFEEDBACK = 33pF
2
nV-s
Multiplying Feedthrough Error
VREF = ±10V, 10kHz Sine Wave
1
mVP-P
Total Harmonic Distortion
(Note 9)
108
dB
Equivalent DAC Thermal Noise
Voltage Density
(Note 10) f = 1kHz
11
nV/√Hz
Analog Outputs (Note 4)
COUT
Output Capacitance (Note 4)
DAC Register Loaded to All 1s
COUT1
●
115
130
pF
DAC Register Loaded to All 0s
COUT1
●
70
80
pF
0.8
V
±1
µA
8
pF
Digital Inputs
VIH
Digital Input High Voltage
●
VIL
Digital Input Low Voltage
●
IIN
Digital Input Current
●
CIN
Digital Input Capacitance
(Note 4) VIN = 0V
●
2.4
V
0.001
Digital Outputs: SRO (LTC1596/LTC1596-1)
VOH
Digital Output High Voltage
IOH = 200µA
●
VOL
Digital Output Low Voltage
IOL = 1.6mA
●
4
V
0.4
V
MAX
UNITS
VDD = 5V ±10%, VREF = 10V, VOUT1 = GND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
Timing Characteristics (LTC1595)
tDS
Serial Input to CLK Setup Time
●
30
5
ns
tDH
Serial Input to CLK Hold Time
●
30
5
ns
3
LTC1595/LTC1596/LTC1596-1
ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tSRI
Serial Input Data Pulse Width
●
60
ns
tCH
Clock Pulse Width High
●
60
ns
tCL
Clock Pulse Width Low
●
60
ns
tLD
Load Pulse Width
●
60
ns
tASB
LSB Clocked into Input Register
to DAC Register Load Time
●
0
ns
VDD = 5V ±10%, VREF = 10V, VOUT1 = VOUT2 = AGND = 0V, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Timing Characteristics (LTC1596/LTC1596-1)
tDS1
Serial Input to Strobe Setup Time
STB1 Used as the Strobe
●
30
5
tDS2
STB2 Used as the Strobe
●
20
–5
ns
tDS3
STB3 Used as the Strobe
●
25
0
ns
STB4 Used as the Strobe
●
20
–5
ns
STB1 Used as the Strobe
●
30
5
ns
tDH2
STB2 Used as the Strobe
●
40
15
ns
tDH3
STB3 Used as the Strobe
●
35
10
ns
tDH4
STB4 Used as the Strobe
●
40
15
ns
●
60
ns
tDS4
tDH1
Serial Input to Strobe Hold Time
ns
tSRI
Serial Input Data Pulse Width
tSTB1 to
tSTB4
Strobe Pulse Width
(Note 11)
●
60
ns
tSTB1 to
tSTB4
Strobe Pulse Width
(Note 12)
●
60
ns
tLD1, tLD2
LD Pulse Width
●
60
ns
tASB
LSB Strobed into Input Register
to Load DAC Register Time
●
0
ns
tCLR
Clear Pulse Width
●
100
tPD1
STB1 to SRO Propagation Delay
CL = 50pF
●
30
150
ns
tPD
STB2, STB3, STB4 to SRO
Propagation Delay
CL = 50pF
●
30
200
ns
●
4.5
5
5.5
V
1.5
10
µA
ns
Power Supply
VDD
Supply Voltage
IDD
Supply Current
Digital Inputs = 0V or VDD
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: ±1LSB = ±0.0015% of full scale = ±15.3ppm of full scale.
Note 3: Using internal feedback resistor.
Note 4: Guaranteed by design, not subject to test.
Note 5: IOUT1 with DAC register loaded with all 0s.
Note 6: Typical temperature coefficient is 100ppm/C.
Note 7: OUT1 load = 100Ω in parallel with 13pF.
4
●
Note 8: To 0.0015% for a full-scale change, measured from the falling
edge of LD1, LD2 or LD.
Note 9: VREF = 6VRMS at 1kHz. DAC register loaded with all 1s;
op amp = LT1007.
Note 10: Calculation from en = √4kTRB where: k = Boltzmann constant
(J/°K); R = resistance (Ω); T = temperature (°K); B = bandwidth (Hz).
Note 11: Minimum high time for STB1, STB2, STB4. Minimum low time
for STB3.
Note 12: Minimum low time for STB1, STB2, STB4. Minimum high time
for STB3.
LTC1595/LTC1596/LTC1596-1
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TYPICAL PERFOR A CE CHARACTERISTICS
Mid-Scale Glitch Inpulse
0
LD FALLING EDGE
–10
Differential Nonlinearity (INL)
1.0
0.8
0.8
DIFFERENTIAL NONLINEARITY (LSB)
INTEGRAL NONLINEARITY (LSB)
1nV-s TYP
USING LT1122 OP AMP
CFEEDBACK = 33pF
VREF = 10V
+10
OUTPUT VOLTAGE (mV)
Integral Nonlinearity (INL)
1.0
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
– 0.8
0
1
2
TIME (µs)
3
–1.0
4
0.2
0
– 0.2
– 0.4
– 0.6
– 0.8
–1.0
49152
16384
32768
DIGITAL INPUT CODE
0
1595/96 G01
0
65535
Differential Nonlinearity
vs Reference Voltage
1.0
USING LT1122 OP AMP
CFEEDBACK = 33pF
DIFFERENTIAL NONLINEARITY (LSB)
1595/96 G04
INTEGRAL NONLINEARITY (LSB)
1.0
GATED
SETTLING
WAVEFORM
500µV/DIV
0.5
0
–10 – 8 – 6 – 4 – 2 0 2 4 6
REFERENCE VOLTAGE (V)
8
0.5
0
–10 – 8 – 6 – 4 – 2 0 2 4 6
REFERENCE VOLTAGE (V)
10
– 40
– 60
– 80
–100
–120
100
ALL
BITS
ON
ALL
BITS OFF
2
1.0
VREF = 10V
1
VREF = 2.5V
USING LT1122 OP AMP
CFEEDBACK = 33pF
0
1k
100k
10k
FREQUENCY (Hz)
1M
10M
1595/96 G07
10
Differential Nonlinearity
vs Supply Voltage
DIFFERENTIAL NONLINEARITY (LSB)
ATTENUATION (dB)
–20
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Integral Nonlinearity
vs Supply Voltage
INTEGRAL NONLINEARITY (LSB)
0
8
1595/96 G06
1595/96 G05
Multiplying Mode Frequency
Response vs Digital Code
65535
1595/96 G03
Integral Nonlinearity
vs Reference Voltage
DAC
OUTPUT
5V/DIV
49152
32768
16384
DIGITAL INPUT CODE
1595/96 TA02
Full-Scale Settling Waveform
1µs/DIV
0.6
0.4
0.5
0
2
3
4
8
6
5
7
SUPPLY VOLTAGE (V)
9
10
1595/96 G08
2
3
4
8
6
5
7
SUPPLY VOLTAGE (V)
9
10
1595/96 G09
5
LTC1595/LTC1596/LTC1596-1
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TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current
vs Logic Input Voltage
1.0
Logic Threshold
vs Supply Voltage
3.0
VDD = 5V
0.9
2.5
LOGIC THRESHOLD (V)
SUPPLY CURRENT (mA)
0.8
0.7
0.6
0.5
0.4
0.3
0.2
2.0
1.5
1.0
0.5
0.1
0
0
1
0
3
2
INPUT VOLTAGE (V)
4
5
0
1
2
3 4 5 6 7 8
SUPPLY VOLTAGE (V)
9
10
1595/96 G11
1595/96 G10
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PIN FUNCTIONS
LTC1595
VREF (Pin 1): Reference Input.
RFB (Pin 2): Feedback Resistor. Normally tied to the output
of the current to voltage converter op amp.
OUT1 (Pin 3): Current Output Pin. Tie to inverting input of
current to voltage converter op amp.
GND (Pin 4): Ground Pin.
LD (Pin 5): The Serial Interface Load Control Input. When
LD is pulled low, data is loaded from the shift register into
the DAC register, updating the DAC output.
SRI (Pin 6): The Serial Data Input. Data on the SRI pin is
latched into the shift register on the rising edge of the serial
clock. Data is loaded MSB first.
CLK (Pin 7): The Serial Interface Clock Input.
VDD (Pin 8): The Positive Supply Input. 4.5V ≤ VDD ≤ 5.5V.
Requires a bypass capacitor to ground.
LTC1596/LTC1596-1
OUT1 (Pin 1): True Current Output Pin. Tie to inverting
input of current to voltage converter op amp.
OUT2 (Pin 2): Complement Current Output Pin. Tie to
analog ground.
AGND (Pin 3): Analog Ground Pin.
6
STB1, STB2, STB3, STB4 (Pins 4, 8, 10, 11): Serial
Interface Clock Inputs. STB1, STB2 and STB4 are rising
edge triggered inputs. STB3 is a falling edge triggered
input (see Truth Tables).
LD1, LD2 (Pins 5, 9): Serial Interface Load Control Inputs.
When LD1 and LD2 are pulled low, data is loaded from the
shift register into the DAC register, updating the DAC
output (see Truth Tables).
SRO (Pin 6): The Output of the Shift Register. Becomes
valid on the active edge of the serial clock.
SRI (Pin 7): The Serial Data Input. Data on the SRI pin is
latched into the shift register on the active edge of the
serial clock. Data is loaded MSB first.
DGND (Pin 12): Digital Ground Pin.
CLR (Pin 13): The Clear Pin for the DAC. Clears DAC to zero
scale when pulled low on LTC1596. Clears DAC to midscale
when pulled low on LTC1596-1. This pin should be tied to
VDD for normal operation.
VDD (Pin 14): The Positive Supply Input. 4.5V ≤ VDD ≤
5.5V. Requires a bypass capacitor to ground.
VREF (Pin 15): Reference Input.
RFB (Pin 16): Feedback Resistor. Normally tied to the
output of the current to voltage converter op amp.
LTC1595/LTC1596/LTC1596-1
TRUTH TABLES
Table 1. LTC1596/LTC1596-1 Input Register
Table 2. LTC1596/LTC1596-1 DAC Register
CONTROL INPUTS
CONTROL INPUTS
STB1 STB2 STB3 STB4
0
1
1
0
0
0
0
0
1
1
X
X
X
X
1
X
X
X
X
0
X
Input Register and SRO Operation
0
0
0
Serial Data Bit on SRI Loaded into Input
Register, MSB First
Data Bit or SRI Appears on SRO Pin
After 16 Clocked Bits
X
X
X
1
No Input Register Operation
No SRO Operation
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BLOCK DIAGRA
CLR
LD1
LD2
0
X
X
Reset DAC Register and Input Register to
All 0s (LTC1596) or to Midscale (LTC1596-1)
(Asynchronous Operation)
DAC Register Operation
1
1
1
X
X
1
No DAC Register Operation
1
0
0
Load DAC Register with the Contents of Input
Register
(LTC1595)
56k
VREF
56k
2 RFB
1
56k
56k
56k
56k
56k
56k
56k
112k
112k
112k
112k
7k
3 OUT1
4 GND
VDD 8
DECODER
D14
D15
(MSB)
CLK 7
D12
D11
DAC REGISTER
LOAD
LD 5
D13
CLK
•••
D0
(LSB)
INPUT 16-BIT SHIFT REGISTER
IN
6 SRI
1595 BD
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TI I G DIAGRA
(LTC1595)
tDH
tDS
tCL
tCH
CLK INPUT
tSRI
SRI
PREVIOUS
WORD
D15
MSB
D14
D1
D0
LSB
tASB
LD
tLD
1595 TD
7
LTC1595/LTC1596/LTC1596-1
W
BLOCK DIAGRA
(LTC1596/LTC1596-1)
56k
56k
VREF 15
16 RFB
56k
56k
56k
56k
56k
56k
56k
112k
112k
112k
112k
7k
1 OUT1
2 OUT2
VDD 14
3 AGND
DECODER
CLR 13
CLR
LD1 5
D14
D15
(MSB)
D12
D13
D11
•••
DAC REGISTER
LOAD
D0
(LSB)
LD2 9
CLR
STB1 4
IN
INPUT 16-BIT SHIFT REGISTER
CLK
STB2 8
7 SRI
OUT
1596 BD
STB3 10
STB4 11
6 SRO
DGND 12
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TI I G DIAGRA
(LTC1596/LTC1596-1)
t DS1
t DS2
t DS3
t DS4
t DH1
t DH2
t DH3
t DH4
STROBE INPUT
STB1, STB2, STB4
(INVERT FOR STB3)
D15
MSB
SRI
D14
t STB1
t STB2
t STB3
t STB4
t STB1
t STB2
t STB3
t STB4
D13
D0
LSB
D1
t SRI
t ASB
t LD1
t LD2
LD1, LD2
t PD
t PD1
SRO
D15 (MSB)
PREVIOUS WORD
D14
PREVIOUS WORD
D13
PREVIOUS WORD
D0 (LSB)
PREVIOUS WORD
D15 (MSB)
CURRENT WORD
1596 TD
8
LTC1595/LTC1596/LTC1596-1
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APPLICATIONS INFORMATION
Description
The 16-pin LTC1596 can operate in identical fashion to the
LTC1595 but offers additional pins for flexibility. Four
clock pins are available STB1, STB2, STB3 and STB4.
STB1, STB2 and STB4 operate like the CLK pin of the
LTC1595, capturing data on their rising edges. STB3
captures data on its falling edge (see Truth Table 1).
The LTC1595/LTC1596 are 16-bit multiplying DACs which
have serial inputs and current outputs. They use precision
R/2R technology to provide exceptional linearity and
stability. The devices operate from a single 5V supply and
provide ±10V reference input and voltage output ranges
when used with an external op amp. These devices have
a proprietary deglitcher that reduces glitch impulse to
1nV-s over a 0V to 10V output range.
The LTC1596 has two load pins, LD1 and LD2. To load
data, both pins must be taken low. If one of the pins is
grounded, the other pin will operate identically to LTC1595’s
LD pin. An asynchronous clear input (CLR) resets the
LTC1596 to zero scale (and the LTC1596-1 to midscale)
when pulled low (see Truth Table 2).
Serial I/O
The LTC1595/LTC1596 have SPI/MICROWIRE compatible serial ports that accept 16-bit serial words. Data is
accepted MSB first and loaded with a load pin.
The LTC1596 also has a data output pin SRO that can be
connected to the SRI input of another DAC to daisy-chain
multiple DACs on one 3-wire interface (see LTC1596
Timing Diagram).
The 8-pin LTC1595 has a 3-wire interface. Data is shifted
into the SRI data input on the rising edge of the CLK pin.
At the end of the data transfer, data is loaded into the DAC
register by pulling the LD pin low (see LTC1595 Timing
Diagram).
VREF
–10V TO 10V
Unipolar (2-Quadrant Multiplying) Mode
(VOUT = 0V to –VREF)
The LTC1595/LTC1596 can be used with a single op amp
to provide 2-quadrant multiplying operation as shown in
Figure 1. With a fixed –10V reference, the circuits shown
give a precision unipolar 0V to 10V output swing.
5V
0.1µF
13
10
4
7
5
6
9
8
11
µP
14
15
16
STB3 CLR VDD VREF RFB
STB1
SRI
LD1
LTC1596
SRO
LD2
STB2
STB4
DGND
AGND
12
0.1µF
7
µP
6
5
SRI
–
+
LT1001
VOUT
0V TO –VREF
2
(a)
Table 1. Unipolar Binary Code Table
2
RFB
LTC1595
OUT2
1
1595/96 F01a
VREF
–10V TO 10V
1
8
VDD VREF
CLK
OUT1
3
TO NEXT DAC
FOR DAISY-CHAINING
5V
33pF
33pF
OUT1 3
–
LD
+
GND
4
LT1001
1595/96 F01b
(b)
VOUT
0V TO –VREF
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
LSB
MSB
1111 1111 1111 1111
1000 0000 0000 0000
0000 0000 0000 0001
0000 0000 0000 0000
ANALOG OUTPUT
VOUT
–VREF (65,535/65,536)
–VREF (32,768/65,536) = –VREF/2
–VREF (1/65,536)
0V
Figure 1. Unipolar Operation (2-Quadrant Multiplication) VOUT = 0V to – VREF
9
LTC1595/LTC1596/LTC1596-1
U
U
W
U
APPLICATIONS INFORMATION
Bipolar (4-Quadrant Multiplying) Mode
(VOUT = – VREF to VREF)
The LTC1595/LTC1596 can be used with a dual op amp
and three external resistors to provide 4-quadrant multiplying operation as shown in Figure 2 (last page). With a
fixed 10V reference, the circuits shown give a precision
bipolar –10V to 10V output swing. Using the LTC1596-1
will cause the power-on reset and clear pin to reset the DAC
to midscale (bipolar zero).
Op Amp Selection
Because of the extremely high accuracy of the 16-bit
LTC1595/LTC1596, thought should be given to op amp
selection in order to achieve the exceptional performance
of which the part is capable. Fortunately, the sensitivity of
INL and DNL to op amp offset has been greatly reduced
compared to previous generations of multiplying DACs.
Op amp offset will contribute mostly to output offset and
gain and will have minimal effect on INL and DNL. For
example, a 500µV op amp offset will cause about 0.55LSB
INL degradation and 0.15LSB DNL degradation with a 10V
full-scale range. The main effects of op amp offset will be
a degradation of zero-scale error equal to the op amp
offset, and a degradation of full-scale error equal to twice
the op amp offset. For example, the same 500µV op amp
offset will cause a 3.3LSB zero-scale error and a 6.5LSB
full-scale error with a 10V full-scale range.
Op amp input bias current (IBIAS) contributes only a zeroscale error equal to IBIAS(RFB) = IBIAS(RREF) = IBIAS(7k).
Table 2 shows a selection of LTC op amps which are
suitable for use with the LTC1595/LTC1596. For a thorough discussion of 16-bit DAC settling time and op amp
selection, refer to Application Note 74, “Component and
Measurement Advances Ensure 16-Bit DAC Settling Time.”
Grounding
As with any high resolution converter, clean grounding is
important. A low impedance analog ground plane and star
grounding should be used. IOUT2 (LTC1596) and GND
(LTC1595) must be tied to the star ground with as low a
resistance as possible.
Table 2. 16-Bit Settling Time for Various Amplifiers Driven by the LT1595 DAC. LT1468 (Shaded) Offers Fastest Settling Time While
Maintaining Accuracy Over Temperature
AMPLIFIER
CONSERVATIVE SETTLING TIME
AND COMPENSATION VALUE
COMMENTS
LT1001
120µs
100pF
LT1007
19µs
100pF
IB Gives ≈1LSB Error at 25°C
LT1013
75µs
150pF
≈1LSB Error Due to VOS over Temperature
LT1077
200µs
100pF
LT1097
120µs
75pF
Good Low Speed Choice
LT1112
120µs
100pF
Good Low Speed Choice Dual
LT1178
450µs
100pF
Low Power Dual
LT1468
2.5µs
30pF
Fastest Settling with 16-Bit Performance
10
Good Low Speed Choice
LTC1595/LTC1596/LTC1596-1
U
PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package 8-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)
0.300 – 0.325
(7.620 – 8.255)
0.045 – 0.065
(1.143 – 1.651)
0.130 ± 0.005
(3.302 ± 0.127)
0.065
(1.651)
TYP
0.009 – 0.015
(0.229 – 0.381)
(
0.400*
(10.160)
MAX
+0.035
0.325 –0.015
+0.889
8.255
–0.381
)
8
7
6
5
1
2
3
4
0.255 ± 0.015*
(6.477 ± 0.381)
0.125
(3.175) 0.020
MIN
(0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
N8 1197
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.053 – 0.069
(1.346 – 1.752)
0.008 – 0.010
(0.203 – 0.254)
7
8
0.004 – 0.010
(0.101 – 0.254)
5
6
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.014 – 0.019
(0.355 – 0.483)
0.050
(1.270)
TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
SO8 0996
1
3
2
4
N Package 16-Lead PDIP (Narrow 0.300) (LTC DWG # 05-08-1510)
0.130 ± 0.005
(3.302 ± 0.127)
0.300 – 0.325
(7.620 – 8.255)
(
+0.035
0.325 –0.015
+0.889
8.255
–0.381
0.045 – 0.065
(1.143 – 1.651)
0.020
(0.508)
MIN
0.009 – 0.015
(0.229 – 0.381)
)
0.770*
(19.558)
MAX
0.065
(1.651)
TYP
0.125
(3.175)
MIN
15
14
13
12
11
10
1
2
3
4
5
6
7
9
0.255 ± 0.015*
(6.477 ± 0.381)
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
16
8
N16 1197
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
SW Package 16-Lead Plastic Small Outline (Wide 0.300) (LTC DWG # 05-08-1620)
0.291 – 0.299**
(7.391 – 7.595)
0.010 – 0.029 × 45°
(0.254 – 0.737)
0.398 – 0.413*
(10.109 – 10.490)
0.093 – 0.104
(2.362 – 2.642)
0.037 – 0.045
(0.940 – 1.143)
16
15
14
13
12
11
10
9
0° – 8° TYP
0.009 – 0.013
(0.229 – 0.330)
NOTE 1
0.016 – 0.050
(0.406 – 1.270)
0.050
(1.270)
TYP
0.014 – 0.019
(0.356 – 0.482)
TYP
0.394 – 0.419
(10.007 – 10.643)
NOTE 1
0.004 – 0.012
(0.102 – 0.305)
NOTE:
1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS.
THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
1
2
3
4
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
5
6
7
8
S16 (WIDE) 0396
11
LTC1595/LTC1596/LTC1596-1
U
TYPICAL APPLICATIONS
R2
20k
VREF
–10V TO 10V
R3
20k
5V
0.1µF
13
10
4
7
5
6
9
8
11
µP
15
14
16
STB3 CLR VDD VREF RFB
STB1
SRI
LD1
LTC1596-1
SRO
LD2
STB2
STB4
DGND
AGND
33pF
OUT1
–
1
R1
10k
1/2 LT1112
OUT2
+
(20k ÷ 2)
VOUT
–VREF TO VREF
1/2 LT1112
+
2
3
12
–
TO NEXT DAC
FOR DAISY-CHAINING
1595/96 F02a
RESISTORS: CADDOCK T914-20K-010-02
(OR EQUIVALENT) 20k, 0.01%, TC TRACK = 2ppm/°C
(a)
0.1µF
7
µP
6
5
8
1
2
VDD VREF
RFB
LTC1595
Table 3. Bipolar Offset Binary Code Table
33pF
CLK
SRI
R3
20k
R2
20k
VREF
–10V TO 10V
5V
OUT1
3
LD
–
R1
10k
1/2 LT1112
+
GND
4
(20k ÷ 2)
–
1/2 LT1112
+
VOUT
–VREF TO VREF
DIGITAL INPUT
BINARY NUMBER
IN DAC REGISTER
LSB
MSB
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
ANALOG OUTPUT
VOUT
VREF (32,767/32,768)
VREF (1/32,768)
0V
–VREF (1/32,768)
–VREF
1595/96 F02b
(b)
Figure 2. Bipolar Operation (4-Quadrant Multiplication) VOUT = – VREF to VREF
RELATED PARTS
PART NUMBER
DACs
LTC1590
LTC1597
LTC1650
LTC1658
LTC7543/LTC8143/LTC8043
ADCs
LTC1418
LTC1604
LTC1605
LTC2400
Op Amps
LT1001
LT1112
LT1468
References
LT1236
LT1634
12
DESCRIPTION
COMMENTS
Dual Serial I/O Multiplying IOUT 12-Bit DAC
Parallel 16-Bit Current Output DAC
Serial 16-Bit Voltage Output DAC
Serial 14-Bit Voltage Output DAC
Serial I/O Multiplying IOUT 12-Bit DACs
16-Pin SO and PDIP, SPI Interface
Low Glitch, ±1LSB Maximum INL, DNL
Low Noise and Glitch Rail-to-Rail VOUT
Low Power, 8-Lead MSOP Rail-to-Rail VOUT
Clear Pin and Serial Data Output (LTC8143)
14-Bit, 200ksps 5V Sampling ADC
16-Bit, 333ksps Sampling ADC
Single 5V, 16-Bit 100ksps ADC
24-Bit, ∆∑ ADC in SO-8
16mW Dissipation, Serial and Parallel Outputs
±2.5V Input, SINAD = 90dB, THD = 100dB
Low Power, ±10V Inputs
1ppm (4ppm) Offset (Full Scale), Internal 50Hz/60Hz Notches
Precision Operational Amplifier
Dual Low Power, Precision Picoamp Input Op Amp
90MHz, 22V/µs, 16-Bit Accurate Op Amp
Low Offset, Low Drift
Low Offset, Low Drift
Precise, 1µs Settling to 0.0015%
Precision Reference
Micropower Reference
Ultralow Drift, 5ppm/°C, High Accuracy 0.05%
Ultralow Drift, 10ppm/°C, High Accuracy 0.05%
Linear Technology Corporation
159561fa LT/TP 0299 2K REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 1997