AD AD7091RBCPZ-RL 1 msps, ultralow power, 12-bit adc in 10-lead lfcsp and msop Datasheet

FEATURES
FUNCTIONAL BLOCK DIAGRAM
REGCAP
Fast throughput rate of 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Logic voltage VDRIVE of 1.65 V to 5.25 V
INL of ±1 LSB maximum
Analog input range of 0 V to VREF
Ultralow power
349 µA typical at 3 V and 1 MSPS
264 nA typical at 3 V in power-down mode
Internal 2.5 V reference, ±4.5 ppm/°C typical drift
Wide input bandwidth
Flexible power/throughput rate management
High speed serial interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
BUSY indicator
Power-down mode
10-lead, 3 mm × 2 mm LFCSP and 10-lead MSOP packages
Temperature range of −40°C to +125°C
SDO
The conversion process and data acquisition are controlled using
a CONVST signal and an internal oscillator. The AD7091R has
a serial interface that allows data to be read after the conversion
while achieving a 1 MSPS throughput rate.
SCLK
SERIAL
INTERFACE
12-BIT
SAR
T/H
VIN
CS
VDRIVE
CLK
OSC
CONVERSION
CONTROL LOGIC
10494-001
CONVST
GND
Figure 1.
1100
VDD
= VVDRIVE
3V
V
DD =
DRIVE ==3V
1000
900
800
POWER (μW)
Battery-powered systems
Handheld meters
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
Optical sensors
Diagnostic/monitoring functions
Energy harvesting
The AD7091R is a 12-bit successive approximation analog-todigital converter (ADC) that offers ultralow power consumption
(typically 349 µA at 3 V and 1 MSPS) while achieving fast
throughput rates (1 MSPS with a 50 MHz SCLK). Operating
from a single 2.7 V to 5.25 V power supply, the part contains a
wide bandwidth track-and-hold amplifier that can handle input
frequencies in excess of 7 MHz. The AD7091R also features an
on-chip conversion clock, accurate reference, and high speed
serial interface.
VDD
AD7091R
2.5V
REF
APPLICATIONS
GENERAL DESCRIPTION
REFIN/REFOUT
700
600
500
VDD
400
300
200
100
VDRIVE
0
0
200
400
600
800
THROUGHPUT RATE (kSPS)
1000
10494-002
Data Sheet
1 MSPS, Ultralow Power,
12-Bit ADC in 10-Lead LFCSP and MSOP
AD7091R
Figure 2. Power vs. Throughput Rate
The AD7091R uses advanced design and process techniques to
achieve very low power dissipation at high throughput rates. An
on-chip, accurate 2.5 V reference is available.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Lowest Power 12-Bit SAR ADC Available.
On-Chip, Accurate 2.5 V Reference.
High Throughput Rate with Ultralow Power Consumption.
Flexible Power/Throughput Rate Management.
Average power scales with the throughput rate. Power-down
mode allows the average power consumption to be reduced
when the device is not performing a conversion.
Single Supply Operation with VDRIVE Function.
The AD7091R operates from a single 2.7 V to 5.25 V supply.
The VDRIVE function allows the serial interface to connect
directly to 1.8 V to 3.3 V processors.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2012 Analog Devices, Inc. All rights reserved.
AD7091R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Circuit Information .................................................................... 12
Applications ....................................................................................... 1
Converter Operation.................................................................. 12
Functional Block Diagram .............................................................. 1
ADC Transfer Function ............................................................. 12
General Description ......................................................................... 1
Internal/External Voltage Reference ........................................ 12
Product Highlights ........................................................................... 1
Typical Connection Diagram ................................................... 13
Revision History ............................................................................... 2
Analog Input ............................................................................... 13
Specifications..................................................................................... 3
Modes of Operation ................................................................... 14
Timing Specifications .................................................................. 5
Power Consumption .................................................................. 14
Absolute Maximum Ratings ............................................................ 6
Serial Interface ................................................................................ 16
Thermal Resistance ...................................................................... 6
With BUSY Indicator ................................................................. 16
ESD Caution .................................................................................. 6
Without BUSY Indicator ........................................................... 17
Pin Configuration and Function Descriptions ............................. 7
Software Reset ............................................................................. 18
Typical Performance Characteristics ............................................. 8
Interfacing With 8-/16-Bit SPI ................................................. 18
Terminology .................................................................................... 11
Outline Dimensions ....................................................................... 20
Theory of Operation ...................................................................... 12
Ordering Guide .......................................................................... 20
REVISION HISTORY
8/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
Data Sheet
AD7091R
SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE = 1.65 V to 5.25 V, VREF = 2.5 V internal reference, fSAMPLE = 1 MSPS, fSCLK = 50 MHz, TA = −40°C to +125°C,
unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE 1
Signal-to-Noise Ratio (SNR) 2
Test Conditions/Comments
fIN = 10 kHz sine wave
fSAMPLE = 500 kSPS
Signal-to-Noise-and-Distortion Ratio (SINAD)2
Total Harmonic Distortion (THD)2
Spurious Free Dynamic Range (SFDR)2
Aperture Delay2
Aperture Jitter2
Full Power Bandwidth2
Typ
66.5
67.5
66
69
70
69
−84
−85
5
40
7.5
1.2
At −3 dB
At −0.1 dB
DC ACCURACY
Resolution
Integral Nonlinearity (INL)2, 3
Differential Nonlinearity (DNL)2
Offset Error2
Gain Error2
Total Unadjusted Error (TUE)2
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance 4
Min
−79
−78
12
VDRIVE ≤ 3.3 V
VDRIVE > 3.3 V with external VREF
Guaranteed no missing codes to 12 bits
±0.3
±0.6
±0.8
−2
0
2.5
±4.5
LSB
LSB
LSB
LSB
LSB
LSB
VREF
±1
V
µA
pF
pF
2.525
VDD
±25
V
V
ppm/°C
0.3 × VDRIVE
±1
5
V
V
µA
pF
0.7 × VDRIVE
Typically 10 nA, VIN = 0 V or VDRIVE
ISOURCE = 200 µA
ISINK = 200 µA
Full-scale step input
Rev. 0 | Page 3 of 20
dB
dB
dB
dB
dB
ns
ps
MHz
MHz
±1
±1
±0.9
±2
±3
7
1
2.485
2.7
Unit
Bits
±0.8
During acquisition phase
Outside acquisition phase
VOLTAGE REFERENCE INPUT/OUTPUT
REFOUT
REFIN
Drift
LOGIC INPUTS
Input High Voltage (VINH)
Input Low Voltage (VINL)
Input Current (IIN)
Input Capacitance (CIN)4
LOGIC OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
Floating State Leakage Current
Floating State Output Capacitance4
Output Coding
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time2, 4
Throughput Rate
Max
VDRIVE − 0.2
0.4
±1
5
Straight binary
650
350
1
V
V
µA
pF
ns
ns
MSPS
AD7091R
Parameter
POWER REQUIREMENTS
VDD
VDRIVE
IDD
Normal Mode—Static 5
Data Sheet
Test Conditions/Comments
Min
Typ
2.7
1.65
Max
Unit
5.25
5.25
V
V
VIN = 0 V
VDD = 5.25 V
VDD = 3 V
22
21.6
60
33
µA
µA
VDD = 5.25 V, fSAMPLE = 1 MSPS
VDD = 3 V, fSAMPLE = 1 MSPS
VDD = 3 V, fSAMPLE = 100 kSPS
388
349
55
449
408
µA
µA
µA
VDD = 5.25 V
VDD = 5.25 V, TA = −40°C to +85°C
VDD = 3 V
VDD = 3 V, TA = −40°C to +85°C
VIN = 0 V
0.334
0.334
0.264
0.264
4.4
1.4
4.2
1.2
µA
µA
µA
µA
VDRIVE = 5.25 V
VDRIVE = 3 V
32
28
500
500
nA
nA
VDRIVE = 5.25 V, fSAMPLE = 1 MSPS
VDRIVE = 3 V, fSAMPLE = 1 MSPS
42
17
86
20
µA
µA
VDRIVE = 5.25 V
VDRIVE = 3 V
7
2
41
28
nA
nA
VDD = VDRIVE = 5.25 V
VDD = VDRIVE = 3 V
116
65
318
101
µW
µW
VDD = VDRIVE = 5.25 V, fSAMPLE = 1 MSPS
VDD = VDRIVE = 3 V, fSAMPLE = 1 MSPS
2.3
1
2.9
1.3
mW
mW
VDD = VDRIVE = 5.25 V
VDD = VDRIVE = 3 V
1.8
0.8
24
13
µW
µW
Normal Mode—Operational
Power-Down Mode
IDRIVE
Normal Mode—Static 6
Normal Mode—Operational
Power-Down Mode
Total Power Dissipation (PDD + PDRIVE)
Normal Mode—Static5
VIN = 0 V
Normal Mode—Operational
Power-Down Mode
Dynamic performance is achieved with a burst SCLK. Operating a free running SCLK during acquisition phase degrades dynamic performance.
See the Terminology section.
3
For VDRIVE < VDD + 0.7 V.
4
Sample tested during initial release to ensure compliance.
5
SCLK is operating in burst mode and CS is idling high. With a free running SCLK and CS pulled low, the IDD static current is increased by 30 µA typical at VDD = 5.25 V.
6
SCLK is operating in burst mode and CS is idling high. With a free running SCLK and CS pulled low, the IDRIVE static current is increased by 32 µA typical at VDRIVE = 5.25 V.
1
2
Rev. 0 | Page 4 of 20
Data Sheet
AD7091R
TIMING SPECIFICATIONS
VDD = 2.75 V to 5.25 V, VDRIVE = 1.65 V to 5.25 V, TA = −40°C to +125°C, unless otherwise noted. 1
Table 2.
Parameter
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
Limit at TMIN, TMAX
50
8
7
0.4 tSCLK
3
0.4 tSCLK
15
10
650
6
Unit
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns max
ns min
Description
Frequency of serial read clock
Delay from the end of a conversion until SDO three-state is disabled
Data access time after SCLK falling edge
SCLK high pulse width
SCLK to data valid hold time
SCLK low pulse width
SCLK falling edge to SDO high impedance
CONVST pulse width
Conversion time
CS low time before the end of a conversion
t10
18
ns max
Delay from CS until SDO three-state is disabled
t11
8
ns min
t12
8
ns min
CS high time before the end of a conversion
Delay from the end of a conversion until CS falling edge
t13
50
100
50
ms typ
µs max
ns min
Power-up time with internal reference 2
Power-up time with external reference
Time between last SCLK edge and next CONVST pulse
tQUIET
1
2
Sample tested during initial release to ensure compliance.
With a 2.2 µF reference capacitor.
Rev. 0 | Page 5 of 20
AD7091R
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VDRIVE to GND
Analog Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
ESD
HBM
FICDM
1
Table 4. Thermal Resistance
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VREF + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
±10 mA
−40°C to +125°C
−65°C to +150°C
150°C
Package Type
10-Lead LFCSP
10-Lead MSOP
ESD CAUTION
±2.5 kV
±1.5 kV
Transient currents of up to 100 mA do not cause silicon controlled rectifier
(SCR) latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 6 of 20
θJA
33.2
25.67
θJC
4
1.67
Unit
°C/W
°C/W
Data Sheet
AD7091R
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD 1
REGCAP 4
AD7091R
9
SDO
TOP VIEW
(Not to Scale)
8
SCLK
7
CS
6
CONVST
GND 5
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND
FOR MAXIMUM THERMAL CAPABILITY, SOLDER THE EXPOSED
PAD TO THE SUBSTRATE, GND.
10
VDRIVE
REFIN/REFOUT 2
AD7091R
9
SDO
VIN 3
TOP VIEW
(Not to Scale)
8
SCLK
7
CS
6
CONVST
VDD 1
REGCAP 4
GND 5
Figure 3. Pin Configuration, 10-Lead LFCSP
10494-004
VIN 3
10 VDRIVE
10494-003
REFIN/REFOUT 2
Figure 4. Pin Configuration, 10-Lead MSOP
Table 5. Pin Function Descriptions
Pin No.
LFCSP MSOP
1
1
Mnemonic
VDD
2
2
REFIN/REFOUT
3
4
3
4
VIN
REGCAP
5
5
GND
6
6
CONVST
7
7
CS
8
9
8
9
SCLK
SDO
10
10
VDRIVE
11
N/A
EPAD
Description
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. This supply pin should be decoupled to
GND. The typical recommended values are 10 µF and 0.1 µF.
Voltage Reference Input Output. Decouple this pin to GND. The typical recommended decoupling
capacitor value is 2.2 µF. The user can either access the internal 2.5 V reference or overdrive the
internal reference with an externally applied voltage. The reference voltage range for an externally
applied reference is 2.7 V to VDD.
Analog Input. The single-ended analog input range is from 0 V to VREF.
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. This output pin should be
decoupled separately to GND using a 1 μF capacitor. The voltage at this pin is 1.8 V typical.
Analog Ground. This pin is the ground reference point for all circuitry on the AD7091R. The analog
input signal should be referred to this GND voltage.
Convert Start. Active low edge triggered logic input. The falling edge of CONVST places the trackand-hold into hold mode and initiates a conversion.
Chip Select. Active low logic input. The serial bus is enabled when CS is held low, and in this mode CS
is used to frame the output data on the SPI bus.
Serial Clock. This pin acts as the serial clock input.
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input. The data is provided MSB first.
Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage of the
interface. Decoupling capacitors should be connected between VDRIVE and GND. The typical
recommended values are 10 µF and 0.1 µF. The voltage range of this pin is 1.65 V to 5.25 V.
Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder
joints and for maximum thermal capability, solder the exposed pad to the substrate, GND.
Rev. 0 | Page 7 of 20
AD7091R
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
72
–20
VDD = 2.7V
VDRIVE = 3.3V
TA = 25°C
fIN = 10kHz
–40
fSAMPLE = 1 MSPS
–60
SNR = 69.32dB
SINAD = 68.66dB
THD = –84.42dB
70
2.7V
3.0V
5.0V
68
SNR (dB)
SNR (dB)
0
–80
66
64
–100
62
–120
TA = 25°C
100
200
300
400
500
FREQUENCY (kHz)
1
Figure 8. SNR vs. Analog Input Frequency
for Various Supply Voltages
1.0
0
VDD = 2.7V
VDRIVE = 3.3V
TA = 25°C
fSAMPLE = 1 MSPS
0.6
0.2
–40
THD (dB)
–30
0.0
–0.2
–50
–70
–0.6
–80
–90
–1.0
–100
1536
2048
2560
3072
3584
4096
CODE
10494-006
–0.8
1024
2.7V
3.0V
5.0V
–60
–0.4
512
fSAMPLE = 1MSPS
–20
0.4
0
TA = 25°C
–10
1
10
10494-009
0.8
100
INPUT FREQUENCY (kHz)
Figure 9. THD vs. Analog Input Frequency
for Various Supply Voltages
Figure 6. Typical INL Performance
–50
1.0
VDD = 2.7V
VDRIVE = 3.3V
TA = 25°C
fSAMPLE = 1 MSPS
0.8
0.6
TA = 25°C
VDD = 3V
fIN = 10kHz
fSAMPLE = 1MSPS
–55
–60
0.4
THD (dB)
0.2
0.0
–0.2
–0.4
–65
–70
–75
–0.6
–80
–1.0
0
512
1024
1536
2048
2560
3072
CODE
3584
4096
10494-007
–0.8
–85
10
100
1k
SOURCE IMPEDANCE (Ω)
Figure 10. THD vs. Source Impedance
Figure 7. Typical DNL Performance
Rev. 0 | Page 8 of 20
10k
10494-010
INL (LSB)
100
INPUT FREQUENCY (kHz)
Figure 5. Typical Dynamic Performance
DNL (LSB)
10
10494-008
0
60
10494-005
–140
Data Sheet
AD7091R
2.502
72
VDD = VDRIVE = 3V
2.500
70
2.498
2.7V
3.0V
5.0V
2.496
VREF (V)
SINAD (dB)
68
66
2.494
2.492
2.490
64
+25°C
–40°C
+85°C
+125°C
2.488
62
2.486
TA = 25°C
10
100
2.484
INPUT FREQUENCY (kHz)
0
60
80
100
Figure 14. Reference Voltage Output vs. Current Load
for Various Temperatures
450
60
53423
50
VDD = VDRIVE = 3V
65k SAMPLES
TA = 25°C
430
fSAMPLE = 1MSPS
410
40
30
20
390
370
350
330
310
290
10
6458
5655
2047
2048
2049
250
2.7
10494-012
0
2046
–40°C
+25°C
+85°C
+125°C
270
2050
CODE
3.2
3.7
4.2
4.7
5.2
VDD SUPPLY VOLTAGE (V)
Figure 12. Histogram of Codes at Code Center (VREF/2)
10494-015
IDD SUPPLY CURRENT (µA)
Figure 15. Operational IDD Supply Current vs. VDD Supply Voltage
for Various Temperatures
90
12
VDRIVE = 1.8V, +125°C
fSAMPLE = 1MSPS
VDRIVE = 1.8V, +25°C
80
IDRIVE SUPPLY CURRENT (µA)
10
8
VDRIVE = 1.8V, –40°C
VDRIVE = 3V, +125°C
6
4
VDRIVE = 3V, +25°C
VDRIVE = 3V, –40°C
VIN = 0V
70
60
50
40
30
20
–40°C
+25°C
+85°C
+125°C
2
10
10
20
30
40
SDO CAPACITANCE LOAD (pF)
50
0
1.65
10494-013
0
2.65
3.65
VDRIVE SUPPLY VOLTAGE (V)
Figure 13. tSDO Delay vs. SDO Capacitance Load and VDRIVE
4.65
10494-031
NUMBER OF OCCURRENCES (k)
40
CURRENT LOAD (µA)
Figure 11. SINAD vs. Analog Input Frequency
for Various Supply Voltages
tSDO DELAY (ns)
20
10494-014
1
10494-011
60
Figure 16. Operational IDRIVE Supply Current vs. VDRIVE Supply Voltage
for Various Temperatures
Rev. 0 | Page 9 of 20
AD7091R
Data Sheet
4000
3500
VDD = 3V, VDRIVE = 3V
VDD = 5V, VDRIVE = 5V
VDD = 5V, VDRIVE = 3.3V
TOTAL CURRENT (nA)
3000
2500
2000
1500
1000
0
–40
25
85
OPERATING TEMPERATURE (°C)
125
10494-032
500
Figure 17. Total Power-Down Supply Current (IDD and IDRIVE) vs. Temperature
for Various Supply Voltages
Rev. 0 | Page 10 of 20
Data Sheet
AD7091R
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. For the
AD7091R, the endpoints of the transfer function are zero scale
(a point 0.5 LSB below the first code transition) and full scale (a
point 0.5 LSB above the last code transition).
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
Total Unadjusted Error (TUE)
TUE is a comprehensive specification that includes the gain,
linearity, and offset errors.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental.
For the AD7091R, THD is defined as
THD (dB ) = 20 log
Offset Error
Offset error is the deviation of the first code transition (00 ...
000) to (00 ... 001) from the ideal (such as GND + 0.5 LSB).
Gain Error
Gain error is the deviation of the last code transition (111 ... 110)
to (111 ... 111) from the ideal (such as VREF − 1.5 LSB) after the
offset error has been adjusted out.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode after the
end of a conversion. The track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within ±0.5 LSB, after a conversion (see the
Serial Interface section for more details).
Signal-to-Noise Ratio (SNR)
SNR is the measured ratio of signal to noise at the output of the
ADC. The signal is the rms amplitude of the fundamental. Noise
is the sum of all nonfundamental signals up to half the sampling
frequency (fSAMPLE/2), excluding dc.
The ratio is dependent on the number of quantization levels in the
digitization process: the more levels, the smaller the quantization
noise. The theoretical signal-to-noise ratio for an ideal N-bit
converter with a sine wave input is given by
Signal-to-Noise Ratio = (6.02N + 1.76) dB
V2 2 + V3 2 + V4 2 + V5 2 + V6 2
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Spurious Free Dynamic Range (SFDR)
SFDR, also known as peak harmonic or spurious noise, is defined
as the ratio of the rms value of the next largest component in the
ADC output spectrum (up to fSAMPLE/2 and excluding dc) to the
rms value of the fundamental. Usually, the value of this specification is determined by the largest harmonic in the spectrum,
but for ADCs where the harmonics are buried in the noise floor,
the largest harmonic would be a noise peak.
Aperture Delay
Aperture delay is the measured interval between the leading
edge of the sampling clock and the point at which the ADC
samples data.
Aperture Jitter
Aperture jitter is the sample-to-sample variation in the effective
point in time at which the data is sampled.
Full Power Bandwidth
Full power bandwidth is the input frequency at which the
amplitude of the reconstructed fundamental is reduced by
0.1 dB or 3 dB for a full-scale input.
Therefore, for a 12-bit converter, the SNR is 74 dB.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the measured ratio of signal to noise and distortion at
the output of the ADC. The signal is the rms value of the sine
wave, and noise is the rms sum of all nonfundamental signals
up to half the sampling frequency (fSAMPLE/2), including
harmonics, but excluding dc.
Rev. 0 | Page 11 of 20
AD7091R
Data Sheet
THEORY OF OPERATION
CIRCUIT INFORMATION
SAMPLING
CAPACITOR
ACQUISITION
PHASE
CONTROL
LOGIC
SW2
COMPARATOR
GND
LDO/2
10494-017
SW1
B
CONTROL
LOGIC
SW2
COMPARATOR
Figure 19. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7091R is straight binary. The designed
code transitions occur midway between successive integer LSB
values, such as 0.5 LSB, 1.5 LSB, and so on. The LSB size for the
AD7091R is VREF/4096. The ideal transfer characteristics for the
AD7091R are shown in Figure 20.
ADC CODE
111 ... 111
111 ... 110
111 ... 000
1LSB = VREF /4096
011 ... 111
000 ... 010
000 ... 001
000 ... 000
0V 1LSB
VREF – 1LSB
ANALOG INPUT
Figure 20. AD7091R Ideal Transfer Characteristics
INTERNAL/EXTERNAL VOLTAGE REFERENCE
The AD7091R allows the choice of an internal voltage reference
or an external voltage reference.
CHARGE
REDISTRIBUTION
DAC
VIN
CONVERSION
PHASE
LDO/2
CONVERTER OPERATION
A
SW1
B
GND
The AD7091R also features a power-down option to save power
between conversions. The power-down feature is implemented
across the standard serial interface as described in the Modes of
Operation section.
The AD7091R is a successive approximation ADC based
around a charge redistribution DAC. Figure 18 and Figure 19
show simplified schematics of the ADC. Figure 18 shows the
ADC during its acquisition phase. SW2 is closed and SW1 is in
Position A, the comparator is held in a balanced condition, and
the sampling capacitor acquires the signal on VIN.
SAMPLING
CAPACITOR
A
10494-018
The AD7091R provides an on-chip track-and-hold ADC with
a serial interface housed in a tiny 10-lead LFCSP and 10-lead
MSOP packages. These packages offer considerable space-saving
advantages compared with alternative solutions. The serial clock
input accesses data from the part. The clock for the successive
approximation ADC is generated internally. The reference voltage
for the AD7091R is generated internally by an accurate on-chip
reference source. The analog input range for the AD7091R is
0 V to VREF.
VIN
10494-019
The AD7091R is a 12-bit successive approximation analog-todigital converter (ADC) that offers ultralow power consumption
(typically 349 µA at 3 V and 1 MSPS) while achieving fast
throughput rates (1 MSPS with a 50 MHz SCLK). The part can be
operated from a single power supply in the range of 2.7 V to 5.25 V.
CHARGE
REDISTRIBUTION
DAC
Figure 18. ADC Acquisition Phase
When the ADC starts a conversion, SW2 opens and SW1 moves
to Position B (see Figure 19), causing the comparator to become
unbalanced. The control logic and the charge redistribution DAC
are used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
Figure 20 show the ideal ADC transfer function.
The internal reference provides an accurate 2.5 V low temperature
drift voltage reference. The internal reference is available at the
REFIN/REFOUT pin. When using the internal reference, this pin
should be decoupled using a capacitor with a typical value of 2.2 µF
to achieve the specified performance. With a fully discharged
2.2 µF reference capacitor, the internal reference requires 50 ms
typically to fully charge to the 2.5 V REFOUT voltage level.
In power-down mode, the internal voltage reference is shut down.
After exiting power-down mode, adequate time should be allowed
for the reference capacitor to recharge before performing a conversion. The time required to recharge the reference capacitor is
dependent on the amount of charge remaining on the capacitor
when exiting power-down mode.
If the on-chip reference is used externally to the AD7091R, it is
recommended to buffer this reference before supplying the
external circuitry.
Alternatively, the AD7091R reference voltage can be applied
externally. If an external reference is applied to the device, the
internal reference is automatically overdriven. An externally
applied reference voltage should be in the range of 2.7 V to
5.25 V and should be connected to the REFIN/REFOUT pin.
Rev. 0 | Page 12 of 20
Data Sheet
AD7091R
TYPICAL CONNECTION DIAGRAM
analog input signal never exceeds VREF or VDD by more than
300 mV. These diodes can conduct a maximum of 10 mA
without causing irreversible damage to the part.
A positive power supply in the range of 2.7 V to 5.25 V should
be connected to the VDD pin, with typical values for decoupling
capacitors being 100 nF and 10 µF. These capacitors should be
placed as close as possible to the device pins. With the power
supply connected to the VDD pin, the AD7091R operates with
the internal 2.5 V reference, and the REFIN/REFOUT pin should
be decoupled using a capacitor with a typical value of 2.2 µF to
achieve the specified performance and provide an analog input
range of 0 V to VREF. The typical value for the regulator bypass
decoupling capacitor (REGCAP) is 1 µF. The voltage applied to
the VDRIVE input controls the voltage of the serial interface;
therefore, this pin should be connected to the supply voltage of
the microprocessor. VDRIVE can be set in the range of 1.65 V to
5.25 V. Typical values for the VDRIVE decoupling capacitors are
100 nF and 10 µF. The conversion result is output in a 12-bit
word with the MSB first.
VDD
VREF
D1
D3
R1
VIN
C1
1pF
D2
C3
2.5pF
NOTES
1. DURING THE CONVERSION PHASE, THE SWITCH IS OPEN.
DURING THE TRACK PHASE, THE SWITCH IS CLOSED.
Figure 21. Equivalent Analog Input Circuit
Capacitor C1 in Figure 21 is typically about 1 pF and can
primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on resistance of a switch.
This resistor is typically about 500 Ω. Capacitor C2 is the ADC
sampling capacitor and typically has a capacitance of 3.6 pF.
The AD7091R requires the user to initiate a software reset upon
power-up (see the Software Reset section).
In applications where harmonic distortion and signal-to-noise
ratio are critical, the analog input should be driven from a low
impedance source. Large source impedances significantly affect
the ac performance of the ADC. This may necessitate using an
input buffer amplifier as shown in Figure 22. The choice of the
op amp is a function of a particular application.
If an external reference is applied to the device, the internal
reference is automatically overdriven. An externally applied
reference voltage should be in the range of 2.7 V to 5.25 V and
should be connected to the REFIN/REFOUT pin.
If the BUSY indicator feature is required, a pull-up resistor of
typically 100 kΩ to VDRIVE should be connected to the SDO pin.
In addition, for applications in which power consumption is a
concern, the power-down mode can be used to improve the
power performance of the ADC (see the Modes of Operation
section for more details).
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of total harmonic distortion
(THD) that can be tolerated. The THD increases as the source
impedance increases and performance degrades. Figure 10 shows a
graph of THD vs. source impedance when using a supply voltage
of 3 V and a sampling rate of 1 MSPS.
ANALOG INPUT
Figure 21 shows an equivalent circuit of the AD7091R analog
input structure. The D1 and D2 diodes provide ESD protection
for the analog input. The D3 diode is a parasitic diode between
VIN and VREF. To prevent the diodes from becoming forwardbiased and from starting to conduct current, ensure that the
Use an external filter—such as a one-pole, low-pass RC filter, or
similar, as shown in Figure 22—on the analog input connected
to the AD7091R to achieve the specified performances.
WITH BUSY
INDICATION
VDRIVE
100kΩ
1.65V TO 5.25V
2.7V TO 5.25V
100nF
10µF
VDD
VDRIVE
REGCAP
100nF
SDO
SCLK
AD7091R
1µF
CS
51Ω
ANALOG
INPUT
4.7nF
VIN
GND
MICROPROCESSOR/
MICROCONTROLLER/
DSP
REFIN/ CONVST
REFOUT
2.2µF
Figure 22. AD7091R Typical Connection Diagram
Rev. 0 | Page 13 of 20
10494-020
10µF
C2
3.6pF
10494-021
Figure 22 shows a typical connection diagram for the AD7091R.
AD7091R
Data Sheet
MODES OF OPERATION
The mode of operation of the AD7091R is selected by controlling
the logic state of the CONVST signal when a conversion is
complete.
The logic level of the CONVST pin at the end of a conversion
determines whether the AD7091R remains in normal mode or
enters power-down mode (see the Normal Mode and PowerDown Mode sections). Similarly, if the device is already in
power-down mode, CONVST controls whether the device
returns to normal mode or remains in power-down mode.
These modes of operation provide flexible power management
options, allowing optimization of the ratio of the power dissipation
to the throughput rate for different application requirements.
Normal Mode
The normal mode of operation is intended to achieve the fastest
throughput rate performance. Users do not have to worry about
power-up times because the AD7091R remains fully powered at
all times. Figure 29 shows the general timing diagram of the
AD7091R in normal mode.
In this mode, the conversion is initiated on the falling edge
of CONVST, as described in the Serial Interface section. To
ensure that the part remains fully powered up at all
times, CONVST must return high after t7 and remain high until
the conversion is complete. At the end of a conversion (denoted
as EOC in Figure 27), the logic state of CONVST is tested.
The serial interface of the AD7091R is functional in powerdown mode; therefore, users can read back the conversion
result after the part enters power-down mode.
To exit this mode of operation and power up the AD7091R,
pull CONVST high at any time. On the rising edge of CONVST,
the device begins to power up. The internal circuitry of the
AD7091R requires 100 μs to power up from power-down mode.
If the internal reference is used, the reference capacitor must be
fully recharged before accurate conversions are possible.
To start the next conversion after exiting power-down mode,
operate the interface as described in the Normal Mode section.
POWER CONSUMPTION
The two modes of operation for the AD7091R—normal mode
and power-down mode (see the Modes of Operation section for
more information)—produce different power vs. throughput
rate performances. Using a combination of normal mode and
power-down mode achieves the optimum power performance.
To calculate the overall power consumption, the IDRIVE current
should also be taken into consideration. Figure 16 shows the IDRIVE
current at various supply voltages. Figure 23 and Figure 24 show
the power consumption for VDRIVE with various throughput rates.
Improved power consumption for the AD7091R can be achieved
by carefully selecting the VDD and VDRIVE supply voltages and the
SDO line capacitance (see Figure 15 and Figure 16).
Normal Mode
To read back data stored in the conversion result register, wait until
the conversion is complete, and then pull CS low. The conversion
data is subsequently clocked out on the SDO pin (see Figure 29).
Because the output shift register is 12 bits wide, data is shifted
out of the device as a 12-bit word under the control of the serial
clock input (SCLK). After reading back the data, the user can
pull CONVST low again to start another conversion after the
tQUIET time has elapsed.
With a 3 V VDD supply and a throughput rate of 1 MSPS, the IDD
current consumption for the part in normal operational mode is
349 μA (composed of 21.6 μA of static current and 327.4 μA of
dynamic current during conversion). The dynamic current
consumption is directly proportional to the throughput rate.
Power-Down Mode
The dynamic conversion time contributes 491 μW to the overall
power dissipation as follows:
The power-down mode of operation is intended for use in
applications where slower throughput rates and lower power
consumption are required. In this mode, the ADC can be
powered down either between each conversion or between a
series of conversions performed at a high throughput rate, with
the ADC powered down for relatively long durations between
these bursts of several conversions. When the AD7091R is in
power-down mode, the serial interface remains active even
though all analog circuitry, including the internal voltage
reference, is powered down.
The following example calculates the power consumption of
AD7091R when operating in normal mode with a 500 kSPS
throughput rate and a 3 V supply.
((500 kSPS/1 MSPS) × 327.4 μA) × 3 V = 491 μW
The contribution to the total power dissipated by the normal
mode static operation is
21.6 μA × 3 V = 65 μW
Therefore, the total power dissipated at 500 kSPS is
To enter power-down mode, pull CONVST low and keep it low
until the end of a conversion (denoted as EOC in Figure 30). After
the conversion is complete, the logic level of the CONVST pin is
tested. If the CONVST signal is logic low at this point, the part
enters power-down mode.
Rev. 0 | Page 14 of 20
491 μW + 65 μW = 556 μW
Data Sheet
AD7091R
Normal and Power-Down Mode Combination
VDRIVE supply. Power consumption for the VDRIVE supply can be
calculated by the same principles as those for the VDD supply.
The internal circuitry of the AD7091R requires 100 μs to power
up from power-down mode. Power-down mode can therefore
be performed at sampling rates of less than 10 kSPS.
Additionally, Figure 24 shows the reduction in power consumption
that can be achieved when power-down mode is used compared
with using only normal mode at lower throughput rates.
1100
VDD
= VVDRIVE
3V
V
DD =
DRIVE ==3V
1000
Recharging the reference capacitor should also be considered
when using the on-chip reference. The AD7091R can fully
charge a 2.2 µF reference capacitor in typically 50 ms. However,
the time to charge the reference capacitor is dependent on the
amount of charge remaining on the capacitor when exiting
power-down mode. The reference capacitor loses charge very
slowly, resulting in much faster recharge times.
900
POWER (μW)
800
Figure 25 shows the AD7091R conversion sequence with a
combination of normal mode and power-down mode with a
throughput of 5 kSPS when using an external reference. With a VDD
supply voltage of 3 V, the static current is 21.6 μA. The dynamic
current is 327.4 μA at 1 MSPS. The current consumption during
power-down mode is 264 nA. A conversion requires 650 ns to
complete, and the AD7091R requires 100 μs to power up from
power-down mode when using an external reference.
700
600
500
VDD
400
300
200
100
VDRIVE
0
0
200
400
600
800
1000
THROUGHPUT RATE (kSPS)
Figure 23. Power Dissipation vs. Throughput Rate (Full Range)
1000
The dynamic conversion time contributes 4.9 μW to the overall
power dissipation as follows:
100
((5 kSPS/1 MSPS) × 327.4 μA) × 3 V = 4.9 μW
VDD = VDRIVE = 3V
VIN = 0V
EXTERNAL REFERENCE
POWER (μW)
10
The contribution to the total power dissipated by the normal
mode static operation and power-down mode is
((100.6 μs/200 μs) × 21.6 μA) × 3 V +
1
0.1
((99.4 μs/200 μs) × 264 nA) × 3 V = 33 μW
0.001
0.01
The total power dissipated at 5 kSPS is
0.1
1
10
100
THROUGHPUT RATE (kSPS)
4.9 μW + 33 μW = 37.9 μW
Figure 24. Power Dissipation vs. Throughput Rate (Lower Range)
Figure 23 and Figure 24 show the typical power vs. throughput
rate for the AD7091R at 3 V for the VDD supply and for the
EOC
CONVST
650ns
CONVERSION
99µs
POWER-DOWN
100µs
POWER-UP
DATA
200µs
Figure 25. 10 SPS with Normal and Power-Down Mode
Rev. 0 | Page 15 of 20
10494-022
CS
10494-117
VDD (NO PD)
VDRIVE (NO PD)
VDD
VDRIVE
0.01
The conversion time of 650 ns is included in the static operation time.
SDO
10494-016
A combination of normal mode and power-down mode
achieves the optimum power performance.
AD7091R
Data Sheet
SERIAL INTERFACE
the AD7091R to enter power-down mode, CONVST should be
taken high before the end of the conversion. A conversion
requires 650 ns to complete. When the conversion process is
finished, the track-and-hold goes back to track mode. Before
the end of a conversion, pull CS low to enable the BUSY
indicator feature.
The AD7091R serial interface consists of four signals: SDO,
SCLK, CONVST, and CS. The serial interface is used for
accessing data from the result register and controlling the
modes of operation of the device. SCLK is the serial clock input
for the device, and SDO data transfers take place with respect to
this SCLK. The CONVST signal is used to initiate the
conversion process and to select the mode of operation of the
AD7091R (see the Modes of Operation section). CS is used to
frame the data. The falling edge of CS takes the SDO line out of a
high impedance state. A rising edge on CS returns the SDO to a
high impedance state.
The conversion result is shifted out of the device as a 12-bit
word under the control of SCLK and the logic state of CS at the
end of a conversion. At the end of a conversion, SDO is driven
low. SDO remains low until the MSB (DB11) of the conversion
result is clocked out on the first falling edge of SCLK. DB10 to
DB0 are shifted out on the subsequent falling edges of SCLK.
The 13th SCLK falling edge returns SDO to a high impedance
state. Data is propagated on SCLK falling edges and is valid on
both the rising and falling edges of the next SCLK. The timing
diagram for this mode is shown in Figure 27.
The logic level of CS at the end of a conversion determines whether
the BUSY indicator feature is enabled. This feature affects the
propagation of the MSB with respect to CS and SCLK.
WITH BUSY INDICATOR
If another conversion is required, pull CONVST low again and
repeat the read cycle.
When the BUSY indicator feature is enabled, the SDO pin can
be used as an interrupt signal to indicate that a conversion is
complete. The connection diagram for this configuration is
shown in Figure 26. Note that a pull-up resistor to VDRIVE is
required on the SDO pin. This allows the host to detect when
the SDO pin exits the three-state condition after the end of a
conversion. In this mode, 13 SCLK cycles are required: 12 clock
cycles to propagate out the data and an additional clock cycle to
return the SDO pin to the three-state condition.
CS1
CONVERT
VDRIVE
100kΩ
CONVST
AD7091R
DATA IN
SDO
SCLK
To enable the BUSY indicator feature, a conversion should first
be started. A high-to-low transition on CONVST initiates a
conversion. This puts the track-and-hold into hold mode and
samples the analog input at this point. If the user does not want
DIGITAL HOST
IRQ
CLK
10494-025
CS
Figure 26. Connection Diagram with BUSY Indicator
EOC
t7
CONVST
tQUIET
t8
CS
t9
t3
t1
SDO
THREE-STATE
3
2
4
10
5
11
12
t5
t2
DB11
t6
t4
DB10
DB9
DB8
DB7
DB2
NOTES
1. EOC IS THE END OF A CONVERSION.
Figure 27. Serial Port Timing with BUSY Indicator
Rev. 0 | Page 16 of 20
13
DB1
DB0
THREE-STATE
10494-026
1
SCLK
Data Sheet
AD7091R
WITHOUT BUSY INDICATOR
The data is shifted out of the device as a 12-bit word under the
control of SCLK and CS. The MSB (Bit DB11) is clocked out on the
falling edge of CS. DB10 to DB0 are shifted out on the subsequent
falling edges of SCLK. The 12th falling SCLK edge returns SDO
to a high impedance state. After all the data is clocked out, pull
CS high again. SCLK should idle low in this mode to ensure that
the MSB is not lost. Data is propagated on SCLK falling edges
and is valid on both the rising and falling edges of the next SCLK.
The timing diagram for this operation is shown in Figure 28.
To operate the AD7091R without the BUSY indicator feature
enabled, a conversion should first be started. A high-to-low
transition on CONVST initiates a conversion. This puts the
track-and-hold into hold mode and samples the analog input
at this point. If the user does not want the AD7091R to enter
power-down mode, CONVST should be taken high before the
end of the conversion. A conversion requires 650 ns to complete.
When the conversion process is finished, the track-and-hold
goes back to track mode. To prevent the BUSY indicator feature
from becoming enabled, ensure that CS is pulled high before
the end of the conversion.
If another conversion is required, pull CONVST low and repeat
the read cycle.
EOC
t7
CONVST
tQUIET
t8
t12
CS
t11
t3
1
SCLK
3
4
5
10
12
11
t5
t2
t10
SDO
2
THREE-STATE
DB11
DB10
t6
t4
DB9
DB8
DB7
DB2
DB0
THREE-STATE
10494-027
NOTES
1. EOC IS THE END OF A CONVERSION.
DB1
Figure 28. Serial Port Timing Without BUSY Indicator
Rev. 0 | Page 17 of 20
AD7091R
Data Sheet
SOFTWARE RESET
INTERFACING WITH 8-/16-BIT SPI
The AD7091R requires the user to initiate a software reset when
power is first applied. It should be noted that failure to apply
the correct software reset command may result in a device
malfunction.
It is also possible to interface the AD7091R with a conventional
8-/16-bit SPI bus.
Performing conversions and reading results can be achieved by
configuring the host SPI interface to 16 bits, which results in
providing an additional four SCLK cycles to complete a conversion
compared with the standard interface methods (see the With
BUSY Indicator and Without BUSY Indicator sections). After
the 13th SCLK falling edge with the BUSY indicator feature
enabled or the 12th SCLK falling edge with the BUSY indicator
feature disabled, SDO returns to a high impedance state. The
additional four bits should be treated as don’t cares by the host.
All other timings are as outlined in Figure 27 and Figure 28,
with tQUIET starting after the 16th SCLK cycle.
To issue a software reset,
1.
2.
3.
4.
Start a conversion.
Read back the conversion result by pulling CS low after the
conversion is complete.
Between the second and eighth SCLK cycles, pull CS high
to short cycle the read operation.
At the end of the next conversion, the software reset is
executed.
If using the on-chip internal reference, the user should wait until
the reference capacitor is fully charged to meet the specified
performance.
A software reset can be performed by configuring the SPI bus to
eight bits and performing the operation outlined in the Software
Reset section.
The timing diagram for this operation is shown in Figure 31.
EOC
t7
CONVST
t8
t12
CS
t10
CONVERSION DATA
SDO
1.
10494-028
NOTES
DON’T CARE.
2. EOC IS THE END OF A CONVERSION.
Figure 29. Serial Interface Read Timing—Normal Mode
EOC
POWER-DOWN MODE
CONVST
t13
t8
t12
CS
t10
CONVERSION DATA
SDO
1.
10494-029
NOTES
DON’T CARE.
2. EOC IS THE END OF A CONVERSION.
Figure 30. Entering/Exiting Power-Down Mode
Rev. 0 | Page 18 of 20
Data Sheet
AD7091R
EOC/
SOFTWARE
RESET
EOC
t7
t7
CONVST
t8
t8
t12
CS
t10
SHORT CYCLE READ
SDO
t3
SCLK
1
2
6
7
8
t5
10494-030
NOTES
1.
DON’T CARE.
2. EOC IS THE END OF A CONVERSION.
Figure 31. Software Reset Timing
Rev. 0 | Page 19 of 20
AD7091R
Data Sheet
OUTLINE DIMENSIONS
2.54
2.44
2.34
3.10
3.00
2.90
2.10
2.00
1.90
PIN 1 INDEX
AREA
1.00
0.90
0.80
EXPOSED
PAD
0.35
0.30
0.25
5
1
BOTTOM VIEW
TOP VIEW
0.05 MAX
0.02 NOM
0.30
0.25
0.20
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.203 REF
05-06-2010-B
0.80
0.75
0.70
SEATING
PLANE
0.50 BSC
10
6
COMPLIANT TO JEDEC STANDARDS MO-229-WCED-3
Figure 32. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 2 mm Body, Very Very Thin, Dual Lead
(CP-10-12)
Dimensions shown in millimeters
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
6°
0°
0.23
0.13
COMPLIANT TO JEDEC STANDARDS MO-187-BA
0.70
0.55
0.40
091709-A
0.15
0.05
COPLANARITY
0.10
Figure 33. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD7091RBCPZ-RL
AD7091RBCPZ-RL7
AD7091RBRMZ
AD7091RBRMZ-RL7
EVAL-AD7091RSDZ
EVAL-SDP-CB1Z
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
Evaluation Board
Evaluation Controller Board
Z = RoHS Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10494-0-8/12(0)
Rev. 0 | Page 20 of 20
Package Option
CP-10-12
CP-10-12
RM-10
RM-10
Branding
C7P
C7P
DRQ
DRQ