ON NCY9100DWR2G Compandor Datasheet

NCY9100
Compandor
The NCY9100 is a versatile low cost dual gain control circuit in
which either channel may be used as a dynamic range compressor or
expandor. Each channel has a full−wave rectifier to detect the average
value of the signal, a linerarized temperature−compensated variable
gain cell, and an operational amplifier.
The NCY9100 is well suited for use in cellular radio and radio
communications systems, modems, telephone, and satellite
broadcast/receive audio systems.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
16
Complete Compressor and Expandor in one IChip
Temperature Compensated
Greater than 110 dB Dynamic Range
Operates Down to 6.0 VDC
System Levels Adjustable with External Components
Distortion may be Trimmed Out
Dynamic Noise Reduction Systems
Voltage Controlled Amplifier
This is a Pb−Free Device
16
1
NCY9100
AWLYYWWG
SOIC−16 WB
D SUFFIX
CASE 751G
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Applications
•
•
•
•
•
Cellular Radio
High Level Limiter
Low Level Expandor − Noise Gate
Dynamic Filters
CD Player
PIN CONNECTIONS
RECT CAP 1
1
16
RECT CAP 2
RECT IN 1
2
15
DG CELL IN 1
3
14
RECT IN 2
DG CELL IN 2
VCC
GND
4
13
INV. IN 1
RES. R3 1
5
12
INV. IN 2
6
11
RES. R3 2
OUTPUT 1
7
10
OUTPUT 2
THD TRIM 1
8
9
THD TRIM 2
TOP VIEW
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2009
April, 2009 − Rev. 0
1
Publication Order Number:
NCY9100/D
NCY9100
THD TRIM
DG IN
R2 20kW
RECT IN R1 10kW
INVERTER IN
R3
VARIABLE
GAIN
R3 20kW
−
R4 30kW
VREF
1.8V
OUTPUT
+
RECTIFIER
RECT CAP
Figure 1. Block Diagram
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VCC
18
VDC
Operating Ambient Temperature Range
TA
−40 to +85
°C
Operating Junction Temperature
TJ
150
°C
Power Dissipation
PD
400
mW
RqJA
105
°C/W
Maximum Operating Voltage
Thermal Resistance, Junction−to−Ambient
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
NCY9100
ELECTRICAL CHARACTERISTICS (VCC = +15 V, TA = 25°C, unless otherwise noted)
Characteristic
Symbol
Test Conditions
Min
Typ
Max
Unit
Supply Voltage
VCC
−
6.0
−
18
V
Supply Current
ICC
No Signal
−
4.2
4.8
mA
Output Current Capability
IOUT
−
± 20
−
−
mA
SR
−
−
± .5
−
V/ms
Untrimmed
Trimmed
−
0.5
0.1
2.0
%
Resistor Tolerance
−
−
±5
± 15
%
Internal Reference Voltage
−
1.65
1.8
1.95
V
Output DC Shift (Note 3)
Untrimmed
−
± 90
± 150
mV
Expandor Output Noise
No Signal, 15 Hz−20 kHz
(Note 1)
−
20
60
mV
1.0 kHz
−1.5
0
+1.5
dBm
Gain Change (Notes 2 and 4)
−
−
± 0.1
−
dB
Reference Drift (Note 4)
−
−
+2.0, −25
+20, −50
mV
−40°C to +85°C
−
+10, −12
−
%
Rectifier Input,
VCC = +6.0 V
V2 = +6.0 dBm, V1 = 0 dB
V2 = −30 dBm, V1 = 0 dB
−
−
−
Output Slew Rate
Gain Cell Distortion (Note 2)
Unity Gain Level (Note 5)
Resistor Drift (Note 4)
Tracking Error
(Measured Relative to Value at Unity Gain)
Equals [VO − VO (unity gain)] dB − V2dBm
Channel Separation
1.
2.
3.
4.
5.
Input to V1 and V2 grounded.
Measured at 0 dBm, 1.0 kHz.
Expandor AC input change from no signal to 0 dBm.
Relative to value at TA = 25°C.
0 dBm = 775 mVRMS.
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3
dB
+0.2
+0.2
−1.0, +1.5
60
−
dB
NCY9100
Circuit Description
as brought out externally. A resistor, R3, is brought out from
the summing node and allows compressor or expander gain
to be determined only by internal components.
The output stage is capable of ± 20 mA output current.
This allows a +13 dBm (3.5 VRMS) output into a 300 W load
which, with a series resistor and proper transformer, can
result in +13 dBm with a 600 W output impedance.
A bandgap reference provides the reference voltage for all
summing nodes, a regulated supply voltage for the rectifier
and DG cell, and a bias current for the DG cell. The low
tempco of this type of reference provides very stable biasing
over a wide temperature range.
The typical performance characteristics illustration
shows the basic input−output transfer curve for basic
compressor or expander circuits.
The NCY9100 compandor building blocks, as shown in
the block diagram, are a full−wave rectifier, a variable gain
cell, an operational amplifier and a bias system. The
arrangement of these blocks in the IC result in a circuit
which can perform well with few external components, yet
can be adapted to many diverse applications.
The full−wave rectifier rectifies the input current which
flows from the rectifier input, to an internal summing node
which is biased at VREF. The rectified current is averaged on
an external filter capacitor tied to the CRECT terminal, and
the average value of the input current controls the gain of the
variable gain cell. The gain will thus be proportional to the
average value of the input signal for capacitively−coupled
voltage inputs as shown in the following equation. Note that
for capacitively−coupled inputs there is no offset voltage
capable of producing a gain error. The only error will come
from the bias current of the rectifier (supplied internally)
which is less than 0.1 mA.
COMPRESSOR INPUT LEVEL OR EXPANDOR
OUTPUT LEVEL (dBm)
+20
|V * V REF | avg
G T IN
R1
or
GT
| V IN | avg
R1
The speed with which gain changes to follow changes in
input signal levels is determined by the rectifier filter
capacitor. A small capacitor will yield rapid response but
will not fully filter low frequency signals. Any ripple on the
gain control signal will modulate the signal passing through
the variable gain cell. In an expander or compressor
application, this would lead to third harmonic distortion, so
there is a trade−off to be made between fast attack and decay
times and distortion. For step changes in amplitude, the
change in gain with time is shown by this equation.
G(t) + (G initial * G final)
t + 10kW
*t
et
0
−10
−20
−30
−40
−50
−60
−70
−80
−40
−30 −20 −10
0
+10
COMPRESSOR OUTPUT LEVEL
OR
EXPANDOR INPUT LEVEL (dBm)
Figure 2. Basic Input−Output Transfer Curve
) G final
VCC = 15V
C RECT
0.1mF
The variable gain cell is a current−in, current−out device
with the ratio IOUT/IIN controlled by the rectifier. IIN is the
current which flows from the DG input to an internal
summing node biased at VREF. The following equation
applies for capacitively−coupled inputs. The output current,
IOUT, is fed to the summing node of the op amp.
I IN +
+10
10mF
13
6, 11
2.2mF 20kW
V1
3, 14
V IN * V REF
V
+ IN
R2
R2
20kW
DG
4
7, 10
VREF
2.2mF 10kW
V2
2, 15
A compensation scheme built into the DG cell
compensates for temperature and cancels out odd harmonic
distortion. The only distortion which remains is even
harmonics, and they exist only because of internal offset
voltages. The THD trim terminal provides a means for
nulling the internal offsets for low distortion operation.
The operational amplifier (which is internally
compensated) has the non−inverting input tied to VREF, and
the inverting input connected to the DG cell output as well
−
+
30kW
1, 16
5, 12
2.2mF
8.2kW
8, 9
200pF
Figure 3. Typical Test Circuit
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4
VO
NCY9100
INTRODUCTION
Much interest has been expressed in high performance
electronic gain control circuits. For non−critical
applications,
an
integrated
circuit
operational
transconductance amplifier can be used, but when
high−performance is required, one has to resort to complex
discrete circuitry with many expensive, well−matched
components. This paper describes an inexpensive integrated
circuit, the NCY9100 Compandor, which offers a pair of
high performance gain control circuits featuring low
distortion (<0.1%), high signal−to−noise ratio (90 dB), and
wide dynamic range (110 dB).
requires a simple full−wave averaging rectifier with good
accuracy, since the rectifier accuracy determines the (input)
output level tracking accuracy. The gain cell determines the
distortion and noise characteristics, and the phone system
specifications here are very loose. These specs could have
been met with a simple Operational Transconductance
Multiplier, or OTA, but the gain of an OTA is proportional
to temperature and this is very undesirable. Therefore, a
linearized transconductance multiplier was designed which
is insensitive to temperature and offers low noise and low
distortion performance. These features make the circuit
useful in audio and data systems as well as in
telecommunications systems.
Circuit Background
EXPANSION
INPUT
LEVEL
+20
COMPRESSION
The NCY9100 Compandor was originally designed to
satisfy the requirements of the telephone system. When
several telephone channels are multiplexed onto a common
line, the resulting signal−to−noise ratio is poor and
companding is used to allow a wider dynamic range to be
passed through the channel. Figure 4 graphically shows
what a compandor can do for the signal−to−noise ratio of a
restricted dynamic range channel. The input level range of
+20 to −80 dB is shown undergoing a 2−to−1 compression
where a 2.0 dB input level change is compressed into a
1.0 dB output level change by the compressor. The original
100 dB of dynamic range is thus compressed to a 50 dB
range for transmission through a restricted dynamic range
channel. A complementary expansion on the receiving end
restores the original signal levels and reduces the channel
noise by as much as 45 dB.
The significant circuits in a compressor or expander are
the rectifier and the gain control element. The phone system
Basic Hook−up and Operation
Figure 5 shows the block diagram of one half of the chip,
(there are two identical channels on the IC). The full−wave
averaging rectifier provides a gain control current, IG, for the
variable gain (DG) cell. The output of the DG cell is a current
which is fed to the summing node of the operational
amplifier. Resistors are provided to establish circuit gain and
set the output DC bias.
The circuit is intended for use in single power supply
systems, so the internal summing nodes must be biased at
some voltage above ground. An internal band gap voltage
reference provides a very stable, low noise 1.8 V reference
denoted VREF. The non−inverting input of the op amp is tied
to VREF, and the summing nodes of the rectifier and DG cell
(located at the right of R1 and R2) have the same potential.
The THD trim pin is also at the VREF potential.
THD TRIM
8,9
R3
OUTPUT
LEVEL
−20
GIN
0dB
0dB
−40
−40
R2
3,14
20kW
RECTIN
R1
2,15 10kW
NOISE
−80
R3
−80
INVIN
6,11
5,12
20kW
DG
−
IG
R4
VREF
30kW
1.8V
1,16
+
OUTPUT
7,10
VCC PIN 13
GND PIN 4
CRECT
Figure 4. Restricted Dynamic Range Channel
Figure 5. Chip Block Diagram (1 of 2 Channels)
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5
NCY9100
Figure 6 shows how the circuit is hooked up to realize an
expandor. The input signal, VIN, is applied to the inputs of
both the rectifier and the DG cell. When the input signal
drops by 6.0 dB, the gain control current will drop by a factor
of 2, and so the gain will drop 6.0 dB. The output level at
VOUT will thus drop 12 dB, giving us the desired 2−to−1
expansion.
R1
R2
DG
VOUT
+
R4
R4 VREF
NOTE: GAIN +
+
ǒ
R1 R2 IB
2R 3 V INavg
Ǔ
1
2
IB = 140mA
VREF
R1
VOUT
−
−
VIN
*CIN2
CDC *
CIN * R
3
VIN
CF*
CRECT *
RDC *
RDC *
R3
*CIN1
R2
DG
*EXTERNAL COMPONENTS
Figure 7. Basic Compressor
*CRECT
Circuit Details − Rectifier
NOTE:
ǒ
GAIN +
IB = 140mA
Figure 8 shows the concept behind the full−wave
averaging rectifier. The input current to the summing node
of the op amp, VIN/R1, is supplied by the output of the op
amp. If we can mirror the op amp output current into a
unipolar current, we will have an ideal rectifier. The output
current is averaged by R5, CR, which set the averaging time
constant, and then mirrored with a gain of 2 to become IG,
the gain control current.
Ǔ
2 R 3 V IN (avg) 2
R1 R2 IB
*EXTERNAL COMPONENTS
Figure 6. Basic Expander
Figure 7 shows the hook−up for a compressor. This is
essentially an expandor placed in the feedback loop of the op
amp. The DG cell is setup to provide AC feedback only, so
a separate DC feedback loop is provided by the two RDC and
CDC. The values of RDC will determine the DC bias at the
output of the op amp. The output will bias to:
V OUT DC +
ǒ
I = VIN / R1
R1
Ǔ
VIN
) R DC2
R
1 ) DC1
V REF
R4
ǒ
V OUT DC + 1 )
R DCTOT
30kW
−
+
CR
Ǔ 1.8V
V+
R5
10kW
The output of the expander will bias up to:
V OUT DC +
ǒ
ǒ 1 ) RR Ǔ V
3
4
REF
Figure 8. Rectifier Concept
Ǔ
V OUT DC + 1 ) 20kW 1.8V + 3.0V
30kW
The output will bias to 3.0 V when the internal resistors are
used. External resistors may be placed in series with R3,
(which will affect the gain), or in parallel with R4 to raise the
DC bias to any desired value.
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6
IG
NCY9100
Figure 9 shows the rectifier circuit in more detail. The op
amp is a one−stage op amp, biased so that only one output
device is on at a time. The non−inverting input, (the base of
Q1), which is shown grounded, is actually tied to the internal
1.8 V, VREF. The inverting input is tied to the op amp output,
(the emitters of Q5 and Q6), and the input summing resistor
R1. The single diode between the bases of Q5 and Q6 assures
that only one device is on at a time. To detect the output
current of the op amp, we simply use the collector currents
of the output devices Q5 and Q6. Q6 will conduct when the
input swings positive and Q5 conducts when the input
swings negative. The collector currents will be in error by
the a of Q5 or Q6 on negative or positive signal swings,
respectively. ICs such as this have typical NPN b’s of 200
and PNP b’s of 40. The a’s of 0.995 and 0.975 will produce
errors of 0.5% on negative swings and 2.5% on positive
swings. The 1.5% average of these errors yields a mere 0.13
dB gain error.
the error of the input bias current. For highest accuracy, the
rectifier should be coupled capacitively. At high input levels
the b of the PNP Q6 will begin to suffer, and there will be an
increasing error until the circuit saturates. Saturation can be
avoided by limiting the current into the rectifier input to
250 mA. If necessary, an external resistor may be placed in
series with R1 to limit the current to this value. Figure 10
shows the rectifier accuracy vs. input level at a frequency of
1.0 kHz.
ERROR GAIN dB
+1
0
−1
V+
Figure 10. Rectifier Accuracy
Q3
Q7
At very high frequencies, the response of the rectifier will
fall off. The roll−off will be more pronounced at lower input
levels due to the increasing amount of gain required to
switch between Q5 or Q6 conducting. The rectifier
frequency response for input levels of 0 dBm, −20 dBm, and
−40 dBm is shown in Figure 11. The response at all three
levels is flat to well above the audio range.
Q4
Q5
Q1 Q2
D1
R1
10kW
VIN
RS
10kW
Q6
I1
−40
−20
0
RECTIFIER INPUT dBm
Q8
I2
Q9
GAIN ERROR (dB)
CR
V−
NOTE: I G + 2
V IN avg
R1
Figure 9. Simplified Rectifier Schematic
At very low input signal levels the bias current of Q2,
(typically 50 nA), will become significant as it must be
supplied by Q5. Another low level error can be caused by DC
coupling into the rectifier. If an offset voltage exists between
the VIN input pin and the base of Q2, an error current of
VOS/R1 will be generated. A mere 1.0 mV of offset will
cause an input current of 100 nA which will produce twice
INPUT = 0dBm
0
3
−20dBm
−40dBm
10k
1MEG
FREQUENCY (Hz)
Figure 11. Rectifier Frequency Response vs.
Input Level
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NCY9100
Variable Gain Cell
This equation is linear and temperature−insensitive, but it
assumes ideal transistors.
If the transistors are not perfectly matched, a parabolic,
non−linearity is generated, which results in second
harmonic distortion. Figure 13 gives an indication of the
magnitude of the distortion caused by a given input level and
offset voltage. The distortion is linearly proportional to the
magnitude of the offset and the input level. Saturation of the
gain cell occurs at a +8 dBm level. At a nominal operating
level of 0 dBm, a 1.0 mV offset will yield 0.34% of second
harmonic distortion. Most circuits are somewhat better than
this, which means our overall offsets are typically about mV.
The distortion is not affected by the magnitude of the gain
control current, and it does not increase as the gain is
changed. This second harmonic distortion could be
eliminated by making perfect transistors, but since that
would be difficult, we have had to resort to other methods.
A trim pin has been provided to allow trimming of the
internal offsets to zero, which effectively eliminated second
harmonic distortion. Figure 14 shows the simple trim
network required.
Figure 12 is a diagram of the variable gain cell. This is a
linearized two−quadrant transconductance multiplier. Q1,
Q2 and the op amp provide a predistorted drive signal for the
gain control pair, Q3 and Q4. The gain is controlled by IG and
a current mirror provides the output current.
V+
I1
140mA
−
+
R2
20k
VIN
Q1
Q2
Q4
Q3
IIN
I2 (= 2I1)
280mA
IG
V−
3
% THD
NOTE: I OUT
4
I
I V
+ G I IN + G IN
I1
I2 R2
Figure 12. Simplified DG Cell Schematic
The op amp maintains the base and collector of Q1 at
ground potential (VREF) by controlling the base of Q2. The
input current IIN (= VIN/R2) is thus forced to flow through
Q1 along with the current I1, so IC1 = I1 + IIN. Since I2 has
been set at twice the value of I1, the current through Q2 is:
3mV
2
2mV
1
1mV
.34
−6
0
+6
INPUT LEVEL (dBm)
Figure 13. DG Cell Distortion vs. Offset Voltage
I2 − (I1 + IIN) = I1 − IIN = IC2.
The op amp has thus forced a linear current swing between
Q1 and Q2 by providing the proper drive to the base of Q2.
This drive signal will be linear for small signals, but very
non−linear for large signals, since it is compensating for the
non−linearity of the differential pair, Q1 and Q2, under large
signal conditions.
The key to the circuit is that this same predistorted drive
signal is applied to the gain control pair, Q3 and Q4. When
two differential pairs of transistors have the same signal
applied, their collector current ratios will be identical
regardless of the magnitude of the currents. This gives us:
VCC
R
3.6V
6.2kW
To THD Trim
20kW
≈200pF
I C1
I
I ) I IN
+ C4 + 1
I C2
I C3
I 1 * I IN
Figure 14. THD Trim Network
plus the relationships IG = IC3 + IC4 and IOUT = IC4 − IC3 will
yield the multiplier transfer function,
I OUT +
4mV
IG
V I
I + IN G
I 1 IN
R2 I1
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8
NCY9100
Figure 15 shows the noise performance of the DG cell.
The maximum output level before clipping occurs in the
gain cell is plotted along with the output noise in a 20 kHz
bandwidth. Note that the noise drops as the gain is reduced
for the first 20 dB of gain reduction. At high gains, the signal
to noise ratio is 90 dB, and the total dynamic range from
maximum signal to minimum noise is 110 dB.
VCC
R−SELECT FOR
3.6V
TO PIN 3 OR 14
100kW
470kW
+20
OUTPUT (dBm)
0
Figure 16. Control Signal Feedthrough
MAXIMUM
SIGNAL LEVEL
−20
90dB
110dB
−40
Operation Amplifier
The main op amp shown in the chip block diagram is
equivalent to a 741 with a 1.0 MHz bandwidth. Figure 17
shows the basic circuit. Split collectors are used in the input
pair to reduce gM, so that a small compensation capacitor of
just 10 pF may be used. The output stage, although capable
of output currents in excess of 20 mA, is biased for a low
quiescent current to conserve power. When driving heavy
loads, this leads to a small amount of crossover distortion.
−60
−80
−100
−40
NOISE IN
20kHz BW
−20
0
VCA GAIN (0dB)
Figure 15. Dynamic Range
I2
I1
Control signal feedthrough is generated in the gain cell by
imperfect device matching and mismatches in the current
sources, I1 and I2. When no input signal is present, changing
IG will cause a small output signal. The distortion trim is
effective in nulling out any control signal feedthrough, but
in general, the null for minimum feedthrough will be
different than the null in distortion. The control signal
feedthrough can be trimmed independently of distortion by
tying a current source to the DG input pin. This effectively
trims I1. Figure 16 shows such a trim network.
−IN
Q1
Q2
+IN
CC
D1
D2
Q6
OUT
Q2
Q3
Q4
Figure 17. Operational Amplifier
ORDERING INFORMATION
Device
NCY9100DWR2G
Description
Temperature Range
Shipping†
SO−16 WB Package
(Pb−Free)
−40 to +85°C
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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9
NCY9100
PACKAGE DIMENSIONS5
SOIC−16 WB
D SUFFIX
CASE 751G−03
ISSUE C
A
D
9
h X 45 _
E
M
0.25
8X
H
B
M
16
q
1
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
MILLIMETERS
DIM MIN
MAX
A
2.35
2.65
A1 0.10
0.25
B
0.35
0.49
C
0.23
0.32
D 10.15 10.45
E
7.40
7.60
e
1.27 BSC
H 10.05 10.55
h
0.25
0.75
L
0.50
0.90
q
0_
7_
8
16X
M
T A
S
B
S
14X
e
A1
L
A
0.25
B
B
SEATING
PLANE
T
C
ON Semiconductor and
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ON Semiconductor Website: www.onsemi.com
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NCY9100/D