TI1 LMH3401IRMST Lmh3401 7-ghz, ultra-wideband, fixed-gain, fully-differential amplifier Datasheet

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LMH3401
SBOS695A – AUGUST 2014 – REVISED DECEMBER 2014
LMH3401 7-GHz, Ultra-Wideband, Fixed-Gain, Fully-Differential Amplifier
1 Features
3 Description
•
The LMH3401 is a very high-performance, differential
amplifier optimized for radio frequency (RF),
intermediate frequency (IF), or high-speed, timedomain applications. This device is ideal for dc- or accoupled applications that require a single-ended to
differential conversion when driving an analog-todigital converter (ADC). The LMH3401 generates
very low levels of second-order and third-order
distortion when operating in single-ended-input to
differential-output or differential-input to differentialoutput mode.
1
•
•
•
•
•
•
•
•
•
Excellent Single-Ended to Differential Conversion
Performance from DC to 2 GHz
7-GHz, –3-dB Bandwidth
Excellent HD2 and HD3 to 2 GHz:
– –96 (HD2), –102 (HD3) at 10 MHz
– –79 (HD2), –77 (HD3) at 500 MHz
– –64 (HD2), –72 (HD3) at 1 GHz
– –55 (HD2), –40 (HD3) at 2 GHz
Best in Class OIP3 Performance to 2 GHz:
– 45 dBm at 200 MHz
– 33 dBm at 1 GHz
– 24 dBm at 2 GHz
Fixed Single-Ended to Differential Voltage Gain:
16 dB
Noise Figure: 9 dB at 200 MHz (RS = 50 Ω)
Slew Rate: 18,000 V/µs
Supports Single-Supply or Split-Supply Operation
Powered-Down Feature
Supply Current: 55 mA
2 Applications
•
•
•
•
•
•
•
GSPS ADC Drivers
ADC Drivers for High-Speed Data Acquisition
ADC Driver for 1-GBPS Ethernet over Microwave
DAC Buffers
Wideband Gain Stages
Single-Ended to Differential Conversions
Level Shifters
The on-chip resistors simplify printed circuit board
(PCB) implementation and provide the highest
performance over the usable bandwidth of 2 GHz.
This performance makes the LMH3401 ideal for
applications such as test and measurement,
broadband communications, and high-speed data
acquisition. A common-mode reference input pin is
provided to align the amplifier output common-mode
with the ADC input requirements. Use this device with
power supplies between 3.3 V and 5.0 V; dual-supply
operation is supported when required by the
application.
This level of performance is achieved at a very low
power level of 275 mW when a 5.0-V supply is used.
A power-down feature is also available for power
savings. The LMH3401 is fabricated in Texas
Instruments' advanced complementary BiCMOS
process and is available in a space-saving, 14-lead
UQFN package with a specified operating
temperature range of –40°C to 85°C.
Device Information(1)
PART NUMBER
LMH3401
PACKAGE
BODY SIZE (NOM)
UQFN (14)
2.50 mm × 2.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
LMH3401 Driving an ADC12J4000
Distortion Products vs Frequency
0
200 W
±20
12.5 W
10 W
VOUT+
RO
AIN+
VIN
VCM
12.5 W
50 W
200 W
ADC
Filter
10 W
VOUT-
AINRO
CM
Distortion (dBc)
Single-Ended,
50-W Source
±40
±60
±80
LMH3401
±100
CM
HD2
HD3
±120
1
10
100
Frequency (MHz)
1000
C002
RL = 200 Ω, VOUT = 2 VPP
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH3401
SBOS695A – AUGUST 2014 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
4
4
5
7
9
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: VS = 5 V...........................
Electrical Characteristics: VS = 3.3 V........................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 17
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
Output Reference Points......................................... 17
ATE Testing and DC Measurements ...................... 17
Frequency Response .............................................. 17
S-Parameters .......................................................... 17
Frequency Response with Capacitive Load............ 17
Distortion ................................................................. 18
Noise Figure............................................................ 18
Pulse Response, Slew Rate, Overdrive Recovery . 18
Power Down............................................................ 18
VCM Frequency Response .................................... 18
8.11 Test Schematics.................................................... 19
9
Detailed Description ............................................ 21
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
21
21
21
26
10 Application and Implementation........................ 27
10.1 Application Information.......................................... 27
10.2 Typical Application ................................................ 29
10.3 Do's and Don'ts .................................................... 37
11 Power-Supply Recommendations ..................... 38
11.1
11.2
11.3
11.4
Supply Voltage ......................................................
Single Supply ........................................................
Split Supply ...........................................................
Supply Decoupling ................................................
38
38
38
38
12 Layout................................................................... 39
12.1 Layout Guidelines ................................................. 39
12.2 Layout Example .................................................... 40
13 Device and Documentation Support ................. 42
13.1
13.2
13.3
13.4
13.5
Device Support......................................................
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
42
42
42
42
42
14 Mechanical, Packaging, and Orderable
Information ........................................................... 42
4 Revision History
Changes from Original (August 2014) to Revision A
Page
•
Changed value of Supply Current bullet in Features ............................................................................................................. 1
•
Changed VOUT value in front-page curve ............................................................................................................................... 1
•
Changed LMH5401 row in Device Comparison Table ........................................................................................................... 3
•
Updated ESD Ratings table to current standards ................................................................................................................. 4
•
Changed Supply voltage parameter minimum specification in Recommended Operating Conditions table ......................... 4
•
Changed test conditions of Output, Output voltage range high parameter from Output voltage range low to TA =
–40°C to 85°C......................................................................................................................................................................... 6
•
Changed Power Down, Enable or disable voltage threshold parameter minimum specification in 5-V Electrical
Characteristics table ............................................................................................................................................................... 6
•
Changed conditions of Figure 41 from differential input to single-ended input ................................................................... 15
2
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SBOS695A – AUGUST 2014 – REVISED DECEMBER 2014
5 Device Comparison Table
DEVICE
BW (AV = 12 dB)
DISTORTION
NOISE
LMH5401
6.2 GHz
–80-dBc HD2, –77-dBc HD3 at 500 MHz
1.25 nV/√Hz
LMH6554
1.6 GHz
–79-dBc HD2, –70-dBc HD3 at 250 MHz
0.9 nV/√Hz
LMH6552
0.8 GHz
–74-dBc HD2, –84-dBc HD3 at 70 MHz
1.1 nV /√Hz
6 Pin Configuration and Functions
NC
4
IN-
5
CM
2
VS+
1
VS3
RMS Package
UQFN-14
(Top View)
14
GND
13
OUT+
LMH3401
IN+
6
12
OUT-
NC
7
11
GND
9
PD
10
8
VS-
VS+
Pin Functions
PIN
NAME
NO.
I/O
CM
2
I
Output common-mode voltage control input pin
DESCRIPTION
GND
11, 14
P
Ground. This ground does not impact the signal path, this pin is the reference for the
digital input pin (PD).
IN–
5
I
Inverting input pin
IN+
6
I
Noninverting input pin
NC
4, 7
—
No internal connection
OUT–
12
O
Inverting output pin
OUT+
13
O
Noninverting output pin
PD
9
I
Power down.
High (> GND + 1.2 V) = low-power (sleep) mode. Low (< GND + 0.9 V) = active.
VS–
3, 8
P
Power-supply pins, negative rail
VS+
1, 10
P
Power-supply pins, positive rail
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SBOS695A – AUGUST 2014 – REVISED DECEMBER 2014
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Power supply
Voltage
Input voltage range
Current
VS– – 0.7
(1)
UNIT
5.5
V
VS+ + 0.7
V
Input current, IN+, IN–
10
mA
Output current (sourcing or sinking) OUT+, OUT–
100
mA
Continuous power dissipation
Temperature
MAX
See Thermal Information
Maximum junction temperature, TJ
150
°C
Maximum junction temperature, continuous operation, long-term
reliability
125
°C
Operating free-air, TA
–40
85
°C
Storage, Tstg
–40
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
Electrostatic
discharge
V(ESD)
(1)
(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
Supply voltage (VS = VS+ – VS–)
3.15
5
5.25
V
Operating junction temperature, TJ
–40
125
°C
Ambient operating air temperature, TA
–40
85
°C
25
UNIT
7.4 Thermal Information
LMH3401
THERMAL METRIC
(1)
RMS (UQFN)
UNIT
14 PINS
RθJA
Junction-to-ambient thermal resistance
101
RθJC(top)
Junction-to-case (top) thermal resistance
51
RθJB
Junction-to-board thermal resistance
61
ψJT
Junction-to-top characterization parameter
4.2
ψJB
Junction-to-board characterization parameter
61
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
(1)
4
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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SBOS695A – AUGUST 2014 – REVISED DECEMBER 2014
7.5 Electrical Characteristics: VS = 5 V
Test conditions are at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VCM = 0 V, RL = 200-Ω differential, G = 16 dB, single-ended
input and differential output, and input and output referenced to midsupply, unless otherwise noted. Measured using an
evaluation module (EVM) as discussed in the section.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
AC PERFORMANCE
(2)
Small-signal bandwidth
VO = 200 mVPP
7
GHz
C
Large-signal bandwidth
VO = 2 VPP
4
GHz
C
Bandwidth for 0.1-dB flatness
VO = 2 VPP
700
MHz
C
Slew rate
VO = 2-V step
18000
V/µs
C
Rise time
VO = 1-V step
80
ps
C
Fall time
VO = 1-V step
80
ps
C
Settling time to 1%
VO = 2-V step
1
ns
C
Input return loss, s11
See S-Parameters section, f < 1 GHz
–20
dB
C
Output return loss, s22
See S-Parameters section, f < 1 GHz
–20
dB
C
Reverse isolation, s12
See S-Parameters section, f < 1 GHz
–65
dB
C
f = 10 MHz, VO = 2 VPP
–96
dBc
C
f = 500 MHz, VO = 2 VPP
–79
dBc
C
f = 1 GHz, VO = 2 VPP
–64
dBc
C
f = 2 GHz, VO = 2 VPP
–55
dBc
C
f = 10 MHz, VO = 2 VPP
–102
dBc
C
f = 500 MHz, VO = 2 VPP
–77
dBc
C
f = 1 GHz, VO = 2 VPP
–72
dBc
C
f = 2 GHz, VO = 2 VPP
–40
dBc
C
f = 10 MHz, VO = 1 VPP per tone
–90
dBc
C
f = 500 MHz, VO = 1 VPP per tone
–77
dBc
C
f = 1 GHz, VO = 1 VPP per tone
–71
dBc
C
f = 2 GHz, VO = 1 VPP per tone
–56
dBc
C
f = 10 MHz, VO = 1 VPP per tone
–101
dBc
C
f = 500 MHz, VO = 1 VPP per tone
–86
dBc
C
f = 1 GHz, VO = 1 VPP per tone
–73
dBc
C
f = 2 GHz, VO = 1 VPP per tone
–52
dBc
C
f = 200 MHz, power measured at amplifier
13
dBm
C
At device outputs, f = 200 MHz
45
dBm
C
At device outputs, f = 1000 MHz
33
dBm
C
f > 1 MHz
1.4
nV/√Hz
C
9
dB
C
9.4
dB
C
300
ps
C
45
dBc
C
Ω
A
Second-order harmonic distortion
Third-order harmonic distortion
Second-order intermodulation distortion
Third-order intermodulation distortion
1-dB compression point
Output third-order intercept point
Input-referred voltage noise
f = 200 MHz
Noise figure
50-Ω, singleended source
Overdrive recovery
Overdrive = ±0.5 V
Output balance error
f = 1000 MHz
Output impedance
At dc
(1)
(2)
f = 1 GHz
16
20
24
Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
All output voltages are specified as differential voltages unless otherwise noted. Output differential voltage is defined as VO = (VO+ –
VO–).
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Electrical Characteristics: VS = 5 V (continued)
Test conditions are at TA = 25°C, VS+ = 2.5 V, VS– = –2.5 V, VCM = 0 V, RL = 200-Ω differential, G = 16 dB, single-ended
input and differential output, and input and output referenced to midsupply, unless otherwise noted. Measured using an
evaluation module (EVM) as discussed in the section.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
15.4
16
16.6
dB
A
dB
C
±20
mV
A
DC PERFORMANCE
50-Ω single-ended source, with external 50-Ω
termination
Gain
Differential output offset
100-Ω differential source, external termination
12
TA = 25°C
±2
TA = –40°C to 85°C
±4
mV
C
4
µV/°C
C
TA = 25°C
72
dBc
C
Differential output offset temperature drift
Common-mode rejection ratio
INPUT
Differential input resistance
Single ended input resistance
With external 50-Ω resistor on INN to ground
Input common-mode range low
Inputs shorted together, VCM = 2.5 V
Input common-mode range high
Inputs shorted together, VCM = 2.5 V
22
25
29
Ω
A
45
50
55
Ω
A
VS– – 0.7
VS– + 0.2
V
A
A
VS+ – 1.3
VS+ – 1.2
V
VS+ – 1.3
VS+ – 1.1
V
A
VS+ – 1.2
V
C
VS– + 1.1
V
A
VS– + 1.2
V
C
5.6
VPP
C
50
mA
A
OUTPUT
Output voltage range high
Measured
single-ended
TA = 25°C
Output voltage range low
Measured
single-ended
TA = 25°C
TA = –40°C to 85°C
VS– + 1.3
TA = –40°C to 85°C
Differential output voltage
Differential output current drive
VO = 0 V
40
OUTPUT COMMON-MODE VOLTAGE CONTROL
VCM small-signal bandwidth
VOUT_CM = 200 mVPP
3.3
GHz
C
VCM slew rate
VOUT_CM = 500 mVPP
2900
V/µs
C
VCM voltage range low
Differential gain shift < 1 dB
V
A
VCM voltage range high
Differential gain shift < 1 dB
V
A
VCM gain
VCM = 0 V
V/V
A
VOUT_CM output common-mode offset
from VCM input voltage (3)
VCM = 0 V
mV
C
µV/°C
C
VS– + 1.6
VS+ – 2.0
VS+ – 1.6
0.98
1.0
VS– + 2.0
1.01
–27
VCM temperature drift
–13.6
POWER SUPPLY
Quiescent current
Power-supply rejection ratio
TA = 25°C
50
55
mA
A
VS+
60
84
62
dB
A
VS–
50
75
dB
A
Device powers on below 0.8 V,
device powers down above 1.2 V
0.9
1.1
V
A
POWER DOWN
Enable or disable voltage threshold
Power-down quiescent current
3
6
mA
A
PD bias current
PD = 2.5 V
10
±100
µA
C
Turn-on time delay
Time to VO = 90% of final value
10
ns
C
Turn-off time delay
Time to VO = 10% of original value
10
ns
C
(3)
6
1
1.2
VOUT_CM = (OUT+ + OUT–) / 2 and is set by the CM pin VOUT_CM ≈ VCM.
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7.6 Electrical Characteristics: VS = 3.3 V
Test conditions are at TA = 25°C, VS+ = 1.65 V, VS– = –1.65 V, VCM = 0 V, RL = 200-Ω differential, G = 16 dB, single-ended
input and differential output, and input and output referenced to midsupply, unless otherwise noted. Measured using an EVM
as discussed in the section.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
AC PERFORMANCE
Small-signal bandwidth
VO = 200 mVPP
6.5
GHz
C
Large-signal bandwidth
VO = 1 VPP
4
GHz
C
Bandwidth for 0.1-dB flatness
VO = 1 VPP
700
MHz
C
Slew rate
VO = 1-V step
17600
V/µs
C
Rise time
VO = 1-V step
90
ps
C
Fall time
VO = 1-V step
90
ps
C
Input return loss, s11
See S-Parameters section, f < 1 GHz
–20
dB
C
Output return loss, s22
See S-Parameters section, f < 1 GHz
–20
dB
C
Reverse isolation, s12
See S-Parameters section, f < 1 GHz
–65
dB
C
f = 10 MHz, VO = 1 VPP
–97
dBc
C
f = 500 MHz, VO = 1 VPP
–74
dBc
C
f = 1 GHz, VO = 1 VPP
–59
dBc
C
f = 2 GHz, VO = 1 VPP
–48
dBc
C
f = 10 MHz, VO = 1 VPP
–100
dBc
C
f = 500 MHz, VO = 1 VPP
–66
dBc
C
f = 1 GHz, VO = 1 VPP
–56
dBc
C
f = 2 GHz, VO = 1 VPP
–49
dBc
C
f = 10 MHz, VO = 0.5 VPP per tone
–95
dBc
C
f = 500 MHz, VO = 0.5 VPP per tone
–81
dBc
C
f = 1 GHz, VO = 0.5 VPP per tone
–72
dBc
C
f = 2 GHz, VO = 0.5 VPP per tone
–60
dBc
C
f = 10 MHz, VO = 0.5 VPP per tone
–100
dBc
C
f = 500 MHz, VO = 0.5 VPP per tone
–86
dBc
C
f = 1 GHz, VO = 0.5 VPP per tone
–78
dBc
C
f = 2 GHz, VO = 0.5 VPP per tone
–56
dBc
C
At device outputs, f = 10 MHz
39.5
dBm
C
At device outputs, f = 1000 MHz
31
dBm
C
Input-referred voltage noise
f > 1 MHz
1.4
nV/√Hz
C
Noise figure
50-Ω, singleended source
9
dB
C
9.4
dB
C
Overdrive recovery
Overdrive = ±0.5 V
400
ps
C
Output impedance
f = 100 MHz
Ω
A
Second-order harmonic distortion
Third-order harmonic distortion
Second-order intermodulation distortion
Third-order intermodulation distortion
Output third-order intercept point
(1)
f = 200 MHz
f = 1 GHz
16
20
24
Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
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Electrical Characteristics: VS = 3.3 V (continued)
Test conditions are at TA = 25°C, VS+ = 1.65 V, VS– = –1.65 V, VCM = 0 V, RL = 200-Ω differential, G = 16 dB, single-ended
input and differential output, and input and output referenced to midsupply, unless otherwise noted. Measured using an EVM
as discussed in the section.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
15.4
16
16.6
dB
A
dB
C
±20
mV
A
DC PERFORMANCE
50-Ω, single-ended source with external 50-Ω
termination
Gain
100-Ω differential source, external termination
12
TA = 25°C
±2
TA = –40°C to 85°C
±4
mV
C
Differential output voltage drift
3.6
µV/°C
C
Common-mode rejection ratio
–72
dB
A
Differential output offset voltage
INPUT
Differential input resistance
Single-ended input resistance
With external 50-Ω resistor on INN to ground
Input common-mode range low
Inputs shorted together
Input common-mode range high
Inputs shorted together
22
25
29
Ω
A
45
50
55
Ω
A
VS– – 0.3
VS– + 0.2
V
A
A
VS+ – 1.5
VS+ –1.6
V
VS+ – 1.2
VS+ – 0.95
V
A
VS+ – 1.05
V
C
VS– + 0.95
V
A
VS– + 1.05
V
C
2.8
VPP
C
40
mA
A
OUTPUT
Output voltage range high
Measured
single-ended
TA = 25°C
Output voltage range low
Measured
single-ended
TA = 25°C
TA = –40°C to 85°C
VS– + 1.2
TA = –40°C to 85°C
Differential output voltage
Differential output current drive
VO = 0 V
30
OUTPUT COMMON-MODE VOLTAGE CONTROL
VCM small-signal bandwidth
VOUT_CM = 200 mVPP
3
GHz
C
VCM slew rate
VOUT_CM = 500 mVPP
2600
V/µs
C
V
A
V
A
V/V
A
mV
C
µV/°C
C
VCM voltage range low
Differential gain shift < 1 dB
VCM voltage range high
Differential gain shift < 1 dB
VCM gain
VCM = 0 V
Output common-mode offset
from VCM input
VCM = 0 V
VS– + 1.35
VS+ –
1.55
VS+ – 1.35
0.98
1.0
VS– +
1.55
1.01
–7
Common-mode voltage drift
–34.6
POWER SUPPLY
Quiescent current
Power-supply rejection ratio
TA = 25°C
49
54
mA
A
VS+
60
84
60
dB
A
VS–
50
75
dB
A
Device powers on below 0.8 V,
device powers down above 1.2 V
1.0
1.1
V
A
1
POWER-DOWN
Enable or disable voltage threshold
Power-down quiescent current
1.2
1.6
5
mA
A
PD bias current
PD = 2.5 V
10
±100
µA
C
Turn-on time delay
Time to VO = 90% of final value
10
ns
C
Turn-off time delay
Time to VO = 10% of original value
10
ns
C
8
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7.7 Typical Characteristics
5
5
0
0
Normalized Gain (dB)
Normalized Gain (dB)
At TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (ROUT = 40 Ω each), G = 16 dB, single-ended input and
differential output, and input and output pins referenced to midsupply, unless otherwise noted. Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 49 to Figure 53).
-5
-10
-15
±5
±10
±15
±20
-20
±25
3.3Vs
5Vs
Sds21
-25
10
100
1000
±30
10000
Frequency (MHz)
10
VS = ±2.5 V, VOUT_AMP = 0.4 VPP
10000
C001
External 37.5-Ω input matching resistors, VOUT_AMP = 0.4 VPP,
gain = 12 dB, see Figure 57, VS = ±1.65 V and ±2.5 V
Figure 2. Frequency Response Differential Input
5
5
0
0
Normalized Gain (dB)
Normalized Gain (dB)
1000
Frequench (MHz)
Figure 1. Frequency Response Single-Ended Input
±5
±10
±15
±5
±10
±15
±20
±20
Sdd21
10
100
3.3V
5V
±25
±25
1000
10
10000
100
1000
10000
Frequency (MHz)
Frequency (MHz)
C001
C001
Single-ended input, VOUT_AMP = 1 VPP
No input matching resistors, VOUT_AMP = 0.2 VPP,
net gain = 14 dB, VS = ±2.5 V
Figure 4. 1-VPP Frequency Response vs Supply Voltage
Figure 3. Frequency Response Differential Input
5
4
2
Normalized Gain (dB)
0
Normalized Gain (dB)
100
C003
-5
-10
-15
-20
0
±2
±4
±6
-40 °C
25 °C
85 °C
±8
±10
6GV«
-25
±12
10
100
1000
10000
Frequency (MHz)
10
100
1000
10000
Frequency (MHz)
C003
VS = ±2.5 V, VOUT_AMP = 4 VPP
C003
VS = ±2.5 V, VOUT_AMP = 1 VPP
Figure 5. Large-Signal Frequency Response
(Single-Ended Input)
Figure 6. Frequency Response vs Temperature
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Typical Characteristics (continued)
5
5
0
0
Normalized Gain (dB)
Normalized Gain (dB)
At TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (ROUT = 40 Ω each), G = 16 dB, single-ended input and
differential output, and input and output pins referenced to midsupply, unless otherwise noted. Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 49 to Figure 53).
±5
±10
±15
0pF
1pF
2.2pF
4.7pF
10pF
±20
±25
±10
±15
0pF
1pF
2.2pF
4.7pF
10pF
±20
±25
±30
1
±5
10
100
±30
1000
1
Frequency (MHz)
C001
Figure 7. Frequency Response with Capacitive Load
Figure 8. Frequency Response with Capacitive Load
20
20
10
10
0
sss11
ssd12
sds21
sdd22
±10
±20
±30
Sparameter s (dB)
S Parameters (dB)
1000
VS = ±1.65 V, VOUT_AMP = 1 VPP,
capacitance at DUT output pins
0
±40
±50
±60
sss11
ssd12
sds21
sdd22
±10
±20
±30
±40
±50
±60
±70
±70
±80
±80
±90
±90
1
100
10000
Frequency (MHz)
1
100
1000
10000
C007
VS = ±1.65 V, VOUT_AMP = 200 mVPP
Figure 9. S-Parameters (±2.5-V Supply)
Figure 10. S-Parameters (3.3-V Supply)
5
0
0
Common Mode Gain (dB)
5
±5
±10
±15
±5
±10
±15
Cm_SSBW
Cm_SSBW
±20
10
10
Frequency (MHz)
C006
VS = ±2.5 V, VOUT_AMP = 200 mVPP
Common Mode Gain (dB)
100
Frequency (MHz)
VS = ±2.5 V, VOUT_AMP = 1 VPP,
capacitance at DUT output pins
100
1000
10000
Frequency (MHz)
±20
10
100
1000
10000
Frequency (MHz)
C004
VS = ±2.5 V, VOUT_AMP = 100 mVPP
C005
VS = ±1.65 V, VOUT_AMP = 100 mVPP
Figure 11. Common-Mode Frequency Response
10
10
C001
Figure 12. Common-Mode Frequency Response
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Typical Characteristics (continued)
At TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (ROUT = 40 Ω each), G = 16 dB, single-ended input and
differential output, and input and output pins referenced to midsupply, unless otherwise noted. Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 49 to Figure 53).
0
±20
HD2
HD3
±30
±20
Distortion (dBc)
Distortion (dBc)
±40
±40
±60
±80
±50
±60
±70
±80
±100
±90
HD2
HD3
±120
1
10
100
±100
10
1000
Frequency (MHz)
100
1000
Frequency (MHz)
C002
C001
VS = ±2.5 V, VOUT_AMP = 2 VPP, RLOAD = 100 Ω
VS = ±2.5 V, VOUT_AMP = 2 VPP
Figure 13. HD2 and HD3 (±2.5-V Supply)
Figure 14. HD2 and HD3 (±2.5-V Supply, 100-Ω Load)
0
0
HD2
HD3
±10
±20
Distortion (dBc)
Distortion (dBc)
±20
±30
±40
±50
±40
±60
±80
±60
±100
±70
±80
HD2
HD3
±120
±50
0
50
1
100
Temperature (ƒC)
100
1000
Frequency (MHz)
VS = ±2.5 V, VOUT_AMP = 2 VPP, f = 1 GHz
C003
VS = ±1.65 V, VOUT_AMP = 1 VPP
Figure 15. HD2 and HD3 vs Temperature
Figure 16. HD2 and HD3 (3.3-V VS)
0
0
HD2
HD3
±10
±10
±20
±20
Distortion (dBc)
Distortion (dBc)
10
C001
±30
±40
±50
±30
±40
±50
±60
±70
±80
±60
±90
±70
HD2
HD3
±100
±50
0
50
100
Temperature (ƒC)
±2
VS = ±1.65 V, VOUT_AMP = 1 VPP, f = 1 GHz
Figure 17. HD2 and HD3 vs Temperature
±1
0
1
Output Common Mode Voltage (V)
C002
2
C001
VS = ±2.5 V, f = 200 MHz, VOUT_AMP = 2 VPP
Figure 18. HD2 and HD3 vs Output Common-Mode Voltage
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Typical Characteristics (continued)
At TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (ROUT = 40 Ω each), G = 16 dB, single-ended input and
differential output, and input and output pins referenced to midsupply, unless otherwise noted. Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 49 to Figure 53).
0
0
±10
±10
±20
±20
Distortion (dBc)
Distortion (dBc)
±30
±40
±50
±60
±70
±90
±100
±1.0
0.0
±0.5
0.5
HD2
HD3
±80
1.0
±2
0
±1
1
2
Output Common Mode Voltage (V)
C002
VS = ±1.65 V, f = 200 MHz, VOUT_AMP = 1 VPP
C003
VS = ±2.5 V, f = 1000 MHz, VOUT_AMP = 2 VPP
Figure 19. HD2 and HD3 vs Output Common-Mode Voltage
Figure 20. HD2 and HD3 vs Output Common-Mode Voltage
0
±20
±10
±30
HD2
HD3
±40
±20
Distortion (dBc)
Distortion (dBc)
±50
±70
HD2
HD3
Output Common Mode Voltage (V)
±30
±40
±50
±50
±60
±70
±80
±60
±70
±1.0
±90
HD2
HD3
0.0
±0.5
0.5
±100
1.0
Output Common Mode Voltage (V)
±3
0
1
2
C001
VS = ±2.5 V, f = 200 MHz, VOUT_AMP = 2 VPP
Figure 22. HD2 and HD3 vs Input Common-Mode Voltage
±20
HD2
HD3
±30
±1
Input Common Mode Voltage (V)
Figure 21. HD2 and HD3 vs Output Common-Mode Voltage
±20
±2
C004
VS = ±1.65 V, f = 1000 MHz, VOUT_AMP = 1 VPP
HD2
HD3
±30
±40
Distortion (dBc)
±40
Distortion (dBc)
±40
±60
±80
±50
±60
±70
±50
±60
±70
±80
±80
±90
±90
±100
±100
±2
±1
0
1
Input Common Mode Voltage (V)
±3
Figure 23. HD2 and HD3 vs Input Common-Mode Voltage
±2
±1
0
1
Input Common Mode Voltage (V)
C001
VS = ±1.65 V, f = 200 MHz, VOUT_AMP = 1 VPP
12
±30
2
C001
VS = ±2.5 V, f = 500 MHz, VOUT_AMP = 2 VPP
Figure 24. HD2 and HD3 vs Input Common-Mode Voltage
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Typical Characteristics (continued)
At TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (ROUT = 40 Ω each), G = 16 dB, single-ended input and
differential output, and input and output pins referenced to midsupply, unless otherwise noted. Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 49 to Figure 53).
±20
±20
HD2
HD3
±30
±40
Distortion (dBc)
Distortion (dBc)
±40
±50
±60
±70
±50
±60
±70
±80
±80
±90
±90
±100
±100
±2
0
±1
1
Input Common Mode Voltage (V)
±3
1
2
C001
Figure 26. HD2 and HD3 vs Input Common-Mode Voltage
0
Intermodulation Products (dBc)
±40
±50
±60
±70
±80
±90
±100
±20
±40
±60
±80
±100
IMD2
IMD3
±120
±2
0
±1
10
1
Input Common Mode Voltage (V)
100
1000
Frequency (MHz)
C001
VS = ±1.65 V, f = 1 GHz, VOUT_AMP = 1 VPP
C002
VS = ±2.5 V, VOUT_AMP = 1 VPP per tone,
Figure 27. HD2 and HD3 vs Input Common-Mode Voltage
Figure 28. Intermodulation Distortion vs Frequency
0
±20
Intermodulation Products (dBc)
IMD2
IMD3
±30
±40
Distortion (dBc)
0
VS = ±2.5 V, f = 1 GHz, VOUT_AMP = 2 VPP
HD2
HD3
±30
±1
Input Common Mode Voltage (V)
Figure 25. HD2 and HD3 vs Input Common-Mode Voltage
±20
±2
C001
VS = ±1.65 V, f = 500 MHz, VOUT_AMP = 1 VPP
Distortion (dBc)
HD2
HD3
±30
±50
±60
±70
±80
±90
±20
±40
±60
±80
±100
IMD2
IMD3
±100
±120
10
100
1000
Frequency (MHz)
10
VS = ±2.5 V, VOUT_AMP = 1 VPP per tone, RLOAD = 100 Ω
Figure 29. Intermodulation Distortion vs Frequency
(100-Ω Load)
100
1000
Frequency (MHz)
C002
C003
VS = ±1.65 V, VOUT_AMP = 0.5 VPP per tone
Figure 30. Intermodulation Distortion vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (ROUT = 40 Ω each), G = 16 dB, single-ended input and
differential output, and input and output pins referenced to midsupply, unless otherwise noted. Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 49 to Figure 53).
0
Intermodulation Products (dBc)
Intermodulation Products (dBc)
0
-20
-40
-60
-80
-100
IMD2 (dBc)
IMD3 (dBc)
-120
-10
-5
0
5
±20
±40
±60
±80
±100
10
Output Power per Tone (dBm)
IMD2 (dBc)
IMD3 (dBc)
±120
±10
5
10
Output Power per Tone (dBm)
VS = ±2.5 V, power measured at amplifier
C004
VS = ±2.5 V, power measured at amplifier
Figure 31. Intermodulation Distortion (f = 200 MHz)
Figure 32. Intermodulation Distortion (f = 500 MHz)
100
0
±10
Voltage Noise (nV/¥Hz)
Intermodulation Products (dBc
0
±5
C002
±20
±30
±40
±50
±60
±70
±80
IMD2 (dBc)
IMD3 (dBc)
±90
±10
±5
0
5
10
1
0
0.1
10
Output Power per Tone (dBm)
1
10
100
1000
10000
Frequency (kHz)
C005
100000
C001
VS = ±2.5 V
VS = ±2.5 V, power measured at amplifier
Figure 34. Input-Referred Voltage Noise
Figure 33. Intermodulation Distortion (f = 1000 MHz)
3
15
Vout = 1Vpp
2
Vout = 3.3VPP
1
Vout (V)
Noise Figure (dB)
13
10
0
±1
8
±2
Vout = 1.8VPP
5
±3
0
500
1000
1500
2000
Frequency (MHz)
0
C001
VS = ±2.5 V
10
15
Time (ns)
20
C005
VS = ±2.5 V, VOUT_AMP
Figure 35. Noise Figure vs Frequency
14
5
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Figure 36. Pulse Response for Various VO
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Typical Characteristics (continued)
At TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (ROUT = 40 Ω each), G = 16 dB, single-ended input and
differential output, and input and output pins referenced to midsupply, unless otherwise noted. Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 49 to Figure 53).
0.08
2.5
0.07
2.0
0.06
1.5
0.05
1.0
Vout (V)
Vout (V)
0.04
0.03
0.02
0.0
0.01
0.00
±1.0
±0.01
±1.5
±2.0
1Vpp Pulse
±0.03
0
5
10
15
Vout = 1.8Vpp
±2.5
0.00
20
Time (ns)
Vout = 3.3Vpp
0.5
±0.5
±0.02
Vout = 1Vpp
5.00
10.00
15.00
20.00
Time (ns)
C002
VS = ±2.5 V, VOUT_AMP, VCM = (VO+ + VO–) / 2
C001
VS = ±1.65 V, VOUT_AMP
Figure 37. Pulse Response Common-Mode
Figure 38. Pulse Response for Various VO
0.10
80
1Vpp Pulse
0.09
70
0.08
60
CMRR (dB)
Vout (V)
0.07
0.06
0.05
0.04
50
40
30
0.03
20
0.02
0.01
10
0.00
0
0
5
10
15
20
Time (ns)
3.3V
5V
1
100
1000
10000
Frequency (MHz)
VS = ±1.65 V, VOUT_AMP
C009
Differential input
Figure 39. Pulse Response Common-Mode
Figure 40. CMRR (Sdc21)
0
0
±10
Normalized Gain(dB)
-10
Balance Error (dBc)
10
C002
-20
-30
-40
-50
±20
±30
±40
±50
±60
±70
-60
-70
1
10
100
1000
3.3V
±90
10000
Frequency (MHz)
5V
±80
3.3V
5V
10
100
1000
10000
Frequency (MHz)
C008
C007
Common-mode input, common-mode output,
RS = 25 Ω, RL = 50 Ω
Single-ended input, differential output
Figure 41. Balance Error (Scd21)
Figure 42. Common-Mode Frequency Response (Scc21)
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Typical Characteristics (continued)
At TA = 25°C, split supplies, VCM = 0 V, RL = 200-Ω differential (ROUT = 40 Ω each), G = 16 dB, single-ended input and
differential output, and input and output pins referenced to midsupply, unless otherwise noted. Measured using an EVM as
discussed in the Parameter Measurement Information section (see Figure 49 to Figure 53).
2.5
6
VO Ideal
2.0
Output Voltage (V)
Output Voltage (V)
4
Should PD be on a secondary y-axis?
1.5
1.0
0.5
0.0
±0.5
VO Measured
2
0
±2
±1.0
±4
Vout
VO
PD
±1.5
±2.0
0
10
20
±6
30
40
50
60
70
80
Time (ns)
90
100
0.0
0.5
1.0
1.5
2.0
Time (ns)
C027
VS = ±2.5 V
2.5
C028
VS = ±2.5 V
Figure 43. Power-Down Timing
Figure 44. Overdrive Recovery
0.15
58
Supply Current (mA)
Gain Error (dB)
0.10
0.05
0.00
±0.05
±0.10
57
56
55
54
0
±50
50
100
Temperature (ƒC)
0
±50
50
Temperature (ƒC)
C003
VS = ±2.5 V
100
C001
VS = ±2.5 V
Figure 45. Gain Drift vs Temperature
Figure 46. Supply Current vs Temperature
0.0
1.8
Output Offset Voltage (mV)
Output Offset Voltage (mV)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
5V
3.3V
0.2
0.0
±50.0
0.0
50.0
Temperature (ƒC)
100.0
±5.0
±10.0
±15.0
±20.0
±25.0
±30.0
±50.0
0.0
50.0
Temperature (ƒC)
C001
At dc
100.0
C001
At dc
Figure 47. Differential Offset Voltage vs Temperature
16
5V
3.3V
Figure 48. Common-Mode Offset Voltage vs Temperature
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8 Parameter Measurement Information
8.1 Output Reference Points
The LMH3401 has on-chip output load resistors. When matching the output to a 100-Ω load, the evaluation
module (EVM) uses external 40-Ω resistors to complete the output matching. Having on-chip output resistors
creates two potential reference points for measuring the output voltage. The amplifier output pins are one output
reference point (OUT_AMP). The other output reference point is the point at the matched 100-Ω load
(OUT_LOAD). These points are illustrated in Figure 49 to Figure 53; see the Test Schematics section.
Most measurements in the Electrical Characteristics tables and in the Typical Characteristics are measured with
reference to the OUT_AMP reference point. The conversion between reference points is a straightforward
correction of 3 dB for power and 6 dB for voltage, as shown in Equation 1. The measurements are referenced to
OUT_AMP when not specified.
VOUT_LOAD = (VOUT_AMP – 6 dB); and POUT_LOAD = (POUT_AMP – 3 dB)
(1)
8.2 ATE Testing and DC Measurements
All production testing and ensured dc parameters are measured on automated test equipment capable of dc
measurements only. Measurements such as output current sourcing and sinking are made in reference to the
device output pins. Some measurements such as voltage gain are referenced to the output of the internal
amplifier and do not include losses attributed to the on-chip output resistors. The Electrical Characteristics table
conditions specify these conditions. When the measurement is referred to the amplifier output, then the output
resistors are not included in the measurement. If the measurement is referred to the device pins, then the output
resistor loss is included in the measurement.
8.3 Frequency Response
This test is run with both single-ended inputs and differential inputs.
For tests with single-ended inputs, the standard EVM is used with no changes; see Figure 49. In order to provide
a matched input, the unused input requires a broadband 50-Ω termination to be connected. When using a fourport network analyzer, the unused input can either be terminated with a broadband load, or can be connected to
the unused input on the four-port analyzer. The network analyzer provides proper termination. A network
analyzer is connected to the input and output of the EVM with 50-Ω coaxial cables and is set to measure the
forward transfer function (s21). The input signal frequency is swept with the signal level set for the desired output
amplitude.
The LMH3401 is fully symmetrical, either input (IN+ or IN–) can be used for single-ended inputs. The unused
input must be terminated.
For tests with differential inputs, the same setup for single-ended inputs is used except all four connectors are
connected to a network analyzer port. Measurements are made in either true differential mode on the Rohde &
Schwarz® network analyzer or in calculated differential mode. In both cases, the differential inputs are each
driven with a 50-Ω source. External resistors are recommended if a matched condition is desired because the
LMH3401 does not provide an input match for 100-Ω differential sources. Both unterminated (Figure 50) and
terminated (Figure 51) differential input measurements are included in this data sheet. The termination is clearly
marked in the figure conditions.
8.4 S-Parameters
The standard EVM is used for all s-parameter measurements. All four ports are used or are terminated with
50 Ω, as in the Frequency Response section.
8.5 Frequency Response with Capacitive Load
The standard EVM is used and the capacitive load is soldered to the inside pads of the 40-Ω matching resistors
(on the DUT side). This this configuration, the on-chip, 10-Ω resistors isolate the capacitive load from the
amplifier output pins. The test schematic for capacitive load measurements is illustrated in Figure 52.
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8.6 Distortion
The standard EVM is used for measuring single-tone harmonic distortion and two-tone intermodulation distortion.
All distortion is measured with single-ended input signals; see Figure 53. In order to interface with single-ended
test equipment, external baluns are required between the EVM output ports and the test equipment. The Typical
Characteristics plots were created using Marki™ baluns, model number BAL-0010. These baluns are used to
combine two tones in the two-tone tests. For distortion measurements the same termination must be used on
both input pins. When a filter is used on the driven input port, the same filter and a broadband load is used to
terminate the other input. When the signal source is a broadband controlled impedance, then only a broadband
controlled impedance is required to terminate the unused input.
8.7 Noise Figure
The standard EVM is used with a single-ended input and the Marki balun on the output. The noise figure is
based on an active input match provided by the on-chip resistor network.
8.8 Pulse Response, Slew Rate, Overdrive Recovery
The standard EVM is used for time-domain measurements. The input is single-ended while the differential
outputs are routed directly to the oscilloscope inputs. The differential signal response is calculated from the two
separate oscilloscope inputs. In addition, the common-mode response is also captured in this configuration.
8.9 Power Down
The standard EVM is used with the shorting block on jumper JPD removed completely. A high-speed, 50-Ω pulse
generator is used to drive the PD pin while the output signal is measured by viewing the output signal (such as a
250-MHz sine wave).
8.10 VCM Frequency Response
The standard EVM is used with Rcm+ and Rcm– removed and a new resistor installed at Rtcm = 49.9 Ω; C17. A
network analyzer is connected to the VCM input of the EVM and the EVM outputs are connected to the network
analyzer with 50-Ω coaxial cables. Set the network analyzer analysis settings to single-ended input and
differential output. Measure the output common-mode with respect to the single-ended input (Scs21). The input
signal frequency is swept with the signal level set for 100 mV (–16 dBm). Note that the common-mode control
circuit gain is one.
18
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8.11 Test Schematics
200 :
50-:, Single-Ended
Input
IN-
Test Equipment
With 50-:
Outputs
12.5 :
:
:
-
OUT+ :
+
OUT_AMP
-
+
VIN
Differential
Load = 200 :
IN+
:
12.5 :
200 :
CM
+
OUT_LOAD
-
:
Test Equipment
With 50-:
Inputs
OUTTest Equipment
Load = 100 :
Device
PD
Figure 49. Test Schematic: Single-Ended Input, Differential Output
200 :
50-:, Single-Ended
Input
IN-
Test Equipment
With 50-:
Outputs
+V
IN
-
12.5 :
Differential
Load = 200 :
:
OUT+ :
+
OUT_AMP
-
IN+
:
12.5 :
200 :
CM
:
+
OUT_LOAD
-
Test Equipment
With 50-:
Inputs
OUTTest Equipment
Load = 100 :
Device
PD
Figure 50. Test Schematic: Differential Input, No Input Match
200 :
50-:, Single-Ended
Input
37.5 :
Test Equipment
With 50-:
Outputs
+V
IN
-
12.5 :
Differential
Load = 200 :
:
OUT+ :
+
OUT_AMP
-
37.5 :
:
12.5 :
200 :
CM
:
+
OUT_LOAD
-
Test Equipment
With 50-:
Inputs
OUTTest Equipment
Load = 100 :
Device
PD
Figure 51. Test Schematic: Differential Input, Input Matched to 100-Ω Differential
Note that in Figure 50, even though the amplifier gain is AV = 200 / 12.5 = 16 V/V (or 24 dB) there is a significant
loss at the input resulting from the low input impedance. With 50-Ω test equipment this loss is 12.5 / (50 + 12.5)
= 0.2 V/V (or –10 dB). The loss created by the low input impedance puts the net gain for this circuit at 14 dB,
only slightly higher than the gain for the fully-terminated configuration of 12 dB. In most applications the external
input termination resistors are worth the cost.
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Test Schematics (continued)
200 :
50-:, Single-Ended
Input
IN-
Test Equipment
With 50-:
Outputs
12.5 :
:
+
OUT_AMP
-
+
VIN
:
-
Differential
Load = 200 :
OUT+
IN+
+
OUT_LOAD
-
COUT
:
12.5 :
Test Equipment
With 50-:
Inputs
:
OUT-
200 :
CM
:
Test Equipment
Load = 100 :
Device
PD
Figure 52. Test Schematic for Capacitive Load
200 :
50-:, Single-Ended
Input
IN-
Signal Generator
With 50-:
Outputs
12.5 :
:
:
-
OUT+
+
OUT_AMP
-
+
VIN
Differential
Load = 200 :
IN+
:
12.5 :
200 :
CM
:
COUT
OUT-
:
+
-
BAL
0010
Spectrum Analyzer
With 50-:
Input
OUT_LOAD
Device
PD
Figure 53. Test Schematic for Harmonic Distortion
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9 Detailed Description
9.1 Overview
The LMH3401 is a very high-performance, differential amplifier optimized for radio frequency (RF) and
intermediate frequency (IF) or high-speed, time-domain applications with signal bandwidths up to 2 GHz. The
device is ideal for dc- or ac-coupled applications that may require a single-ended to differential conversion when
driving an analog-to-digital converter (ADC). The necessary feedback (RF) and gain set (RG) resistors are
fabricated on the device silicon and provide 16 dB of gain when configured for single-ended inputs driven from a
50-Ω source. When used in a fully-differential configuration, 12 dB is obtained when matching the input to a
100-Ω differential. The on-chip resistors simplify PCB implementation and ensure the highest performance over
the useable bandwidth of 2 GHz.
A common-mode reference input pin is provided to align the amplifier output common-mode with the ADC input
requirements. Power supplies between 3.3 V and 5.0 V can be selected and dual-supply operation is supported
when required by the application. A power-down feature is also available for power savings.
In addition to the on-chip feedback resistors, the LMH3401 offers two on-chip termination resistors, one for each
output with values of 10 Ω each. For most load conditions the 10-Ω resistors are only a partial termination,
consequently external termination resistors are required in most applications. Some common load values and the
matching resistors; see Table 1.
9.2 Functional Block Diagram
200
RF
RG
10
IN-
OUT+
12.5
CM
LMH3401
OUT-
RG
10
IN+
12.5
RF
200
PD
9.3 Feature Description
The LMH3401 includes the following features:
• Fully-differential amplifier
• Fixed gain with on-chip resistors
• Output common-mode control
• Single- or split-supply operation
• Small-signal bandwidth of 7 GHz
• Linear bandwidth of 2 GHz
• Power down
9.3.1 Fully-Differential Amplifier
The LMH3401 is a voltage feedback (VFA)-based fully-differential amplifier (FDA) offering a 7-GHz signal
bandwidth with on-chip gain set and feedback resistors. The core differential amplifier is a slightly
decompensated voltage feedback design with a high slew rate, and best-in-class linearity up to 2 GHz. The onchip feedback network provides a gain of 16 dB when used as a single-ended amplifier or 12 dB when used as a
differential amplifier and matched to a 100-Ω source with external, series 37.5-Ω resistors.
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Feature Description (continued)
Like all FDA devices, the output average voltage (common-mode) is controlled by a separate common-mode
loop. The target for this output average is set by the VCM input pin. The VOCM range extends from 1.1 V below the
mid-supply voltage to 1.1 V above the mid-supply voltage when using a 5-V supply. Note that on a 3.3-V supply
the output common-mode range is quite small. For applications using a 3.3-V supply voltage, the output
common-mode must remain very close to the mid-supply voltage.
The input common-mode voltage offers more flexibility than the output common-mode voltage. The input
common-mode range extends from the negative rail to approximately 1 V above the mid-supply voltage when
powered with a 5-V supply.
A power-down pin is included. This pin is referenced to the GND pins with a threshold voltage of approximately
1 V. Setting the PD pin voltage to more than 1.2 V turns the device off, placing the LMH3401 into a very low
quiescent current state. Note that, when disabled, the signal path is still present through the passive external
resistors. Input signals applied to a disabled LMH3401 device still appear at the outputs at some level through
this passive resistor path as they would for any disabled FDA device. The power-down pin is biased to the logic
low state with a 50-kΩ internal resistor.
9.3.2 Single-Ended to Differential Signals
The LMH3401 can be used to amplify and convert single-ended input signals to differential output signals. A
basic block diagram of the circuit is shown in Figure 54. The gain from the single-ended input to the differential
output is 16 dB. In order to maintain proper balance in the amplifier and avoid offsets at the output, the unused
input pin must be biased to the same voltage as the input dc voltage, and the impedance on the unused pin must
match the source impedance of the driven input pin. For example, if a 50-Ω source biased to 2.5 V provides the
input signal, tie the other input pin to 2.5 V through 50 Ω. If a 50-Ω source is ac-coupled to the input, the
alternate input is ac-coupled to ground through a 50-Ω termination. Note that the ac coupling on both inputs
provides a similar frequency response to balance the gain over frequency. In single-ended to differential
applications, the input impedance is actively set by the amplifier. For example, in Figure 54, the input impedance
to the amplifier is 50 Ω even though the input resistor is only 12.5 Ω. This active input impedance match allows
for lower noise than the case of a purely resistive input impedance. Detailed solutions for input impedance
calculations are shown in the Input Impedance Calculations section.
When considering the input impedance of the LMH3401, the device input pins move in a common-mode sense
with the input signal. The common-mode current functions to increase the apparent input impedance at the
device input into the gain element over the value of RG. Input signals also can cause input clipping if this
common-mode signal moves beyond the input range. This input active impedance issue applies to both ac- and
dc-coupled designs and requires somewhat more complex solutions for the resistors to account for this issue.
The full set of resistor value calculations is included in the Resistor Design Equations for Single-to-Differential
Applications section.
200 :
50-:, Single-Ended
Input
Differential
Output
12.5 :
:
VIN
V OUT+
:
V OUT-
VREF
12.5 :
CM
:
200 :
Device
VREF Equal to
DC Voltage of VIN
PD
Figure 54. Single-Ended Input to Differential Output Amplifier
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Feature Description (continued)
9.3.2.1 Resistor Design Equations for Single-to-Differential Applications
Even though the resistors for the LMH3401 are on-chip, being familiar with the FDA resistor selection criteria is
still important. The design equations for setting the resistors around an FDA to convert from a single-ended input
signal to a differential output can be approached in several ways. In this section, several critical assumptions are
made to simplify the results:
• The feedback resistors are selected first and set to be equal on the two sides of the device.
• The dc and ac impedances from the summing junctions back to the signal source and ground (or a bias
voltage on the non-signal input side) are set as equal to retain the feedback divider balance on each side of
the FDA.
Both of these assumptions are typical and aimed to deliver the best dynamic range through the FDA signal path.
After the feedback resistor values are chosen, the aim is to solve for RT (a termination resistor to ground on the
signal input side), RG1 (the input gain resistor for the signal path), and RG2 (the matching gain resistor on the
non-signal input side), as shown in Figure 55 (this example uses the THS4541, an external resistor FDA). The
same resistor solutions can be applied to either ac- or dc-coupled paths. Adding blocking capacitors in the inputsignal chain is a simple option. Adding these blocking capacitors after the RT element (as shown in Figure 55)
has the advantage of removing any dc currents in the feedback path from the output VOCM to ground.
50- Input Match Gain of
2 V/V from RT Single-Ended
Source to Differential Output
C1
100 nF
50- Source
THS4541 Wideband,
Fully-Differential Amplifier
RF1
402
VCC
RG1
191
±
RT
60.2
VOCM
FDA
RLOAD
Measurement
500
±
+
PD
RG2
221
C2
100 nF
Output
+
Point
VCC
RF2
402
Figure 55. AC-Coupled, Single-Ended Source to a Differential Gain of a 2-V/V Test Circuit
Most FDA amplifiers use external resistors and have complete flexibility in the selected RF, just like the THS4541
does in Figure 55, however the LMH3401 has on-chip feedback resistors that are fixed at 200 Ω. The equations
used in this section still apply, and an external resistance can be added to the on-chip RG resistors.
After the feedback resistor values are chosen, the aim is to solve for RT (a termination resistor to ground on the
signal input side), RG1 (the input gain resistor for the signal path), and RG2 (the matching gain resistor on the
non-signal input side). The same resistor solutions can be applied to either ac- or dc-coupled paths. Adding
blocking capacitors in the input-signal chain is a simple option. Adding these blocking capacitors after the RT
element has the advantage of removing any dc currents in the feedback path from the output VOCM to ground.
Earlier approaches to the solutions for RT and RG1 (when the input must be matched to a source impedance, RS)
follow an iterative approach. This complexity arises from the active input impedance at the RG1 input. When the
FDA is used to convert a single-ended signal to differential, the common-mode input voltage at the FDA inputs
must move with the input signal to generate the inverted output signal as a current in the RG2 element. A more
recent solution is illustrated in Equation 2, where a quadratic in RT can be solved for an exact required value.
This quadratic emerges from the simultaneous solution for a matched input impedance and target gain. The only
inputs required are:
1. The selected RF value.
2. The target voltage gain (AV) from the input of RT to the differential output voltage.
3. The desired input impedance at the junction of RT and RG1 to match RS.
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Feature Description (continued)
Solving this quadratic for RT starts the solution sequence, as shown in Equation 2:
R
§
·
2R S ¨ 2R F S A V 2 ¸
2R F R S2 A V
2
©
¹
R T 2 R T
0
2RF 2 A V R S A V (4 A V ) 2RF 2 A V R S A V (4 A V )
(2)
Being a quadratic, there are limits to the range of solutions. Specifically, after RF and RS are chosen, there is
physically a maximum gain beyond which Equation 2 starts to solve for negative RT values (if input matching is a
requirement). With RF selected, use Equation 3 to verify that the maximum gain is greater than the desired gain.
Av max
RF
RS
ª
R
4 F
«
RS
2 ‡ «1 1 «
RF
(
2)2
«
R
S
¬«
º
»
»
»
»
¼»
(3)
If the achievable AVmax is less than desired, increase the RF value. After RT is derived from Equation 2, the RG1
element is given by Equation 4:
R
2 F RS
AV
R G1
R
1 S
RT
(4)
Then, the simplest approach is to use a single RG2 = RT || RS + RG1 on the non-signal input side. Often, this
approach is shown as the separate RG1 and RS elements. This approach can provide a better divider match on
the two feedback paths, but a single RG2 is often acceptable. A direct solution for RG2 is given as Equation 5:
R
2 F
AV
R G2
R
1 S
RT
(5)
This design proceeds from a target input impedance matched to RS, signal gain AV, and a selected RF value. The
nominal RF value chosen for the LMH3401 characterization is 200 Ω. As discussed previously, this resistance is
on-chip and cannot be changed.
Note that when driving the LMH3401 with a 50-Ω source impedance the on-chip resistor is RG1 and the other
input requires only 50 Ω to complete RG2. The above equations are provided to help show the effects of the
active termination and to assist when using the LMH3401 with source impedances other than 50 Ω.
9.3.2.2 Input Impedance Calculations
The designs so far have included a source impedance, RS, that must be matched by RT and RG1. The total
impedance with respect to the input at RG1 for the circuit of Figure 54 is the parallel combination of RT to ground
and ZA (active impedance) presented by the amplifier input at RG1. That expression, assuming RG2 is set to
obtain a differential divider balance, is given by Equation 6:
ZA
§
R G1 ·§
RF ·
¨1 ¸¨ 1 ¸
R
R
G2 ¹©
G1 ¹
R G1 ©
R
2 F
R G2
(6)
For designs that do not need impedance matching (but instead come from the low-impedance output of another
amplifier, for instance), RG1 = RG2 is the single-to-differential design used without RT to ground. Setting RG1 = RG2
= RG in Equation 6 gives the input impedance of a simple input FDA driving from a low-impedance, single-ended
source to a differential output.
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Feature Description (continued)
9.3.3 Differential to Differential Signals
The LMH3401 can also be used to amplify differential input signals to differential output signals. A basic block
diagram of the circuit is shown in Figure 56. The differential input impedance set by the on-chip resistors is lower
than optimal for most applications (25 Ω). In order to match a load such as 100 Ω, external resistors are required,
as shown in Figure 57.
200 :
Differential
Input
Differential
Output
:
12.5 :
V OUT+
V IN-
V OUT-
V IN+
12.5 :
:
200 :
CM
LMH3401
PD
Figure 56. Differential Input To Differential Output Amplifier
200 :
37.5 :
VIN100: Differential
37.5 :
Input
VIN+
12.5 :
Differential
Output
:
V OUT+
V OUT-
12.5 :
CM
200 :
:
LMH3401
Gain =20*log(200/50) =
12dB
PD
Figure 57. Differential Input Configured for a 100-Ω Source
9.3.4 Output Common-Mode Voltage
The CM input controls the output common-mode voltage. CM has no internal biasing network and must be driven
by an external source or resistor divider network to the positive power supply. The CM input impedance is very
high and bias current is not critical. Also, the CM input has no internal reference and must be driven from an
external source. Using a bypass capacitor is also necessary. A capacitor value of 0.01 µF is recommended. For
best harmonic distortion, maintain the CM input within ±1 V of the mid-supply voltage using a 5-V supply and
within ±0.5 V when using a 3.3-V supply. The CM input voltage can be operated outside this range if lower
output swing is used or distortion degradation is allowed. For more information, see Figure 18 and Figure 19.
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9.4 Device Functional Modes
9.4.1 Operation with a Split Supply
The LMH3401 can be operated using split supplies. One of the most common supply configurations is ±2.5 V. In
this case, VS+ is connected to 2.5 V, and VS– is connected to –2.5 V, while the GND pins are connected to the
system ground. As with any device, the LMH3401 is impervious to what the levels are named in the system. In
essence, using split supplies is simply a level shift of the power pins by –2.5 V. If everything else is level-shifted
by the same amount, the device does not detect any difference. With a ±2.5-V power supply, the CM range is
0 V ±1 V; while the input has a slightly larger range of –2.5 V to 1 V; see Figure 22. This design has certain
advantages in systems where signals are referenced to ground, and as noted in the ADC Input Common-Mode
Voltage Considerations—DC-Coupled Input section, for driving ADCs with low input common-mode voltage
requirements in dc-coupled applications. With the GND pin connected to the system ground, the power-down
threshold is 1.2 V which is compatible with most logic levels from 1.5-V CMOS to 2.5-V CMOS.
As noted previously, the absolute supply voltage values are not critical. For example, using a 4-V VS+ and a
–1-V VS– is still a 5-V supply condition. As long as the input and output common-mode voltages remain in the
optimum range, the amplifier can operate on any supply voltages from 3.3 V to 5.25 V. When considering using
supply voltages near the 3.3-V total supply, be very careful to make sure that the amplifier performance is
adequate. Setting appropriate common-mode voltages for large-signal swing conditions becomes difficult when
the supply voltage is below 4 V.
9.4.2 Operation with a Single Supply
As with split supplies, the LMH3410 can be operated from single-supply voltages from 3.3 V to 5.25 V. Singlesupply operation is most appropriate when the signal path is ac coupled and the input and output common-mode
voltages are set to mid supply by the CM pin and are preserved by coupling capacitors on the input and output.
For example, with a single 5-V supply the amplifier outputs are biased to between 2.0 V and 3.0 V. The input
common-mode range is more forgiving towards the negative supply rail, thus the input voltage can range from
0 V to 3.5 V. Although the amplifier operates outside these recommendations, there is less signal swing available
and performance degrades.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Input and Output Headroom Considerations
The starting point for most designs is to assign an output common-mode voltage. For ac-coupled signal paths,
this starting point is often the default mid-supply voltage to retain the most available output swing around the
output operating point, which is centered with Vcm equal to the mid-supply point. For dc-coupled designs, set this
voltage while considering the required minimum headroom to the supplies listed in the Electrical Characteristics
for VCM control. From that target output VCM, the next step is to verify that the desired output differential VPP stays
within the supplies. For any desired differential output voltage (VOPP) check the maximum possible signal swing
for each output pin. Make sure that each pin can swing to the voltage required by the application.
For instance, when driving the ADC12D1800RF with a 1.25-V common-mode and 0.8-VPP input swing, the
maximum output swing is set by the negative-going signal from 1.25 V to 0.2 V. The negative swing of the signal
is right at the edge of the output swing capability of the LMH3401. In order to set the output common-mode to an
acceptable range, a negative power supply of at least –1 V is recommended. The ideal negative supply voltage
is the ADC VCM – 2.5 V for the negative supply and the ADC VCM + 2.5 V for the input swing. In order to use the
existing supply rails, deviating from the ideal voltage may be necessary.
With the output headroom confirmed, the input junctions must also stay within their operating range. Because the
input range extends nearly to the negative supply voltage, input range limitations only appear when approaching
the positive supply where a maximum 1.5-V headroom is required.
The input pins operate at voltages set by the external circuit design, the required output VOCM, and the input
signal characteristics. The operating voltage of the input pins depends on the external circuit design. With a
differential input, the input pins operate at a fixed input VICM, and the differential input signal does not influence
this common-mode operating voltage.
AC-coupled differential input designs have a VICM equal to the output VOCM. DC-coupled differential input designs
must check the voltage divider from the source VCM to the LMH3401 CM setting. That result solves to an input
VICM within the specified range. If the source VCM can vary over some voltage range, the validation calculations
must include this variation.
10.1.2 Noise Analysis
The first step in the output noise analysis is to reduce the application circuit to its simplest form with equal
feedback and gain setting elements to ground (see Figure 58) with the FDA and resistor noise terms to be
considered. For most single-ended input applications, the LMH3401 has RF = 200 Ω and RG = 12.5 Ω + 50 Ω.
The noise equations show the benefit of active termination when using the LMH3401 for single-ended inputs.
The LMH3401 internal resistors are not 50 Ω, as is the case with resistive termination. Thus, active termination
gives a significant reduction in noise.
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Application Information (continued)
enRG2
enRF2
RG
RF
r
r
In+2
+
In±2
eno2
±
eni2
enRG2
enRF2
RG
RF
r
r
Figure 58. FDA Noise-Analysis Circuit
The noise powers are shown in Figure 58 for each term. When the RF and RG terms are matched on each side,
the total differential output noise is the root sum of squares (RSS) of these separate terms. Using NG ≡ 1 + RF /
RG, the total output noise is given by Equation 7. Each resistor noise term is a 4-kTR power.
eno
eniNG
2
2 inR F
2
2 4kTR FNG
(7)
The first term is simply the differential input spot noise times the noise gain. The second term is the input current
noise terms times the feedback resistor (and because there are two terms, the power is two times one of the
terms). The last term is the output noise resulting from both the RF and RG resistors, again times two, for the
output noise power of each side added together. Using the exact values for a 50-Ω, matched, single-ended to
differential gain, sweep with a fixed RF = 200 Ω and the intrinsic noise eni = 1.4 nV and In = 2.5 pA for the
LMH3401, which gives an output spot noise from Equation 7. Then, dividing by the signal gain (AV) gives the
input-referred, spot-noise voltage (ei). Note that for the LMH3401 the current noise is an insignificant noise
contributor because of the low value of RF.
10.1.3 Thermal Considerations
The LMH3401 is packaged in a space-saving UQFN package that has a thermal coefficient (RθJA) of 101°C/W.
Limit the total power dissipation in order to keep the device junction temperature below 150°C for instantaneous
power and below 125°C for continuous power.
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10.2 Typical Application
The LMH3401 is designed as a single-ended to differential conversion block with gain. The LMH3401 has no
low-end frequency cutoff and has 7 GHz of bandwidth. The LMH3401 is a very attractive substitute for a balun
transformer in many applications.
The resistors labeled RO serve to match the filter impedance the to 20-Ω amplifier output impedance. If no filter is
used these resistors may not be required if the ADC is located very close to the LMH3401. If there is a
transmission line between the LMH3401 and the ADC then the RO resistors must be sized to match the
transmission line impedance. A typical application driving an ADC is shown in Figure 59.
200 W
Single-Ended,
50-W Source
12.5 W
10 W
VOUT+
RO
AIN+
VIN
VCM
12.5 W
200 W
50 W
ADC
Filter
10 W
VOUT-
AINRO
CM
LMH3401
CM
Figure 59. Single-Ended Input ADC Driver
10.2.1 Design Requirements
The main design requirements are to keep the amplifier input and output common-mode voltages compatible
with the ADC requirements and the amplifier requirements. Using split power supplies may be required.
10.2.2 Detailed Design Procedure
10.2.2.1 Driving Matched Loads
The LMH3401 has on-chip output resistors, however for most load conditions additional resistance must be
added to the output to match a desired load. Table 1 lists the matching resistors for some common load
conditions.
Table 1. Load Component Values (1)
LOAD (RL)
(1)
RO+ AND RO– FOR A MATCHED TOTAL LOAD RESISTANCE AT
TERMINATION
AMPLIFIER OUTPUT
TERMINATION LOSS
50Ω
15 Ω
100 Ω
6 dB
100 Ω
40 Ω
200 Ω
6 dB
200 Ω
90 Ω
400 Ω
6 dB
400 Ω
190 Ω
800 Ω
6 dB
1 kΩ
490 Ω
2000 Ω
6 dB
The total load includes termination resistors.
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10.2.2.2 Driving Capacitive Loads
With high-speed signal paths, capacitive loading is highly detrimental to the signal path, as shown in Figure 60.
Designers must make every effort to reduce parasitic loading on the amplifier output pins. The device on-chip
resistors are included in order to isolate the parasitic capacitance associated with the package and the PCB pads
that the device is soldered to. The LMH3401 is stable with most capacitive loads up to 10 pF; however,
bandwidth suffers with capacitive loading on the output.
5
Normalized Gain (dB)
0
±5
±10
±15
0pF
1pF
2.2pF
4.7pF
10pF
±20
±25
±30
1
10
100
1000
Frequency (MHz)
C001
Figure 60. Frequency Response with Capacitive Load
10.2.2.3 Driving ADCs
The LMH3401 is designed and optimized for the highest performance to drive differential input ADCs. Figure 61
shows a generic block diagram of the LMH3401 driving an ADC. The primary interface circuit between the
amplifier and the ADC is usually a filter of some type for antialias purposes, and provides a means to bias the
signal to the input common-mode voltage required by the ADC. Filters range from single-order real RC poles to
higher-order LC filters, depending on the requirements of the application. Output resistors (RO) are shown on the
amplifier outputs to isolate the amplifier from any capacitive loading presented by the filter.
200W
Differential
Source
12.5W
10W
VOUT+
RO
VIN-
Filter
AIN+
VCM
ADC
VIN+
AIN12.5W
10W
200W
VOUT-
RO
CM
LMH3401
CM
Figure 61. Differential ADC Driver Block Diagram
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The key points to consider for implementation are the SNR, SFDR, and ADC input considerations, as described
in this section. When the application circuit requires an input match, external resistors can be used such as
shown in Figure 62.
200W
Differential
Source
12.5W
10W
VOUT+
RO
VIN-
Filter
37.5W
AIN+
VCM
ADC
VIN+
AIN37.5W
12.5W
10W
VOUT-
200W
RO
CM
LMH3401
CM
Figure 62. Using External Resistors for Matching a 100-Ω Source
10.2.2.3.1 SNR Considerations
The signal-to-noise ratio (SNR) of the amplifier and filter can be calculated from the amplitude of the signal and
the bandwidth of the filter. The noise from the amplifier is band-limited by the filter with the equivalent brick-wall
filter bandwidth. The amplifier and filter noise can be calculated using Equation 8:
SNRAMP+FILTER = 10 × log
V2O
e
2
= 20 × log
FILTEROUT
VO
eFILTEROUT
where:
•
•
•
•
eFILTEROUT = eNAMPOUT • √ENB,
eNAMPOUT = the output noise density of the LMH3401 (3.4 nV/√Hz),
ENB = the brick-wall equivalent noise bandwidth of the filter, and
VO = the amplifier output signal.
(8)
For example, with a first-order (N = 1) band-pass or low-pass filter with a 30-MHz cutoff, the ENB is 1.57 • f–3dB =
1.57 • 30 MHz = 47.1 MHz. For second-order (N = 2) filters, the ENB is 1.22 • f–3dB. As the filter order increases,
the ENB approaches f–3dB (N = 3 → ENB = 1.15 • f–3dB; N = 4 → ENB = 1.13 • f–3dB). Both VO and eFILTEROUT are
in RMS voltages. For example, with a 2-VPP (0.707 VRMS) output signal and a 30-MHz first-order filter, the SNR of
the amplifier and filter is 70.7 dB with eFILTEROUT = 3.4 nV/√Hz • √47.1 MHz = 23 μVRMS.
The SNR of the amplifier, filter, and ADC sum in RMS fashion, is as shown in Equation 9 (SNR values in dB):
-SNRAMP+FILTER
SNRSYSTEM = -20 × log
10
10
-SNRADC
+ 10
10
(9)
This formula shows that if the SNR of the amplifier and filter equals the SNR of the ADC, the combined SNR is
3 dB lower (worse). Thus, for minimal degradation (< 1 dB) on the ADC SNR, the SNR of the amplifier and filter
must be ≥ 10 dB greater than the ADC SNR. The combined SNR calculated in this manner is usually accurate to
within ±1 dB of the actual implementation.
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10.2.2.3.2 SFDR Considerations
The SFDR of the amplifier is usually set by the second-order or third-order harmonic distortion for single-tone
inputs, and by the second-order or third-order intermodulation distortion for two-tone inputs. Harmonics and
second-order intermodulation distortion can be filtered to some degree, but third-order intermodulation spurs
cannot be filtered. The ADC generates the same distortion products as the amplifier, but as a result of the
sampling and clock feedthrough, additional spurs (not linearly related to the input signal) are included.
When the spurs from the amplifier and filter are known, each individual spur can be directly added to the same
spur from the ADC, as shown in Equation 10, to estimate the combined spur (spur amplitudes in dBc):
-HDxADC
-HDxAMP+FILTER
HDxSYSTEM = -20 × log 10
20
+ 10
20
(10)
This calculation assumes the spurs are in phase, but usually provides a good estimate of the final combined
distortion.
For example, if the spur of the amplifier and filter equals the spur of the ADC, then the combined spur is 6 dB
higher. To minimize the amplifier contribution (< 1 dB) to the overall system distortion, the spur from the amplifier
and filter must be approximately 15 dB lower in amplitude than that of the converter. The combined spur
calculated in this manner is usually accurate to within ±6 dB of the actual implementation; however, higher
variations can be detected as a result of phase shift in the filter, especially in second-order harmonic
performance.
This worst-case spur calculation assumes that the amplifier and filter spur of interest is in phase with the
corresponding spur in the ADC, such that the two spur amplitudes can be added linearly. There are two phaseshift mechanisms that cause the measured distortion performance of the amplifier-ADC chain to deviate from the
expected performance calculated using Equation 10: common-mode phase shift and differential phase shift.
Common-mode phase shift is the phase shift detected equally in both branches of the differential signal path
including the filter. Common-mode phase shift nullifies the basic assumption that the amplifier, filter, and ADC
spur sources are in phase. This phase shift can lead to better performance than predicted when the spurs
become phase shifted, and there is the potential for cancellation when the phase shift reaches 180°. However,
there is a significant challenge in designing an amplifier-ADC interface circuit to take advantage of a commonmode phase shift for cancellation: the phase characteristic of the ADC spur sources are unknown, thus the
necessary phase shift in the filter and signal path for cancellation is also unknown.
Differential phase shift is the difference in the phase response between the two branches of the differential filter
signal path. Differential phase shift in the filter as a result of mismatched components caused by nominal
tolerance can severely degrade the even-order distortion of the amplifier-ADC chain. This effect has the same
result as mismatched path lengths for the two differential traces, and causes more phase shift in one path than
the other. Ideally, the phase response over frequency through the two sides of a differential signal path are
identical, such that even-order harmonics remain optimally out of phase and cancel when the signal is taken
differentially. However, if one side has more phase shift than the other, then the even-order harmonic
cancellation is not as effective.
Single-order RC filters cause very little differential phase shift with nominal tolerances of 5% or less, but higherorder LC filters are very sensitive to component mismatch. For instance, a third-order Butterworth bandpass filter
with a 100-MHz center frequency and a 20-MHz bandwidth shows as much as 20° of differential phase
imbalance in a SPICE Monte Carlo analysis with 2% component tolerances. Therefore, while a prototype may
work, production variance is unacceptable. In ac-coupled applications that require second- and higher-order
filters between the LMH3401 and ADC, a transformer or balun is recommended at the ADC input to restore the
phase balance. For dc-coupled applications where a transformer or balun at the ADC input cannot be used,
using first- or second-order filters is recommended to minimize the effect of differential phase shift because of the
component tolerance.
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10.2.2.3.3 ADC Input Common-Mode Voltage Considerations—AC-Coupled Input
The input common-mode voltage range of the ADC must be respected for proper operation. In an ac-coupled
application between the amplifier and the ADC, the input common-mode voltage bias of the ADC is
accomplished in different ways depending on the ADC. Some ADCs use internal bias networks such that the
analog inputs are automatically biased to the required input common-mode voltage if the inputs are ac-coupled
with capacitors (or if the filter between the amplifier and ADC is a band-pass filter). Other ADCs supply their
required input common-mode voltage from a reference voltage output pin (often called CM or VCM). With these
ADCs, the ac-coupled input signal can be re-biased to the input common-mode voltage by connecting resistors
from each input to the CM output of the ADC, as Figure 63 shows. However, the signal is attenuated because of
the voltage divider created by RCM and RO.
RO
RCM
AIN+
Amp
ADC
AIN-
RCM
CM
RO
Figure 63. Biasing AC-Coupled ADC Inputs Using the ADC CM Output
The signal can be re-biased when ac coupling; thus, the output common-mode voltage of the amplifier is a don’t
care for the ADC.
10.2.2.3.4 ADC Input Common-Mode Voltage Considerations—DC-Coupled Input
DC-coupled applications vary in complexity and requirements, depending on the ADC. One typical requirement is
resolving the mismatch between the common-mode voltage of the driving amplifier and the ADC. Devices such
as the ADS5424 require a nominal 2.4-V input common-mode, while other devices such as the ADS5485 require
a nominal 3.1-V input common-mode; still others such as the ADS6149 and the ADS4149 require 1.5 V and
0.95 V, respectively. As shown in Figure 64, a resistor network can be used to perform a common-mode level
shift. This resistor network consists of the amplifier series output resistors and pull-up or pull-down resistors to a
reference voltage. This resistor network introduces signal attenuation that may prevent the use of the full-scale
input range of the ADC. ADCs with an input common-mode closer to the typical 2.5-V LMH3401 output commonmode are easier to dc-couple, and require little or no level shifting.
VREF
VAMP+
RO
RP
ADC
VADC+
Amp
RIN
VAMP-
RO
RP
CIN
VADC-
VREF
Figure 64. Resistor Network To DC Level-Shift Common-Mode Voltage
For common-mode analysis of the circuit in Figure 64, assume that VAMP± = VCM and VADC± = VCM (the
specification for the ADC input common-mode voltage). VREF is chosen to be a voltage within the system higher
than VCM (such as the ADC or amplifier analog supply) or ground, depending on whether the voltage must be
pulled up or down, respectively; RO is chosen to be a reasonable value, such as 24.9 Ω. With these known
values, RP can be found by using Equation 11:
RP = RO
VADC - VREF
VAMP - VADC
(11)
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Shifting the common-mode voltage with the resistor network comes at the expense of signal attenuation.
Modeling the ADC input as the parallel combination of a resistance (RIN) and capacitance (CIN) using values
taken from the ADC data sheet, the approximate differential input impedance (ZIN) for the ADC can be calculated
at the signal frequency. The effect of CIN on the overall calculation of gain is typically minimal and can be ignored
for simplicity (that is, ZIN = RIN). The ADC input impedance creates a divider with the resistor network; the gain
(attenuation) for this divider can be calculated by Equation 12:
GAIN =
2RP || ZIN
2RO + 2RP || ZIN
(12)
With ADCs that have internal resistors that bias the ADC input to the ADC input common-mode voltage, the
effective RIN is equal to twice the value of the bias resistor. For example, the ADS5485 has a 1-kΩ resistor tying
each input to the ADC VCM; therefore, the effective differential RIN is 2 kΩ.
The introduction of the RP resistors also modifies the effective load that must be driven by the amplifier.
Equation 13 shows the effective load created when using the RP resistors.
RL = 2RO + 2RP || ZIN
(13)
The RP resistors function in parallel to the ADC input such that the effective load (output current) at the amplifier
output is increased. Higher current loads limit the LMH3401 differential output swing.
Using the gain and knowing the full-scale input of the ADC (VADC
with the network can be calculated using Equation 14:
V
VAMP PP = ADC FS
GAIN
FS),
the required amplitude to drive the ADC
(14)
As with any design, testing is recommended to validate whether the specific design goals are met.
10.2.2.4 GSPS ADC Driver
The LMH3401 can drive the full Nyquist bandwidth of ADCs with sampling rates up to 4 GSPS, as shown in
Figure 65. If the front-end bandwidth of the ADC is more than 2 GHz, use a simple noise filter to improve SNR.
Otherwise, the ADC can be connected directly to the amplifier output pins. Matching resistors may not be
required, however allow space for matching resistors on the preliminary design.
200 W
Single-Ended,
50-W Source
12.5 W
10 W
VOUT+
RO
AIN+
VIN
VCM
12.5 W
50 W
200 W
10 W
VOUT-
RO
GSPS ADC
AINCM
Device
CM
Figure 65. GSPS ADC Driver
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10.2.2.5 Common-Mode Voltage Correction
The LMH3401 can set the output common-mode voltage to within a typical value of ±30 mV. If greater accuracy
is desired, a simple circuit can improve this accuracy by an order of magnitude. A precision, low-power
operational amplifier is used to sense the error in the output common-mode of the LMH3401 and corrects the
error by adjusting the voltage at the CM pin. In Figure 66, the precision of the op amp replaces the less accurate
precision of the LMH3401 common-mode control circuit while still using the LMH3401 common-mode control
circuit speed. The op amp in this circuit must have better than a 1-mV input-referred offset voltage and low noise.
Otherwise the specifications are not very critical because the LMH3401 is responsible for the entire differential
signal path.
OUT+
IN±
±
5k
+
CM
LMH3401
±
IN+
5k
+
OUT-
10 nF
±
LMV771
+
Desired
Vocm
Figure 66. Common-Mode Correction Circuit
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10.2.2.6 Active Balun
The LMH3401 is designed to convert single-ended, 50-Ω source impedance signals to a differential output with
very high bandwidth and linearity, as shown in Figure 67. The LMH3401 can support dc coupling as well as ac
coupling. The LMH3401 is smaller than any balun with low-frequency response and has balance errors that are
excellent over a wide frequency range. As shown in Figure 68, the LMH3401 balance error is better than
–40 dBc up to 1 GHz when used with a 5-V supply.
200 :
50-:, Single-Ended
Input
Differential
Output
12.5 :
:
VIN
V OUT+
:
V OUT-
VREF
12.5 :
CM
:
200 :
Device
VREF Equal to
DC Voltage of VIN
PD
Figure 67. Active Balun
0
Balance Error (dBc)
-10
-20
-30
-40
-50
-60
3.3V
5V
-70
1
10
100
1000
Frequency (MHz)
10000
C008
Figure 68. Balance Error
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10.2.2.7 Application Curves
7
17
6
16
15
5
Gain (dB)
Resistor Loss (dB)
The LMH3401 has on-chip series output resistors to facilitate board layout. These resistors provide the LMH3401
extra phase margin in most applications. When the amplifier is used to drive a terminated transmission line or a
controlled impedance filter, extra resistance is required to match the transmission line of the filter. In these
applications, there is a 6 dB loss of gain. When the LMH3401 is used to drive loads that are not back-terminated
there is a loss in gain resulting from the on-chip resistors. Figure 69 shows that loss for different load conditions.
In most cases the loads are between 50 Ω and 200 Ω, where the on-chip resistor losses are 1.6 dB and 0.42 dB,
respectively. Figure 70 shows the net gain realized by the amplifier for a large range of load resistances.
4
3
2
14
13
12
11
1
10
0
9
10
100
1k
External Load (Ÿ)
10k
10
Figure 69. Gain Loss Due to On Chip Output Resistors
100
1k
External Load (Ÿ)
C072
10k
C073
Figure 70. Net Gain versus Load Resistance
10.3 Do's and Don'ts
10.3.1 Do:
• Include a thermal design at the beginning of the project.
• Use well-terminated transmission lines for all signals.
• Use solid metal layers for the power supplies.
• Keep signal lines as straight as possible.
• Use split supplies where required.
10.3.2 Don't:
• Use a lower supply voltage than necessary.
• Use thin metal traces to supply power.
• Forget about the common-mode response of filters and transmission lines.
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11 Power-Supply Recommendations
The LMH3401 can be used with either split or single-ended power supplies. The ideal supply voltage is a 5.0-V
total supply, split around the desired common-mode of the output signal swing. For example, if the LMH3401 is
used to drive an ADC with a 1.0-V input common mode, then the ideal supply voltages are 3.5 V and –1.5 V. The
GND pin can then be connected to the system ground and the PD pin is ground referenced.
11.1 Supply Voltage
Using a 5-V power supply gives the best balance of performance and power dissipation. If power dissipation is a
critical design criteria a power supply as low as 3.3 V (±1.65) can be used. When using a lower power supply,
the input common-mode and output swing capabilities are drastically reduced. Make sure to study the commonmode voltages required before deciding on a lower-voltage power supply. In most cases the extra performance
achieved with 5-V supplies is worth the power.
11.2 Single Supply
Single-supply voltages from 3.3 V to 5 V are supported. When using a single supply check both the input and
output common-mode voltages that are required by the system.
11.3 Split Supply
In general, split supplies allow the most flexibility in system design. To operate as split supply, apply the positive
supply voltage to VS+, the negative supply voltage to VS–, and the ground reference to GND. Note that supply
voltages do not need to be symmetrical. Provided the total supply voltage is between 3.3 V and 5.25 V, any
combination of positive and negative supply voltages is acceptable. This feature is often used when the output
common-mode voltage must be set to a particular value. For best performance, the power-supply voltages are
symmetrical around the desired output common-mode voltage. The input common-mode voltage range is much
more flexible than the output.
11.4 Supply Decoupling
Power-supply decoupling is critical to high-frequency performance. Onboard bypass capacitors are used on the
LMH3401EVM; however, the most important component of the supply bypassing is provided by the PCB. As
illustrated in Figure 71, there are multiple vias connecting the LMH3401 power planes to the power-supply
traces. These vias connect the internal power planes to the LMH3401. Both VS+ and VS– must be connected to
the internal power planes with several square centimeters of continuous plane in the immediate vicinity of the
amplifier. The capacitance between these power planes provides the bulk of the high-frequency bypassing for
the LMH3401.
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12 Layout
12.1 Layout Guidelines
With 7 GHz of bandwidth, layout for the LMH3401 is critical and nothing can be neglected. In order to simplify
board design, the LMH3401 has on-chip resistors that reduce the impact of off-chip capacitance. For this reason,
TI recommends that the ground layer below the LMH3401 not be cut. The recommendation not to cut the ground
plane under the amplifier input and output pins is different than many other high-speed amplifiers, but the reason
is that parasitic inductance is more harmful to the LMH3401 performance than parasitic capacitance. By leaving
the ground layer under the device intact, parasitic inductance of the output and power traces is minimized. The
DUT portion of the evaluation board layout is illustrated in Figure 71 and Figure 72.
The EVM uses long edge capacitors for the decoupling capacitors, which reduces series resistance and
increases the resonant frequency. Vias are also placed to the power planes before the bypass capacitors.
Although not evident in the top layer, two vias are used at the capacitor in addition to the two vias underneath the
device.
The output matching resistors are 0402 size and are placed very close to the amplifier output pins, which
reduces both parasitic inductance and capacitance. The use of 0603 output matching resistors produces a
measurable decrease in bandwidth.
When the signal is on a 50-Ω controlled impedance transmission line, the layout then becomes much less critical.
The transition from the 50-Ω transmission line to the amplifier pins is the most critical area.
The CM pin also requires a bypass capacitor. Place this capacitor near the device. Refer to the user guide
LMH3401EVM Evaluation Module (SBOU124) for more details on board layout and design.
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12.2 Layout Example
Figure 71. Layout Example
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Layout Example (continued)
Figure 72. EVM Layout Ground Layer Showing Solid Ground Plane
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13 Device and Documentation Support
13.1 Device Support
13.1.1 Device Nomenclature
= Pin 1 designator
L3401
THS770006IRGE = device name
TIYMF
TI = TI LETTERS
PLLL
YM = YEAR MONTH DATE CODE
F P = ASSEMBLY SITE CODES
LLL = ASSY LOT CODE
Figure 73. Device Marking Information
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• THS4541 Data Sheet, SLOS375
• ADS12D1800RF Data Sheet, SNAS518
• ADS5424 Data Sheet, SLWS157
• ADS5485 Data Sheet, SLAS610
• ADS6149 Data Sheet, SLWS211
• ADS4149 Data Sheet, SBAS483
• LMH3401EVM Evaluation Module, SBOU124
• AN-2188 Between the Amplifier and the ADC: Managing Filter Loss in Communications Systems, SNOA567
• AN-2235 Circuit Board Design for LMH6517/21/22 and Other High-Speed IF/RF Feedback Amplifiers,
SNOA869
13.3 Trademarks
Marki is a trademark of Marki Microwave, Inc.
Rohde & Schwarz is a registered trademark of Rohde & Schwarz.
All other trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
13.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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4-Nov-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMH3401IRMSR
ACTIVE
UQFN
RMS
14
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
L3401
LMH3401IRMST
ACTIVE
UQFN
RMS
14
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 85
L3401
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
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Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMH3401IRMSR
UQFN
RMS
14
3000
180.0
9.5
2.7
2.7
0.7
4.0
8.0
Q2
LMH3401IRMST
UQFN
RMS
14
250
180.0
9.5
2.7
2.7
0.7
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMH3401IRMSR
UQFN
RMS
14
3000
205.0
200.0
30.0
LMH3401IRMST
UQFN
RMS
14
250
205.0
200.0
30.0
Pack Materials-Page 2
PACKAGE OUTLINE
RMS0014A
UQFN - 0.6 mm max height
SCALE 5.500
UQFN
2.6
2.4
B
A
PIN 1 INDEX AREA
2.6
2.4
C
0.6 MAX
SEATING PLANE
0.05
0.00
0.08 C
2X 1.5
(0.15)
TYP
SYMM
7
4
3
2X
1
8
10X 0.5
SYMM
1
10
14X
14
0.5 0.05
PIN 1 ID
(45 X 0.1)
11
13X
0.3
0.2
0.1
0.05
C B
C
A
0.45
0.35
4221200/A 12/2013
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RMS0014A
UQFN - 0.6 mm max height
UQFN
(2.3)
SEE DETAILS
11
14
(0.7)
(0.3)
10
1
SYMM
(2.3)
10X (0.5)
8
3
13X (0.6)
4
14X (0.25)
7
SYMM
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MAX
ALL AROUND
(0.07)
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221200/A 12/2013
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB application report
in literature No. SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RMS0014A
UQFN - 0.6 mm max height
UQFN
(2.3)
14
11
(0.7)
(0.3)
10
1
SYMM
(2.3)
10X (0.5)
8
3
14X (0.6)
14X (0.25)
4
7
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:20X
4221200/A 12/2013
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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