Holt HI-8020 Cmos high voltage display driver Datasheet

HI-8020/HI-8120
January 2001
GENERAL DESCRIPTION
PIN CONFIGURATION (Top View)
The HI-8020 & HI-8120 high voltage display drivers
are functional replacements for the AMI S5420 and
Micrel MIC8013/8014 series. These CMOS products are designed to drive liquid crystal displays by
converting 5 volt serial data to parallel segment and
backplane waveforms with amplitudes up to 30 volts.
The HI-8020 & HI-8120 differ from the HI-8010 by
only the shift register clock and chip select gating
logic. The HI-8020 has TTL logic inputs whereas the
HI-8120 has CMOS logic inputs.
S27
S28
S29
S30
S31
S32
N/C
VSS
CS
CL
LD
Both devices can drive up to 38 segments and have 3
possible shift register data taps to provide options to
cascade devices for larger displays. Data is clocked
into a 38 stage shift register and parallel latched
before the output translators by a Load input.
7
39
8
38
9
10
11
12
HI-8020J-85
&
HI-8120J-85
13
14
15
16
37
36
35
34
33
44 - PIN
PLASTIC
PLCC
17
32
31
30
29
S17
S16
S15
VEE
S14
S13
S12
S11
S10
S9
S8
The HI-8020 & HI-8120 are available in a variety of
ceramic and plastic packaging including DIP; leaded
and leadless chip carriers; and J-lead and gull-wing
quad flat packs.
(See page 3-6 for additional package pin configurations)
FEATURES
! 5 volt input translated to 30 volts or less
! Pin-out adaptable to drive 30, 32 or 38
LCD segments
! RC oscillator or high voltage (BP) clock input
! TTL compatible inputs (HI-8020 only)
FUNCTIONAL BLOCK DIAGRAM
DIN Þ
CL Þ
DATA IN
38 Stage
Shift Register
! CMOS compatible inputs (HI-8120 only)
CLK
! Low power consumption
CS Þ
! Industrial (-40°C to +85°C) & Military (-55°C
to +125°C) temperature ranges
LD Þ
! Pin for pin compatible with the Micrel
MIC8010/8011 series and the AMI S4520
series drivers
! Cascadable
LCDØ Þ
LCDØ OPT Þ
Þ DOUT 38
Þ DOUT 32
Þ DOUT 30
38 Bit Latch
Oscillator
Divider
Voltage
Translator
! Military level processing available
Voltage
Translators
High Voltage
Drivers
H i g h Voltage
Buffer
Þ BP
! Dichroic Liquid Crystal Displays
! Standard Liquid Crystal Displays
! Vacuum Fluorescent Displays
(DS8020 Rev. B)
HOLT INTEGRATED CIRCUITS
3-9
SEGMENTS
01/01
HI-8020/HI-8120 Series
FUNCTIONAL DESCRIPTION
Whenever a Logic "0" is applied to the Chip Select (CS)
input, one bit of data is clocked into the shift register from the
serial data input (DIN) with each negative transition of the
Clock (CL) input. CS is internally tied to VSS on some
versions. A Logic "1" present at the Load (LD) input will
cause a parallel transfer of data from the shift register to the
data latch. If the Load (LD) input is held high while data is
clocked into the shift register, the latch will be transparent.
All four logic inputs are TTL compatible on the HI-8020 and
CMOS compatible on the HI-8120.
on the rising edge of the Clock (CL). Clock (CL), Load (LD)
and Chip Select (CS) should be tied in common with each
other, respectively, between all cascaded display drivers.
INTERNAL OSCILLATOR CIRCUIT
To display segments, a Logic "1" is stored in the appropriate
shift register bit position, and the segment output is out-ofphase with the backplane.
The backplane output functions in 1 of 2 modes; externally
driven or self-oscillating. When the LCDØ input is externally
driven with the LCDØOPT input open circuit (Figure 2), the
backplane output will be in-phase with LCDØ. Utilizing the
self-oscillating mode, inputs LCDØ and LCDØOPT are tied
together and connected to an RC circuit (Figure 3).
A 150KW resistor with a 470pF capacitor generates an
approximate backplane frequency of 100Hz. The
LCDØ/LCDØOPT oscillator frequency is divided by 256 to
determine the backplane output frequency. The resistor
value (R) must be at least 30KW for proper self-oscillator
operation.
C
R
÷ 256
Q
LCDØ
LCDØ
OPT
TO BACKPLANE
TRANSLATOR
AND DRIVER
For displays having a number of segments greater than 38,
two or more of the display drivers may be cascaded together
by connecting the serial data output (DOUT) from the first
driver, to the serial data input (DIN) of the following driver,
etc.(See Figures 2 & 3). Data out (DOUT) will change state
Figure 1.
TIMING DIAGRAM
CL
INPUT
tCL
DIN
INPUT
VALID
tDS
tDH
CS
INPUT
tCSS
tLCS
tCSL
tCSH
LD
INPUT
tLS
tCDO
DOUT
OUTPUT
VALID
HOLT INTEGRATED CIRCUITS
3-10
tLW
VALID
HI-8020/HI-8120 Series
Voltages referenced to VSS = 0V
Supply Voltage
VDD........................ 0V to 7V
VEE................VDD-35V to 0V
Voltage at any input, except LCDØ..-0.3 to VDD+0.3V
Voltage at LCDØ input...............VDD-35 to VDD+0.3V
DC Current any input pin...................................10 mA
Power Dissipation......................................................300 mW
Operating Temperature Range - Industrial........-40° to +85°C
Operating Temperature Range - Hi-Temp/Mil..-55° to +125°C
Storage Temperature Range...........................-65° to +150°C
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
CONDITION
MIN
3.0
TYP
MAX
UNITS
7.0
V
Operating Voltage
VDD
Supply Current
IDD
Static, No Load
200
µA
IEE
Static, No Load fBP=100Hz
150
µA
Input Low Voltage, HI-8020 (except LCDØ)
VILTTL
0
0.8
V
Input High Voltage, HI-8020 (except LCDØ)
VIHTTL
2
VDD
V
Input Low Voltage, HI-8120 (except LCDØ)
VILCMOS
0
0.3 VDD
V
Input High Voltage, HI-8120 (except LCDØ)
VIHCMOS
0.7 VDD
VDD
V
Input Low Voltage (LCDØ)
VILX
VEE
3
V
Input High Voltage (LCDØ)
VIHX
3.5
VDD
V
1
µA
5
pF
Input Current
IIN
Input Capacitance (not tested)
CI
VIN = 0 to 5V
RSEG
IL = 10µA
10,000
W
Backplane Output Impedance
RBP
IL = 10µA
450
W
Data Out Current:
IDOH
Source Current, VOH = 4.5V
-0.6
mA
IDOL
Sink Current, VOL = 0.5V
Segment Output Impedance
0.6
mA
AC ELECTRICAL CHARACTERISTICS
VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
SYMBOL
VDD
MIN
TYP
MAX
UNITS
Clock Period
tCL
5V
1200
ns
Clock Pulse Width
tCW
5V
520
ns
Data In - Setup
tDS
5V
50
ns
Data In - Hold
tDH
5V
400
ns
Chip Select - Setup to Clock
tCSS
5V
200
ns
Chip Select - Hold to Clock
tCSH
5V
450
ns
Load - Setup to Clock
tLS
5V
500
ns
Chip Select - Setup to Load
tCSL
5V
300
ns
Load Pulse Width
tLW
5V
500
ns
Chip Select - Hold to Load
tLCS
5V
300
Data Out Valid, from Clock
tCDO
5V
HOLT INTEGRATED CIRCUITS
3-11
ns
800
ns
HI-8020/HI-8120 Series
CASCADING - EXT. OSCILLATOR
CASCADING - RC OSCILLATOR
LD
CL
CS
LD
CL
CS
CS
DIN
CL
LD
DOUT
HI-8020J-85
LCDØ
BP
CS
DIN
CL
LD
DOUT
CS
DIN
HI-8020J-85
LCDØ
CL
LD
DOUT
CS
DIN
150KW
HI-8020J-85
BP
LCDØ
BP
CL
LD
DOUT
CS
DIN
CL
LD
DOUT
HI-8120J-85
HI-8120J-85
LCDØ
LCDØ
BP
LCDØ OPT
CS
DIN
CL
LD
DOUT
HI-8120J-85
BP
LCDØ
BP
LCDØ OPT
LCDØ OPT
470pf
SEGMENTS
1 - 33
SEGMENTS BACK
33 - 64
PLANE
SEGMENTS
1 - 32
SEGMENTS
65 - 96
Figure 2
SEGMENTS BACK
PLANE
33 - 64
SEGMENTS
65 - 96
Figure 3
PIN DESCRIPTIONS
SYMBOL
FUNCTION
VSS
POWER
DESCRIPTION
CS
INPUT
Logic input
Chip select
0 Volts
CL
INPUT
Logic input
Clocks shift register on negative edge and DOUT pins on positive edge
LD
INPUT
Logic input
Segment outputs equal shift register data if Load is high
DIN
INPUT
Logic input
Shift register data input
LCD0
INPUT
Analog input
Display clock input and is always bonded out. Can swing from VEE to VDD
LCD0OPT
OUTPUT
Analog output
Bonded out only if an RC oscillator is required
VDD
POWER
5 Volts
VEE
POWER
O Volts to -30 Volts
DOUT
OUTPUT
Logic output
Selected pinout can provide shift register taps at positions 30, 32, 34, or 38
BP
OUTPUT
Display drive output
Low resistance drive for the backplane and swings from VDD to VEE
Segments
OUTPUT
Display drive output
High resistance drive for each segment and swings from VDD to VEE
ADDITIONAL HI-8020/HI-8120 PIN CONFIGURATIONS
(See page 3-9 for 44-Pin Plastic PLCC)
S17
S18
S19
BP
DOUT 38
S20
S21
S22
S23
S24
S25
S26
8
9
10
11
12
13
HI-8020S-61
HI-8120S-61
HI-8020SM-62
&
HI-8120SM-62
14
15
16
17
18
35
S5
S4
S3
S2
S1
S38
S37
VDD
34
LCDØ/LCDØOPT
33
DIN
LD
CL
42
7
48 - PIN
CERAMIC
LCC
41
40
39
38
37
36
32
S17
S18
S19
BP
DOUT 38
S20
S21
S22
S23
S24
S25
S26
42
7
8
9
10
11
12
13
HI-8020S-63
HI-8120S-63
HI-8020SM-64
&
HI-8120SM-64
16
17
18
HOLT INTEGRATED CIRCUITS
3-12
40
39
38
37
36
35
14
15
41
48 - PIN
CERAMIC
LCC
34
33
32
S5
S4
S3
S2
S1
S38
S37
VDD
LCDØ
DIN
LD
CL
HI-8020/HI-8120 Series
ORDERING INFORMATION
PART
NUMBER OF
MASTER
PACKAGE
TEMPERATURE
NUMBER
SEGMENTS
/SLAVE
DESCRIPTION
RANGE
BURN
LEAD
FLOW
IN
FINISH
I
I
NO
NO
SOLDER
GOLD
TTL Input Logic
HI-8020J-85
HI-8020S-61
32
38
BOTH
44 PIN PLASTIC J LEAD
MASTER 48 PIN CERAMIC LEADLESS CHIP CARRIER
-40°C TO +85°C
-40°C TO +85°C
HI-8020SM-62
HI-8020S-63
HI-8020SM-64
38
38
38
MASTER 48 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C
SLAVE 48 PIN CERAMIC LEADLESS CHIP CARRIER -40°C TO +85°C
SLAVE 48 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C
M
I
M
YES
NO
YES
SOLDER
GOLD
SOLDER
HI-8120J-85
HI-8120S-61
HI-8120SM-62
HI-8120S-63
32
38
38
38
BOTH
MASTER
MASTER
SLAVE
44 PIN PLASTIC J LEAD
-40°C TO +85°C
48 PIN CERAMIC LEADLESS CHIP CARRIER -40°C TO +85°C
48 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C
48 PIN CERAMIC LEADLESS CHIP CARRIER -40°C TO +85°C
I
I
M
I
NO
NO
YES
NO
SOLDER
GOLD
SOLDER
GOLD
HI-8120SM-64
38
SLAVE
48 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C
M
YES
SOLDER
CMOS Input Logic
SEMI-CUSTOM PACKAGING
The above part numbers represent some of the typical configurations of the HI-8020 & HI-8120 products. They can also be provided
with a varied number of output segments (30, 32 and 38), with either industrial or military screening and in a wide variety of packages.
Listed below are currently available packages. Please contact the Holt Sales Department for your specific requirements.
PACKAGE
DESCRIPTION
NO.
LEADS
PLASTIC DUAL-IN-LINE (PDIP)
40
48
PLASTIC QUAD FLAT PACK (PQFP)
52
PLASTIC J-LEAD CHIP CARRIER (PLCC)
44
CERAMIC DUAL-IN-LINE (CDIP)
40
48
CERAMIC LEADLESS CHIP CARRIER (LCC)
40
48
CERAMIC J-LEAD CHIP CARRIER
44
48
CERAMIC LEADED CHIP CARRIER
40
48
HOLT INTEGRATED CIRCUITS
3-13
HI-8020/HI-8120 PACKAGE DIMENSIONS
inches (millimeters)
44-PIN PLASTIC PLCC
Package Type: 44J
PIN NO. 1
PIN NO. 1 IDENT
.045 x 45°
.045 x 45°
.050 ± .005
(1.27 ± .127)
.690 ± .005
(17.526 ± .127)
SQ.
.653 ± .004
(16.586 ± .102)
SQ.
.031± .005
(.787 ± .127)
.017 ± .004
(.432 ± .102)
SEE DETAIL
A
.009
.011
.015 ± .002
(.381 ± .051)
.172 ± .008
(4.369 ± .203)
DETAIL A
.610 ± .020
(15.494± .508)
.020 MIN
(.508 ΜΙΝ)
R .025
.045
48-PIN CERAMIC LEADLESS CHIP CARRIER
Package Type: 48S
PIN 1 IDENT.
.090 MAX.
(2.286 MAX.)
.040 ± .007
(1.016 ± .178)
PIN 1 IDENT.
.563 ± .009
(14.300 ± .228)
SQ.
.020 TYP.
(.508 TYP.)
HOLT INTEGRATED CIRCUITS
1
.040 TYP.
(1.016 TYP.)
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