Renesas HIP2100IBZ 100v/2a peak, low cost, high frequency half bridge driver Datasheet

DATASHEET
HIP2100
FN4022
Rev 15.00
August 31, 2015
100V/2A Peak, Low Cost, High Frequency Half Bridge Driver
The HIP2100 is a high frequency, 100V Half Bridge
N-Channel power MOSFET driver IC. The low-side and
high-side gate drivers are independently controlled and
matched to 8ns. This gives the user maximum flexibility in
dead-time selection and driver protocol. Undervoltage
protection on both the low-side and high-side supplies force
the outputs low. An on-chip diode eliminates the discrete
diode required with other driver ICs. A new level-shifter
topology yields the low-power benefits of pulsed operation
with the safety of DC operation. Unlike some competitors,
the high-side output returns to its correct state after a
momentary undervoltage of the high-side supply.
Features
• Drives N-Channel MOSFET Half Bridge
• SOIC, EPSOIC, QFN and DFN Package Options
• SOIC, EPSOIC and DFN Packages Compliant with 100V
Conductor Spacing Guidelines of IPC-2221
• Pb-Free Product Available (RoHS Compliant)
• Bootstrap Supply Max Voltage to 114VDC
• On-Chip 1 Bootstrap Diode
• Fast Propagation Times for Multi-MHz Circuits
• Drives 1000pF Load with Rise and Fall Times Typ. 10ns
Applications
• CMOS Input Thresholds for Improved Noise Immunity
• Telecom Half Bridge Power Supplies
• Independent Inputs for Non-Half Bridge Topologies
• Avionics DC/DC Converters
• No Start-Up Problems
• Two-Switch Forward Converters
• Outputs Unaffected by Supply Glitches, HS Ringing Below
Ground, or HS Slewing at High dv/dt
• Active Clamp Forward Converters
• Low Power Consumption
• Wide Supply Range
• Supply Undervoltage Protection
• 3 Driver Output Resistance
• QFN/DFN Package:
- Compliant to JEDEC PUB95 MO-220
QFN - Quad Flat No Leads - Package Outline
- Near Chip Scale Package Footprint, which Improves
PCB Efficiency and has a Thinner Profile
-
Ordering Information
PART NUMBER
(Note 1)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
PKG.
DWG. #
HIP2100IB (No longer available,
recommended replacements: HIP2100IBZ, HIP2100IBZT)
2100 IB
-40 to +125
8 Ld SOIC
M8.15
HIP2100IBZ (Note 2)
2100 IBZ
-40 to +125
8 Ld SOIC (Pb-free)
M8.15
HIP2100EIBZ (Note 2)
2100 EIBZ
-40 to +125
8 Ld EPSOIC (Pb-free)
M8.15C
HIP2100IRZ (Note 2)
HIP 2100IRZ
-40 to +125
16 Ld 5x5 QFN (Pb-free)
L16.5x5
HIP2100IR4Z (Note 2) (No longer available,
recommended replacements: HIP2100IRZ, HIP2100IRZT)
21 00IR4Z
-40 to +125
12 Ld 4x4 DFN (Pb-free)
L12.4x4A
NOTES:
1. Add “T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
FN4022 Rev 15.00
August 31, 2015
Page 1 of 13
HIP2100
Pinouts
3
HS
4
6
LI
5
HI
NOTE: EPAD = Exposed PAD.
NC
2
11 VSS
NC
3
EPAD O
E
ABL
VAIL
HOGE5R A
LON
NO HS 6
HB
4
D)
RTE
10
NC
PO
P
U
RS
NC
12 LO
LO
1
16
15
14
13
NC 1
12 NC
9
NC
HB 2
8
LI
HO 3
10 LI
7
HI
NC 4
9
11 VSS
EPAD
5
6
7
NC
8
NC
HO
VDD
HI
VSS
VDD
LO
7
HS
8
2
NC
1
HB
NC
VDD
EPAD
HIP2100
(16 LD QFN)
TOP VIEW
HIP2100IR4
(12 LD DFN)
TOP VIEW
HIP2100
(8 LD SOIC, EPSOIC)
TOP VIEW
Application Block Diagram
+12V
+100V
SECONDARY
CIRCUIT
VDD
HB
DRIVE
HI
PWM
CONTROLLER
LI
CONTROL
HI
HS
DRIVE
LO
HIP2100
VSS
FN4022 Rev 15.00
August 31, 2015
HO
LO
REFERENCE
AND
ISOLATION
Page 2 of 13
HIP2100
Functional Block Diagram
HB
VDD
UNDER
VOLTAGE
HO
LEVEL SHIFT
DRIVER
HS
HI
UNDER
VOLTAGE
LO
DRIVER
LI
VSS
EPAD (EPSOIC, QFN and DFN PACKAGES ONLY)
*EPAD = Exposed Pad. The EPAD is electrically isolated from all other pins. For best
thermal performance connect the EPAD to the PCB power ground plane.
+48V
+12V
PWM
HIP2100
SECONDARY
CIRCUIT
ISOLATION
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
+48V
SECONDARY
CIRCUIT
+12V
PWM
HIP2100
ISOLATION
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP
FN4022 Rev 15.00
August 31, 2015
Page 3 of 13
HIP2100
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VDD, VHB-VHS (Notes 3, 4) . . . . . . . . -0.3V to 18V
LI and HI Voltages (Note 4) . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Voltage on LO (Note 4) . . . . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V
Voltage on HO (Note 4) . . . . . . . . . . . . . . . VHS -0.3V to VHB +0.3V
Voltage on HS (Continuous) (Note 4) . . . . . . . . . . . . . . -1V to 110V
Voltage on HB (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +118V
Average Current in VDD to HB diode . . . . . . . . . . . . . . . . . . . 100mA
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 (1kV)
Thermal Resistance (Typical)
Maximum Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . +9V to 14.0VDC
Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to 100V
Voltage on HS. . . . . . . . . . . . . . . .(Repetitive Transient) -5V to 105V
Voltage on HB . . . VHS +8V to VHS +14.0V and VDD -1V to VDD +100V
HS Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <50V/ns
JA (°C/W)
JC (°C/W)
SOIC (Note 5) . . . . . . . . . . . . . . . . . . .
95
50
EPSOIC (Note 6) . . . . . . . . . . . . . . . . .
40
3.0
QFN (Note 6) . . . . . . . . . . . . . . . . . . . .
37
6.5
DFN (Note 6) . . . . . . . . . . . . . . . . . . . .
40
3.0
Max Power Dissipation at +25°C in Free Air (SOIC, Note 5) . . . . 1.3W
Max Power Dissipation at +25°C in Free Air (EPSOIC, Note 6) . . 3.1W
Max Power Dissipation at +25°C in Free Air (QFN, Note 6) . . . . . 3.3W
Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3. The HIP2100 is capable of derated operation at supply voltages exceeding 14V. Figure 16 shows the high-side voltage derating curve for this
mode of operation.
4. All voltages referenced to VSS unless otherwise specified.
5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. JC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified.
TJ = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN TYP MAX
TJ = -40°C TO +125°C
MIN
(Note 7)
MAX
(Note 7)
UNITS
SUPPLY CURRENTS
VDD Quiescent Current
IDD
LI = HI = 0V
-
0.1
0.15
-
0.2
mA
VDD Operating Current
IDDO
f = 500kHz
-
1.5
2.5
-
3
mA
Total HB Quiescent Current
IHB
LI = HI = 0V
-
0.1
0.15
-
0.2
mA
Total HB Operating Current
IHBO
f = 500kHz
-
1.5
2.5
-
3
mA
HB to VSS Current, Quiescent
IHBS
VHS = VHB = 114V
-
0.05
1
-
10
µA
HB to VSS Current, Operating
IHBSO
f = 500kHz
-
0.7
-
-
-
mA
INPUT PINS
Low Level Input Voltage Threshold
VIL
4
5.4
-
3
-
V
High Level Input Voltage Threshold
VIH
-
5.8
7
-
8
V
VIHYS
-
0.4
-
-
-
V
RI
-
200
-
100
500
k
VDD Rising Threshold
VDDR
7
7.3
7.8
6.5
8
V
VDD Threshold Hysteresis
VDDH
-
0.5
-
-
-
V
HB Rising Threshold
VHBR
6.5
6.9
7.5
6
8
V
HB Threshold Hysteresis
VHBH
-
0.4
-
-
-
V
Input Voltage Hysteresis
Input Pulldown Resistance
UNDERVOLTAGE PROTECTION
FN4022 Rev 15.00
August 31, 2015
Page 4 of 13
HIP2100
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified. (Continued)
TJ = +25°C
PARAMETERS
SYMBOL
TEST CONDITIONS
TJ = -40°C TO +125°C
MIN TYP MAX
MIN
(Note 7)
MAX
(Note 7)
UNITS
BOOT STRAP DIODE
Low-Current Forward Voltage
VDL
IVDD-HB = 100µA
-
0.45 0.55
-
0.7
V
High-Current Forward Voltage
VDH
IVDD-HB = 100mA
-
0.7
0.8
-
1
V
RD
IVDD-HB = 100mA
-
0.8
1
-
1.5

Dynamic Resistance
LO GATE DRIVER
Low Level Output Voltage
VOLL
ILO = 100mA
-
0.25
0.3
-
0.4
V
High Level Output Voltage
VOHL
ILO = -100mA, VOHL = VDD-VLO
-
0.25
0.3
-
0.4
V
Peak Pullup Current
IOHL
VLO = 0V
-
2
-
-
-
A
Peak Pulldown Current
IOLL
VLO = 12V
-
2
-
-
-
A
Low Level Output Voltage
VOLH
IHO = 100mA
-
0.25
0.3
-
0.4
V
High Level Output Voltage
VOHH
IHO = -100mA, VOHH = VHB-VHO
-
0.25
0.3
-
0.4
V
Peak Pullup Current
IOHH
VHO = 0V
-
2
-
-
-
A
Peak Pulldown Current
IOLH
VHO = 12V
-
2
-
-
-
A
HO GATE DRIVER
Switching Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified.
TJ = +25°C
PARAMETERS
SYMBOL
TEST
CONDITIONS
MIN TYP MAX
TJ = -40°C TO +125°C
MIN
(Note 7)
MAX
(Note 7)
UNITS
Lower Turn-Off Propagation Delay (LI Falling to LO Falling)
tLPHL
-
20
35
-
45
ns
Upper Turn-Off Propagation Delay (HI Falling to HO Falling)
tHPHL
-
20
35
-
45
ns
Lower Turn-On Propagation Delay (LI Rising to LO Rising)
tLPLH
-
20
35
-
45
ns
Upper Turn-On Propagation Delay (HI Rising to HO Rising)
tHPLH
-
20
35
-
45
ns
Delay Matching: Lower Turn-On and Upper Turn-Off
tMON
-
2
8
-
10
ns
Delay Matching: Lower Turn-Off and Upper Turn-On
tMOFF
-
2
8
-
10
ns
CL = 1000pF
-
10
-
-
-
ns
CL = 0.1µF
-
0.5
0.6
-
0.8
µs
Either Output Rise/Fall Time
tRC, tFC
Either Output Rise/Fall Time (3V to 9V)
tR, tF
Either Output Rise Time Driving DMOS
tRD
CL = IRFR120
-
20
-
-
-
ns
Either Output Fall Time Driving DMOS
tFD
CL = IRFR120
-
10
-
-
-
ns
Minimum Input Pulse Width that Changes the Output
tPW
-
-
-
-
50
ns
Bootstrap Diode Turn-On or Turn-Off Time
tBS
-
10
-
-
-
ns
NOTE:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
FN4022 Rev 15.00
August 31, 2015
Page 5 of 13
HIP2100
Pin Descriptions
SYMBOL
DESCRIPTION
VDD
Positive Supply to lower gate drivers. De-couple this pin to VSS. Bootstrap diode connected to HB.
HB
High-Side Bootstrap supply. External bootstrap capacitor is required. Connect positive side of bootstrap capacitor to this pin.
Bootstrap diode is on-chip.
HO
High-Side Output. Connect to gate of High-Side power MOSFET.
HS
High-Side Source connection. Connect to source of High-Side power MOSFET. Connect negative side of bootstrap capacitor to
this pin.
HI
High-Side input.
LI
Low-Side input.
VSS
Chip negative supply, generally will be ground.
LO
Low-Side Output. Connect to gate of Low-Side power MOSFET.
EPAD
Exposed Pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
Timing Diagrams
LI
HI
HI,
LI
tHPLH ,
tLPLH
tHPHL,
tLPHL
LO
tMOFF
tMON
HO,
LO
HO
FIGURE 3.
FIGURE 4.
10
10
1
1
0.1
0.01
10k
T = +150°C
T = +125°C
T = +25°C
T = -40°C
100k
FREQUENCY (Hz)
FIGURE 5. OPERATING CURRENT vs FREQUENCY
FN4022 Rev 15.00
August 31, 2015
IHBSO (mA)
IDDO, IHBO (mA)
Typical Performance Curves
T = +150°C
T = -40°C
T = +125°C
T = +25°C
0.1
1M
0.01
10k
100k
FREQUENCY (Hz)
1M
FIGURE 6. HB TO VSS OPERATING CURRENT vs
FREQUENCY
Page 6 of 13
HIP2100
Typical Performance Curves
(Continued)
500
500
VHB = VDD = 9V
VHB = VDD = 9V
VHB = VDD = 12V
400
VHB = VDD = 14V
VOLL, VOLH (mV)
VOHL, VOHH (mV)
400
300
200
100
-50
VHB = VDD = 12V
VHB = VDD = 14V
300
200
0
50
100
100
-50
150
0
50
TEMPERATURE (°C)
FIGURE 7. HIGH LEVEL OUTPUT VOLTAGE vs TEMPERATURE
0.54
0.50
VDDR
VHBH, VDDH (mV)
VHBR, VDDR (V)
7.4
7.2
7.0
VHBR
VDDH
0.46
0.42
0.38
VHBH
6.8
0.34
0
50
TEMPERATURE (°C)
100
0.30
-50
150
0
50
TEMPERATURE (°C)
100
150
FIGURE 10. UNDERVOLTAGE LOCKOUT HYSTERESIS vs
TEMPERATURE
FIGURE 9. UNDERVOLTAGE LOCKOUT THRESHOLD vs
TEMPERATURE
2.5
30
tHPHL
2.0
tHPLH
tLPHL
25
tLPLH
IHO , ILO (A)
tLPLH, tLPHL, tHPLH, tHPHL (ns)
150
FIGURE 8. LOW LEVEL OUTPUT VOLTAGE vs TEMPERATURE
7.6
6.6
-50
100
TEMPERATURE (°C)
1.5
1.0
20
0.5
15
-50
0
0
50
TEMPERATURE (°C)
100
FIGURE 11. PROPAGATION DELAYS vs TEMPERATURE
FN4022 Rev 15.00
August 31, 2015
150
0
2
4
6
VHO , VLO (V)
8
10
12
FIGURE 12. PEAK PULLUP CURRENT vs OUTPUT VOLTAGE
Page 7 of 13
HIP2100
(Continued)
2.5
1.000
2.0
0.100
FORWARD CURRENT (A)
ILO, IHO (A)
Typical Performance Curves
1.5
1.0
0.5
0
0
2
4
6
8
10
12
0.010
0.001
1·10-4
1·10-5
1·10-6
0.3
FIGURE 13. PEAK PULLDOWN CURRENT vs OUTPUT
VOLTAGE
60
0.6
0.7
0.8
FIGURE 14. BOOTSTRAP DIODE I-V CHARACTERISTICS
100
VHS TO VSS VOLTAGE (V)
IHB vs VHB
IDD , IHB (µA)
0.5
120
50
40
IDD vs VDD
30
20
10
0
0.4
FORWARD VOLTAGE (V)
VLO, VHO (V)
0
5
10
VDD , VHB (V)
15
FIGURE 15. QUIESCENT CURRENT vs VOLTAGE
FN4022 Rev 15.00
August 31, 2015
80
60
40
20
0
12
14
15
VDD TO VSS VOLTAGE (V)
FIGURE 16. VHS VOLTAGE vs VDD VOLTAGE
Page 8 of 13
16
HIP2100
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
August 31, 2015
FN4022.15
CHANGE
Updated Ordering Information Table on page 1.
Added Revision History and About Intersil sections.
Updated POD M8.15 from rev 1 to rev 4. Changes since rev 1:
Updated to new format by removing table, moving dimensions onto drawing and adding land pattern
Typical Recommended Land Pattern, changed the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
Changed Note 1 "1982" to "1994"
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
© Copyright Intersil Americas LLC 2004-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN4022 Rev 15.00
August 31, 2015
Page 9 of 13
HIP2100
Dual Flat No-Lead Plastic Package (DFN)
Micro Lead Frame Plastic Package (MLFP)
L12.4x4A
12 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
SYMBOL
2X
0.15
A
C
D
A
D/2
D1
0.15
E1/2
E1
INDEX
AREA
0.15
B
0.15
C
E
B
0.90
-
0.05
-
A2
-
0.65
0.70
-
TOP VIEW
4X 0
A2
A
//
A1
A3
SIDE VIEW
C
0.10
0.08
C
0.20 REF
0.18
D
C
0.23
0.30
5, 8
4.00 BSC
-
3.75 BSC
2.65
2.80
2.95
7, 8
E
4.00 BSC
-
E1
3.75 BSC
-
1.43
e
2X
SEATING
PLANE
0.85
0.01
E2
1 2 3
A
-
D2
9
C
B
NOTES
0.00
D1
E/2
6
C
MAX
A
b
2X
N
NOMINAL
A1
A3
D1/2
2X
MIN
1.58
1.73
7, 8
0.50 BSC
-
k
0.635
-
-
-
L
0.30
0.40
0.50
8
N
12
2
Nd
6
3
P
0.24
0.42
0.60
-

-
-
12
Rev. 0 8/03
7
8
NOTES:
D2
1. Dimensioning and tolerancing conform to ASME Y14.5M-1994.
(Nd-1)Xe
REF.
2. N is the number of terminals.
D2/2
1
3. Nd refer to the number of terminals on D.
2 3
4. All dimensions are in millimeters. Angles are in degrees.
6
INDEX
AREA
E2
7
8
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
NX k
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
E2/2
4X P
N N-1
NX b
0.10
e
5
M
C A B
BOTTOM VIEW
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. COMPLIANT TO JEDEC MO-229-VGGD-2 ISSUE C except for
the L dimension.
CL
NX b
A1
L
5
C C
5
TERMINAL TIP
e
FOR EVEN TERMINAL/SIDE
FN4022 Rev 15.00
August 31, 2015
Page 10 of 13
HIP2100
Quad Flat No-Lead Plastic Package (QFN)
Micro Lead Frame Plastic Package (MLFP)
L16.5x5
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHB ISSUE C)
MILLIMETERS
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.80
0.90
1.00
-
A1
-
-
0.05
-
A2
-
-
1.00
9
A3
b
0.20 REF
0.28
D
0.40
5, 8
5.00 BSC
D1
D2
0.33
9
-
4.75 BSC
2.55
2.70
9
2.85
7, 8
E
5.00 BSC
-
E1
4.75 BSC
9
E2
2.55
e
2.70
2.85
7, 8
0.80 BSC
-
k
0.25
-
-
-
L
0.35
0.60
0.75
8
L1
-
-
0.15
10
N
16
Nd
2
4
3
Ne
4
4
3
P
-
-
0.60
9

-
-
12
9
Rev. 2 10/02
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P &  are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.
FN4022 Rev 15.00
August 31, 2015
Page 11 of 13
HIP2100
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
6.20 (0.244)
5.80 (0.228)
AREA
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
1
2
8°
0°
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
SEATING PLANE
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
1
8
2
7
0.60 (0.023)
1.27 (0.050)
3
6
4
5
-C-
1.27 (0.050)
0.51(0.020)
0.33(0.013)
SIDE VIEW “A
0.25(0.010)
0.10(0.004)
5.20(0.205)
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN4022 Rev 15.00
August 31, 2015
Page 12 of 13
HIP2100
Small Outline Exposed Pad Plastic Packages (EPSOIC)
M8.15C
N
INDEX
AREA
H
0.25(0.010) M
8 LEAD NARROW BODY SMALL OUTLINE EXPOSED PAD
PLASTIC PACKAGE
B M
E
INCHES
-B-
1
2
SYMBOL
3
TOP VIEW
L
SEATING PLANE
-A-
A
D
-C-
e
A1
B
0.25(0.010) M

C
0.10(0.004)
C A M
SIDE VIEW
B S
MILLIMETERS
MAX
MIN
MAX
NOTES
A
0.056
0.066
1.43
1.68
-
A1
0.001
0.005
0.03
0.13
-
B
0.0138
0.0192
0.35
0.49
9
C
0.0075
0.0098
0.19
0.25
-
D
0.189
0.196
4.80
4.98
3
E
0.150
0.157
3.811
3.99
4
e
h x 45°
MIN
0.050 BSC
1.27 BSC
-
H
0.230
0.244
5.84
6.20
-
h
0.010
0.016
0.25
0.41
5
L
0.016
0.035
0.41
0.89
6
8°
0°
N

8
0°
8
7
8°
-
P
-
0.126
-
3.200
11
P1
-
0.099
-
2.514
11
Rev. 1 6/05
NOTES:
1
2
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
3
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
P1
N
P
BOTTOM VIEW
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch
dimensions are not necessarily exact.
11. Dimensions “P” and “P1” are thermal and/or electrical enhanced
variations. Values shown are maximum size of exposed pad
within lead count and body size.
FN4022 Rev 15.00
August 31, 2015
Page 13 of 13
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