D at a S he e t, R ev . 0 .8 5 , Ap r . 2 00 4 H YS72 T 640 00 [G/H ]R - x -A (5 12 M B y t e ) H YS72 T 128 00 0[ G/H] R-x-A ( 1 G B y t e ) H YS72 T 128 02 0[ G/H] R-x-A ( 1 G B y t e ) H YS72 T 256 02 0[ G/H] R-x-A ( 2 G B y t e ) H YS72 T 256 22 0[ G/H] R-x-A ( 2 G B y t e ) DDR 2 Reg istered Me mo ry Mo dul es M em or y P r od uc t s N e v e r s t o p t h i n k i n g . HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Preliminary Data Sheet Rev. 0.85 (Apr. 2004) Low Profile 240-pin Registered DDR2 SDRAM Modules Datasheet 512 MByte, 1 GByte & 2 GByte Modules PC2-3200R, PC2-4300R • Programmable CAS Latencies (3, 4 & 5), Burst Length (4 & 8) and Burst Type. • 240-pin Registered 8-Byte ECC Dual-In-Line DDR2 SDRAM Module for PC, Workstation and Server main memory applications • Auto Refresh and Self Refresh • One rank 64Mb x 72, 128Mb x 72 and two ranks 128Mb × 72 and 256Mb x 72 organizations • All inputs and outputs SSTL_1.8 compatible • Re-drive for all input signals using register and PLL devices. • JEDEC standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAMs) with + 1.8 V (± 0.1 V) power supply • OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) • Serial Presence Detect with E2PROM • 512MB and 1 GB modulesModules built with 512Mb DDR2 SDRAMs in 60-ball FBGA chipsize packages • Low Profile Modules form factor: 133.35 mm x 30,00 mm (MO-237) • Two versions of 2 GB modules • Based on JEDEC standard reference card designs built with 63-ball FBGA dual die chipsize packages (2 x 512Mb components) or 60-ball FBGA packages Performance: –5 –3.7 Component Speed Grade on Module Speed Grade Indicator DDR2–400 DDR2–533 Module Speed Grade Unit PC2–3200R PC2–4300R Max. Clock Frequency @ CL = 3 200 200 MHz Max. Clock Frequency@ CL = 4 & 5 200 266 MHz 1.0 Description The INFINEON HYS72Taaabcd[G/H]R module family are low profile Registered DIMM modules with 30,00 mm height based on DDR2 technology. DIMMs are available in 64M x 72 (512MByte), 128M x 72 (1GByte) and 256M x 72 (2GByte) organisation and density, intended for mounting into 240 pin connector sockets. The memory array is designed with 512Mb Double Data Rate (DDR2) Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board, which provide a proper voltage supply impedance over the whole frequency range of operations as number and values are accordant to the JEDEC specification. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. 2 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 1.1 Ordering Information Product Type Compliance Code Description SDRAM Technology PC2-3200 (DDR2-400) HYS72T64000GR-5-A PC2-3200R-333-11-A one rank 512 MB Reg. DIMM HYS72T128020GR-5-A PC2-3200R-333-11-B two ranks 1024 MB Reg.DIMM 512 Mbit (x8) 512 Mbit (x8) HYS72T128000GR-5-A PC2-3200R-333-11-C one rank 1024 MB Reg. DIMM 512 Mbit (x4) HYS72T256220GR-5-A PC2-3200R-333-11 two ranks 2048 MB Reg. DIMM 512 Mbit (x4) HYS72T256020GR-5-A PC2-3200R-333-11 two ranks 2048 MB Reg. DIMM 512 Mbit (x4) HYS72T64000GR-3.7-A PC2-4300R-444-11-A one rank 512 MB Reg. DIMM 512 Mbit (x8) HYS72T128020GR-3.7-A PC2-4300R-444-11-B two ranks 1024 MB Reg.DIMM 512 Mbit (x8) HYS72T128000GR-3.7-A PC2-4300R-444-11-C one rank 1024 MB Reg. DIMM 512 Mbit (x4) HYS72T256020GR-3.7-A PC2-4300R-444-11 two ranks 2048 MB Reg. DIMM 512 Mbit (x4) PC2-4300 (DDR2-533) PC2-3200 (DDR2-400) HYS72T64000HR-5-A PC2-3200R-333-11-A one rank 512 MB Reg. DIMM 512 Mbit (x8) HYS72T128020HR-5-A PC2-3200R-333-11-B two ranks 1024 MB Reg.DIMM 512 Mbit (x8) HYS72T128000HR-5-A PC2-3200R-333-11-C one rank 1024 MB Reg. DIMM 512 Mbit (x4) HYS72T256220HR-5-A PC2-3200R-333-11 two ranks 2048 MB Reg. DIMM 512 Mbit (x4) HYS72T256020HR-5-A PC2-3200R-333-11 two ranks 2048 MB Reg. DIMM 512 Mbit (x4) HYS72T64000HR-3.7-A PC2-4300R-444-11-A one rank 512 MB Reg. DIMM 512 Mbit (x8) HYS72T128020HR-3.7-A PC2-4300R-444-11-B two ranks 1024 MB Reg.DIMM 512 Mbit (x8) HYS72T128000HR-3.7-A PC2-4300R-444-11-C one rank 1024 MB Reg. DIMM 512 Mbit (x4) HYS72T256020HR-3.7-A PC2-4300R-444-11 two ranks 2048 MB Reg. DIMM 512 Mbit (x4) PC2-4300 (DDR2-533) Notes: 1. For all INFINEON DDR2 module and component nomenclature see section 8 of this data sheet. 2. The Compliance Code is printed on the module label and describes the speed grade, e. g. “PC2-4300R-444-11-C”, where 4300R means Registered modules with 4.26 GB/sec Module Bandwidth and “444-11” means CAS latency = 4, trcd latency = 4 and trp latency = 4 using the latest JEDEC SPD Revision 1.1 and produced on the Raw Card “C”. 1.2 Address Format Product Type DIMM Density Organization DIMM Ranks SDRAMs # of SDRAMs # of row/bank/ column bits HYS72T64000GR HYS72T64000HR 512 MB 64Mb × 72 1 (512Mb) 64Mb × 8 9 14/2/10 HYS72T128020GR HYS72T128020HR 1024 MB 2 x 64Mb × 72 2 (512Mb) 64Mb × 8 18 14/2/10 HYS72T128000GR HYS72T128000HR 1024 MB 128Mb x 72 1 (512Mb) 128Mb × 4 18 14/2/11 HYS72T256220GR HYS72T256220HR 2048 MB 2 x 128Mb × 72 2 (512Mb) 128Mb × 4 36 14/2/11 HYS72T256020GR HYS72T256020HR 2048 MB 2 x 128Mb × 72 2 (512Mb) 128Mb × 4 36 14/2/11 Data Sheet Preliminary 3 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 1.3 Components on Modules and RawCard DIMM Density DRAM components reference datasheet PLL Register Raw Card 512 MB HYB18T512800AC HYB18T512800AF 1:10, 1.8V, CU877 1:1 25-bit 1.8V SSTU32864 A 1024 MB HYB18T512800AC HYB18T512800AF 1:10, 1.8V, CU877 1:2 14-bit 1.8V SSTU32864 B 1024 MB HYB18T512400AC HYB18T512400AF 1:10, 1.8V, CU877 1:2 14-bit 1.8V SSTU32864 C 2048 MB HYB18T512400AC HYB18T512400AF tbd. tbd. tbd. 2048 MB HYB18T512400AC HYB18T512400AF tbd. tbd. tbd. For a detailed description of all functionalities of the DRAM components on these modules see the referenced component data sheet 1.4 Pin Definition and Function Pin Name Description Pin Name Description A[13:0] Row Address Inputs CB[7:0] DIMM ECC Check Bits A11, A[9:0] Column Address Inputs 4) DQS[8:0] SDRAM low data strobes A10/AP Column Address Input for AutoPrecharge DM[8:0] / DQS[17:9] SDRAM low data mask/ high data strobes BA[1:0] SDRAM Bank Selects DQS[17:0] SDRAM differential data strobes CK0 Clock input SCL Serial bus clock SDA Serial bus data line (positive line of differential pair) CK0 Clock input (negative line of differential pair) RAS Row Address Strobe SA[2:0] slave address select CAS Column Address Strobe VDD Power (+ 1.8 V) WE Read/Write Input VREF I/O reference supply CS[1:0] Chip Selects 3) VSS Ground CKE[1:0] Clock Enable 3) VDDSPD EEPROM power supply ODT[1:0] Active termination control lines 1) 3) RESET Register and PLL control pin 2) DQ[63:0] Data Input/Output NC No connection 1) Active termination only applies to DQ, DQS, DQS and DM signals 2) When low, all register outputs will be driven low and the PLL clocks to the DRAM and registers will be set to low levels (the PLL will remain synchronized with the input clock 3) CS1, ODT1 and CKE1 are used on dual rank modules only 4) Column address A11 is used on modules based on x4 organised 512Mb DDR2 components only. Data Sheet Preliminary 4 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 1.5 Pin Configuration PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS RESET NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 Data Sheet Preliminary PIN# 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Symbol VSS DQ4 DQ5 VSS DM0, DQS9 DQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1, DQS10 DQS10 VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2, DQS11 DQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3, DQS12 DQS12 VSS DQ30 DQ31 VSS PIN# 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 5 Symbol A4 VDDQ A2 VDD KEY VSS VSS VDD NC VDD A10/AP BA0 VDDQ WE CAS VDDQ CS1 ODT1 VDDQ VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 PIN# 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 Symbol VDDQ A3 A1 VDD KEY CK0 CK0 VDD A0 VDD BA1 VDDQ RAS CS0 VDDQ ODT0 A13 VDD VSS DQ36 DQ37 VSS DM4, DQS13 DQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5, DQS14 DQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules Pin Configuration (cont’d) PIN# 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Symbol VSS CB0 CB1 VSS DQS8 DQS8 VSS CB2 CB3 VSS VDDQ CKE0 VDD NC NC VDDQ A11 A7 VDD A5 PIN# 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Symbol CB4 CB5 VSS DM8, DQS17 DQS17 VSS CB6 CB7 VSS VDDQ NC, CKE1 VDD NC NC VDDQ A12 A9 VDD A8 A6 PIN# 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Symbol VSS SA2 NC VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL PIN# 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Symbol NC NC VSS DM6, DQS15 DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7, DQS16 DQS16 VSS DQ62 DQ63 VSS VDDSPD SA0 SA1 1.6 Pin Locations Front p in 1 pin 1 21 64 18 4 65 1 85 120 2 40 Backside 240 pin Modules (MO-237) Data Sheet Preliminary 6 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 1.7 Registered DIMM Input/Output Functional Description Symbol Type Polarity Function CK0, CK0 Input The system clock inputs. All address and command lines are sampled on the cross point of Cross point the rising edge of CK and the falling edge of CK. An on-board DLL circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. CKE[1:0] Input CKE high activates and CKE low deactivates internal clock signals and device input buffers Active High and output drivers of the SDRAMs. Taking CKE low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CS[1:0] Input Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled, new commands are ignored and previous operations conActive Low tinue. The input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. When both CS[1:0] are high, all register outputs (except CK, ODT and Chip select) remain in the previous state. ODT[1:0] RAS, CAS, WE Input Active High On-Die Termination control signals Input sampled at the positive edge of the clock, RAS, CAS and WE define the operation to Active Low When be executed by the SDRAM. Input Active High Masks write data when high, issued concurrently with input data. DM[8:0] BA[1:0] A[13:0] DQ[63:0], CB[7:0] - Selects which internal SDRAM memory bank is activated Input - During Bank Activate command cycle, Address defines the row address. During a Read or Write command cycle, Address defines the column address. In addition to the column address, A10(=AP) is used to invoke Auto-Precharge operation at the end of the burst read or write cycle. If AP is high, Auto Precharge is selected and BA[1:0] defines the bank to be precharged. If AP is low, Auto-Precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA[1:0]. If AP is low, BA[1:0] are used to define which bank to precharge. I/O - Data and Check Bit Input /Output pins. Input The data strobes, associated with one data byte, source with data transfer. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode the data strobe is sources by the DDR2 SDRAM and is sent at the leading edge of the Cross point data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately. DQS[17:0], DQS[17:0] I/O SA[2:0] Input - These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range SDA I/O - This bidirectional pin is used to transfer data into and out of the SPD EEPROM. A resistor maybe connected from the SDA bus line to VDDSPD on the system planar to act as a pullup. SCL Input - This signal is used to clock data into the SPD EEPROM. A resistor maybe connected from the SCL bus line to VDDSPD on the system planar to act as a pull-up. RESET Input - The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and the register(s) will be set to low level. The PLL will remain synchronized with the input clock. VDD, VSS Supply - Power and ground for the DDR SDRAM input buffers and core logic. VREF Supply - Reference voltage for the SSTL-18 inputs. VDDSPD Supply - Serial EEPROM positive power supply, wired to a separated power pin at the connector which supports from 1.7 Volt to 3.6 Volt. Note: CS1, ODT1 and CKE1 are used on dual rank modules only. Data Sheet Preliminary 7 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 2.0 Block Diagrams 2.1 One Rank 64M x 72 (512 MByte) DDR2 SDRAM DIMM Module (x8 components) HYS72T64000[G/H] on Raw Card A RS0 DQS0 DQS4 DQS0 DM0/DQS9 DQS4 DM4/DQS13 NU/ RDQS DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O I/O I/O I/O I/O I/O I/O I/O DM/ RDQS 0 1 2 3 4 5 6 7 CS DQS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D0 DQS1 DQS5 DQS1 DM1/DQS10 DQS5 DM5/DQS14 NU/ RDQS DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 I/O I/O I/O I/O I/O I/O I/O I/O DM/ RDQS 0 1 2 3 4 5 6 7 CS DQS DQS DQS2 DQS6 DQS6 DM6/DQS15 NU/ RDQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM/ RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS D2 DQS7 DQS7 DM7/DQS16 NU/ RDQS DM/ RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS I/O I/O I/O I/O I/O I/O I/O I/O DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D3 DM/ RDQS I/O I/O I/O I/O I/O I/O I/O I/O DM/ RDQS 0 1 2 3 4 5 6 7 DQS CS DQS DQS D5 0 1 2 3 4 5 6 7 NU/ RDQS DQS16 CS DQS D4 0 1 2 3 4 5 6 7 NU/ RDQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O I/O I/O I/O I/O I/O I/O I/O DQS15 DQS3 DM3/DQS12 DQS12 NU/ RDQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D1 DM/ RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS14 DQS0 DM2/DQS11 DQS11 NU/ RDQS DQS13 CS DQS DQS D6 DM/ RDQS CS DQS DQS D7 DQS8 DQS8 DM8/DQS17 NU/ RDQS DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 1:1 CS0 * B A 0-BA1 A0 -A13 RAS CAS WE CKE0 ODT0 RESET PCK7 PCK 7 R E G I S T E R I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ RDQS VDDSPD Serial PD Serial PD CS DQS DQS SCL D8 SDA WP A0 RS0 -> C S : SDRAMs D0-D8 RB A0 -RBA1 -> BA 0-BA1 : SDRAMs D0 -D8 RA0 -RA 13-> A0 -A 13: SDR A Ms D0 -D 8 RR A S -> RAS : SD RAMs D0- D 8 RC AS -> C A S: SD RAMs D0-D8 RW E -> WE : SD RAMs D0-D8 RCK E0 -> CKE : SDR A D0-D8 RODT0 -> ODT 0: SDRAMs D0-D8 A1 A2 SA0 SA1 SA2 CK0 CK 0 RESET P L L OE VDD, V DDQ D0 - D8 VREF D0 - D8 V SS D0 - D8 PCK0-PCK6,PCK8,PCK9 PCK0-PCK6,PCK8,PCK9 CK : SDRAMs D0-D8 CK : SDRAMs D0-D8 PCK7 -> CK : Register PCK7 > CK : Register Notes: 1. DQ-to-I/O wiring may be changed within a byte 2. Unless otherwise noted, resistor values are 22 Ohms RST *) CS0 connects to DCS and VDD connects to CSR on the Registers Data Sheet Preliminary 8 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules Block Diagrams (cont’d) 2.2 128M x 72 (1GByte) two rank DDR2 SDRAM DIMM Modules (x8 components) HYS72T128020[G/H] on Raw Card B RS1 RS0 DQS0 DQS4 DQS0 DM0/DQS9 DQS4 DM4/DQS13 NU/ RDQS DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM/ RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS NU/ RDQS I/O I/O I/O I/O I/O I/O I/O I/O D0 DM/ RDQS 0 1 2 3 4 5 6 7 CS DQS DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D9 DQS1 DQS5 DQS1 DM1/DQS10 DQS5 DM5/DQS14 NU/ RDQS DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM/ RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS NU/ RDQS DM/ RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 CS DQS DQS DQS2 DQS6 DQS6 DM6/DQS15 NU/ RDQS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 I/O I/O I/O I/O I/O I/O I/O I/O DM/ RDQS 0 1 2 3 4 5 6 7 CS DQS DQS NU/ RDQS I/O I/O I/O I/O I/O I/O I/O I/O D2 DM/ RDQS 0 1 2 3 4 5 6 7 CS DQS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D11 DQS3 DQS7 DQS7 DM7/DQS16 NU/ RDQS DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 I/O I/O I/O I/O I/O I/O I/O I/O DM/ RDQS 0 1 2 3 4 5 6 7 CS DQS DQS NU/ RDQS DM/ RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 CS DQS DQS NU/ RDQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D12 DM/ RDQS I/O I/O I/O I/O I/O I/O I/O I/O CS DQS DM/ RDQS CS DQS I/O I/O I/O I/O I/O I/O I/O I/O DM/ RDQS DM/ RDQS DM/ RDQS NU/ RDQS I/O I/O I/O I/O I/O I/O I/O I/O D7 CS DQS DQS D14 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS CS DQS DQS D13 0 1 2 3 4 5 6 7 NU/ RDQS DQS D6 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ RDQS 0 1 2 3 4 5 6 7 NU/ RDQS DQS D5 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS16 NU/ RDQS CS DQS DQS D4 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 NU/ RDQS DQS15 DQS3 DM3/DQS12 DQS12 NU/ RDQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D10 DM/ RDQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS14 DQS0 DM2/DQS11 DQS11 NU/ RDQS DQS13 CS DQS DQS D15 DM/ RDQS 0 1 2 3 4 5 6 7 CS DQS DQS D16 DQS8 DQS8 DM0/DQS17 NU/ RDQS DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM/ RDQS CS DQS D8 DQS NU/ RDQS I/O I/O I/O I/O I/O I/O I/O I/O DM/ RDQS 0 1 2 3 4 5 6 7 VDDSPD Serial PD VDD, V DDQ D0 - D17 VREF D0 - D17 CS DQS DQS D17 V SS D0 - D17 Serial PD SCL 1:2 CS0 * CS1 * B A 0-BA1 A0 -A13 RAS CAS WE CKE0 CKE1 ODT0 ODT1 RESET PCK7 PCK 7 R E G I S T E R RS1 -> C S : SDRAMs D9-D17 RB A0 -RBA1 -> B A 0-BA1 : SDRAMs D0-D17 RA0 -RA 13-> A0 -A 13: SDR A Ms D0-D17 RR A S -> RAS : SD RAMs D0-D17 RC AS -> C A S: SD RAMs D0-D17 RW E -> WE : SD RAMs D0-D17 RCK E0 -> CKE :SDRAMs D0-D8 RCK E1 -> CKE :SDRAMs D9-D17 RODT0 -> ODT : SDRAMs D0-D8 SDA WP A0 RS0 -> C S : SDRAMs D0-D8 A1 A2 SA0 SA1 SA2 PCK0-PCK6, PCK8,PCK9 CK 0 CK 0 P L L RESET OE PCK0-PCK6, PCK8,PCK9 CK : SDRAMs D0-D17 CK : SDRAMs D0-D17 : PCK7 -> CK Register PCK7 > CK : Register RODT1 -> ODT : SDRAMs D9-D17 RST DQ-to-I/O wiring may be changed within a byte DQ/DQS/DQS, adress and control resistors are 22 Ohms *) CS0 connects to CRS, CS1 connects to CSR on a Register. CS1 connects to DCS and CS0 connects to CSR on another Register. RESET, PCK7 and PCK7 connect to bother Registers. Other signals connect to one of two Registers. Data Sheet Preliminary 9 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules Block Diagrams (cont’d) 2.3 One Rank 128M x 72 (1 GByte) DDR2 SDRAM DIMM Modules (x4 components) HYS72T128000[G/H] on Raw Card C VSS RS0 DQS0 DQS9 DQS9 DQS0 DM DQ0 DQ1 DQ2 DQ3 I/O 0 I/O 1 I/O 2 I/O 3 CS DQS DM DQS D0 DQS1 DQS0 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 DQ28 DQ29 DQ30 DQ31 I/O 0 I/O 1 I/O 2 I/O 3 DQ36 DQ37 DQ38 DQ39 I/O 0 I/O 1 I/O 2 I/O 3 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 CB4 CB5 CB6 CB7 I/O 0 I/O 1 I/O 2 I/O 3 DQS10 DQS10 DM DQ8 DQ9 DQ10 DQ11 I/O 0 I/O 1 I/O 2 I/O 3 DQ16 DQ17 DQ18 DQ19 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS D1 DM DM CS DQS DQS D2 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS D3 DQS CS DQS DQS D12 DQS13 DQS4 DQS4 DQS13 DM DQ32 DQ33 DQ34 DQ35 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS D4 CS DQS DQS D13 DQS14 DQS14 DQS5 DQS5 DM DQ40 DQ41 DQ42 DQ43 I/O 0 I/O 1 I/O 2 I/O 3 DQ48 DQ49 DQ50 DQ51 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS D5 CS DQS DQS D14 DQS15 DQS15 DQS6 DQS6 DM DM CS DQS DQS D6 CS DQS DQS D15 DQS16 DQS16 DQS7 DQS7 DM DQ56 DQ57 DQ58 DQ59 I/O 0 I/O 1 I/O 2 I/O 3 CB0 CB1 CB2 CB3 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS D7 DQS8 DQS8 CS DQS DQS D16 DQS17 DQS17 DM DM CS DQS DQS D8 Serial PD RS0 -> C S : SDRAMs D0-D17 RB A0 -RBA1 -> BA 0-BA1 : SDRAMs RA0 -RA 13-> A0 -A 13: SDR A Ms D0-D17 RR A S -> RAS : SD RAMs D0-D17 RC AS -> C A S: SD RAMs D0-D17 RW E -> WE : SD RAMs D0-D17 RCK E0 -> CKE :SDRAMs D0-D17 RODT0 -> ODT : SDRAMs D0-D17 SCL SDA WP A0 A1 A2 SA0 SA1 SA2 CK 0 CK 0 RST RESET *) CS0 connects to DCS of Register 1 and CSR of Register 2, CSR of Register 1 and DCS of Register 2 connects to VDD **) RESET, PCK7 and PCK7 connet to both Registers. Other signals connect to one of two Registers. Data Sheet Preliminary CS DQS D11 DQS12 DM DQ24 DQ25 DQ26 DQ27 R E G I S T E R DQS DQS12 DQS3 DQS3 1:2 CS DQS D10 DQS11 DQS11 DQS2 DQS2 CS0 * B A 0-BA1 A0 -A13 RAS CAS WE CKE0 ODT0 RESET PCK7 PCK 7 CS DQS DQS D9 P L L OE CS DQS DQS D17 VDDSPD Serial PD VDD, V DDQ D0 - D17 VREF D0 - D17 V SS PCK0-PCK6, PCK8,PCK9 PCK0-PCK6, PCK8,PCK9 D0 - D17 CK : SDRAMs D0-D17 CK : SDRAMs D0-D17 PCK7 -> CK : Register PCK7 > CK : Register DQ-to-I/O wiring may be changed within per nibble Unless otherwise noted, resistor values are 22 Ohms 10 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules Block Diagrams (cont’d) 2.4 256M x 72 (2 GByte) two rank DDR2 SDRAM DIMM Modules (x4 components) HYS72T256020[G/H] / HYS72T256220[G/H] RS1 VSS RS0 DQS0 DQS9 DQS9 DQS0 DM CS DQS DQS DQ0 DQ1 DQ2 DQ3 I/O 0 I/O 1 I/O 2 I/O 3 D0-0 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS D0-1 DQS1 DQS1 DQ4 DQ5 DQ6 DQ7 I/O 0 I/O 1 I/O 2 I/O 3 DQ12 DQ13 DQ14 DQ15 I/O 0 I/O 1 I/O 2 I/O 3 DQ20 DQ21 DQ22 DQ23 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS D1-0 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS D9-0 DM CS DQS D1-1 DQS2 DQS2 DQS D9-1 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 D10-0 DQS D10-1 DQS11 DQS11 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQ16 DQ17 DQ18 DQ19 DQS D2-0 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS DM CS DQS D2-1 DQS3 DQS3 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 D11-0 DQS D11-1 DQS12 DQS12 DM CS DQS DQ24 DQ25 DQ26 DQ27 I/O 0 I/O 1 I/O 2 I/O 3 DQS D3-0 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQ28 DQ29 DQ30 DQ31 D3-1 DQS4 DQS4 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 D12-0 DQS D12-1 DQS13 DQS13 DM CS DQS DQ32 DQ33 DQ34 DQ35 I/O 0 I/O 1 I/O 2 I/O 3 DQS D4-0 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQ36 DQ37 DQ38 DQ39 D4-1 DQS5 DQS5 DM CS DQS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 D13-0 D13-1 DQS14 DQS14 DM CS DQS DQ40 DQ41 DQ42 DQ43 I/O 0 I/O 1 I/O 2 I/O 3 DQS D5-0 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS DM CS DQS D5-1 DQS6 DQS6 DQ44 DQ45 DQ46 DQ47 I/O 0 I/O 1 I/O 2 I/O 3 DQ52 DQ53 DQ54 DQ55 I/O 0 I/O 1 I/O 2 I/O 3 DQ60 DQ61 DQ62 DQ63 I/O 0 I/O 1 I/O 2 I/O 3 CB4 CB5 CB6 CB7 I/O 0 I/O 1 I/O 2 I/O 3 DM CS DQS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 D14-0 D14-1 DQS15 DQS15 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQ48 DQ49 DQ50 DQ51 DQS D6-0 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS DM CS DQS D6-1 DQS7 DQS7 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 D15-0 DQS D15-1 DQS16 DQS16 DM CS DQS DQ56 DQ57 DQ58 DQ59 I/O 0 I/O 1 I/O 2 I/O 3 DQS D7-0 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS DM CS DQS D7-1 DQS8 DQS8 DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 D16-0 DQS D16-1 DQS17 DQS17 DM CS DQS CB0 CB1 CB2 CB3 I/O 0 I/O 1 I/O 2 I/O 3 DQS D8-0 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS DM CS DQS D8-1 1:2 R E G I S T E R RS0 -> C S : SDRAMs D0-0 ~ D17-0 RS1 -> C S : SDRAMs D0-1 ~ D17-1 RB A0 -RBA1 -> BA 0-BA1 : SDRAMs D0~D17 RA0 -RA 13-> A0 -A 13: SDR A Ms D0~D17 RR A S -> RAS : SD RAMs D0~D17 RC AS -> C A S: SDRAMs D0~D17 RW E -> WE : SDRAMs D0~D17 RCK E0 -> CKE : SDRAMs D0-0 ~ D17-0 RCK E1 -> CKE :SDRAMs D0-1 ~ D17-1 RODT0 -> ODT : SDRAMs D0-0 ~ D17-0 RODT1 -> ODT : SDRAMs D0-1 ~ D17-1 SCL DM CS DQS DQS I/O 0 I/O 1 I/O 2 I/O 3 D17-0 Serial PD RESET PCK7 PCK 7 I/O 0 I/O 1 I/O 2 I/O 3 DQS10 DQS10 DQ8 DQ9 DQ10 DQ11 CS0 * CS1 * B A 0-BA1 A0 -A13 RAS CAS WE CKE0 CKE1 ODT0 ODT1 DM CS DQS DQS DQS D17-1 VDDSPD Serial PD VDD, V DDQ D0 - D17 SDA WP A0 A1 A2 VREF SA0 SA1 SA2 CK 0 CK 0 RESET P L L OE V SS PCK0-PCK6, PCK8,PCK9 PCK0-PCK6, PCK8,PCK9 D0 - D17 D0 - D17 CK : SDRAMs D0-D17 CK : SDRAMs D0-D17 PCK7 -> CK : Register PCK7 > CK : Register Notes: 1. DQ-to-I/O wiring may be changed within a nibble. 2. Unless otherwise noted, resistors values are 22 Ohms RST *) CS0 connects to CRS, CS1 connects to CSR on a Register. CS1 connects to DCS and CS0 connects to CSR on another Register. RESET, PCK7 and PCK7 connect to bother Registers. Other signals connect to one of two Registers. Data Sheet Preliminary 11 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 3.0 Absolute Maximum Ratings Parameter Symbol Limit Values min. max. Unit Voltage on any pins relative to VSS VIN, VOUT – 0.5 2.3 V Voltage on VDD relative to VSS VDD – 1.0 2.3 V Voltage on VDD Q relative to VSS VDDQ – 0.5 2.3 Storage temperature range TSTG -55 +100 o C Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3.1 Operating Temperature Range Parameter Symbol Limit Values min. max. Unit DIMM Module Operating Temperature Range (ambient) TOPR 0 +55 o C DRAM Component Case Temperature Range TCASE 0 +95 o C Notes 1-4 1. DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. Within the DRAM Component Case Temperature range all DRAM specification will be supported. 3. Above 85oC DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs. 4. Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85oC case temperature before initiating self-refresh operation. 3.2 Supply Voltage Levels and DC Operating Conditions Parameter Symbol Limit Values min. nom. Unit Notes max. Device Supply Voltage VDD 1.7 1.8 1.9 V - Output Supply Voltage VDDQ 1.7 1.8 1.9 V 1) Input Reference Voltage VREF 0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V 2) EEPROM Supply Voltage VDDSPD 1.7 – 3.6 V DC Input Logic High VIH (DC) VREF + 0.125 – VDDQ + 0.3 V DC Input Logic Low VIL (DC) – 0.30 – VREF – 0.125 V In / Output Leakage Current IL –5 – 5 µA 1 2 3 3) Under all conditions, VDDQ must be less than or equal to VDD Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise variations in VDDQ. For any pin on the DIMM connector under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V. Data Sheet Preliminary 12 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 4.0 IDD Specifications and Conditions 4.1 512 MByte Registered Module HYS72T64000[G/H] (one rank, nine components x8) 512 MByte HYS72T64000[G/H] PC2-3200R “-5” PC2-4300R “-3.7” max. max. 918 Unit mA Note 745 Symbol Parameter / Condition Operating Current IDD0 1 IDD1 Operating Current 790 1008 mA 1 IDD2P Precharge PD Standby Current 286 369 mA 1 IDD2N Precharge Standby Current 538 639 mA 1 IDD2Q Precharge Quiet Standby Current 475 603 mA 1 IDD3P(0) Active PD Standby Current 367 477 mA 1 IDD3P(1) LP Active PD Standby Current 295 378 mA 1 IDD3N Active Standby Current 565 693 mA 1 IDD4R Operating Current Burst Read 880 1143 mA 1 IDD4W Operating Current Burst Write 925 1188 mA 1 IDD5B Auto-Refresh Current (tRFCmin.) 1330 1503 mA 1 IDD5D Auto-Refresh Current (tREFI) 304 387 mA 1 IDD6 Self-Refresh Current 36 36 mA 1 IDD7 Operating Current 1420 1593 mA 1 Note: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled. Currents includes Registers and PLL. 4.2 1024 MByte Registered Module HYS72T128020[G/H] (two ranks, 18 components x8) 1024 MByte HYS72T128020[G/H] PC2-3200R “-5” Symbol Parameter / Condition Operating Current IDD0 PC2-4300R “-3.7” max. max. 1111 Unit mA Note 899 1, 2 IDD1 Operating Current 944 1201 mA 1, 2 IDD2P Precharge PD Standby Current 440 562 mA 1, 3 IDD2N Precharge Standby Current 944 1210 mA 1, 3 IDD2Q Precharge Quiet Standby Current 818 1030 mA 1, 3 IDD3P(0) Active PD Standby Current 602 778 mA 1, 3 IDD3P(1) LP Active PD Standby Current 458 580 mA 1, 3 IDD3N Active Standby Current 998 1210 mA 1, 3 IDD4R Operating Current Burst Read 1034 1336 mA 1, 2 IDD4W Operating Current Burst Write 1079 1381 mA 1, 2 IDD5B Auto-Refresh Current (tRFCmin.) 1484 1696 mA 1, 2 IDD5D Auto-Refresh Current (tREFI) 476 598 mA 1, 3 IDD6 Self-Refresh Current 72 72 mA 1, 3 IDD7 Operating Current 1574 1786 mA 1, 2 Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled. Currents includes Registers and PLL. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD current mode Data Sheet Preliminary 13 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 4.3 1024 Mbyte Registered Module HYS72T128000[G/H] (one rank, 18 components x4) 1024 MByte HYS72T128000[G/H] PC2-3200R “-5” Symbol Parameter / Condition Operating Current IDD0 PC2-4300R “-3.7” max. max. 1660 Unit mA Note 1358 1448 1840 mA 1 1 IDD1 Operating Current IDD2P Precharge PD Standby Current 440 562 mA 1 IDD2N Precharge Standby Current 944 1210 mA 1 IDD2Q Precharge Quiet Standby Current 818 1030 mA 1 IDD3P(0) Active PD Standby Current 602 778 mA 1 IDD3P(1) LP Active PD Standby Current 458 580 mA 1 IDD3N Active Standby Current 998 1210 mA 1 IDD4R Operating Current Burst Read 1628 2110 mA 1 IDD4W Operating Current Burst Write 1718 2200 mA 1 IDD5B Auto-Refresh Current (tRFCmin.) 2528 2830 mA 1 IDD5D Auto-Refresh Current (tREFI) 476 598 mA 1 IDD6 Self-Refresh Current 72 72 mA 1 IDD7 Operating Current 2708 3010 mA 1 Note: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled. Currents includes Registers and PLL. 4.4 2048 MByte Registered Module HYS72T256[0/2]20[G/H] (two ranks, 36 components x4) 2048 MByte HYS72T256020[G/H] 2048 MByte HYS72T256220[G/H] PC2-3200R “-5” Symbol Parameter / Condition Operating Current IDD0 PC2-4300R “-3.7” max. max. 1696 Unit mA Note 1394 1520 1912 mA 1, 2 512 623 mA 1, 3 1, 2 IDD1 Operating Current IDD2P Precharge PD Standby Current IDD2N Precharge Standby Current 1520 1930 mA 1, 3 IDD2Q Precharge Quiet Standby Current 1268 1570 mA 1, 3 IDD3P(0) Active PD Standby Current 836 1066 mA 1, 3 IDD3P(1) LP Active PD Standby Current 548 670 mA 1, 3 IDD3N Active Standby Current 1628 1930 mA 1, 3 IDD4R Operating Current Burst Read 1700 2182 mA 1, 2 IDD4W Operating Current Burst Write 1790 2272 mA 1, 2 IDD5B Auto-Refresh Current (tRFCmin.) 2600 2902 mA 1, 2 IDD5D Auto-Refresh Current (tREFI) 584 706 mA 1, 3 IDD6 Self-Refresh Current 144 144 mA 1, 3 IDD7 Operating Current 2780 3082 mA 1, 2 Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled. Currents includes Registers and PLL. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD current mode Data Sheet Preliminary 14 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 4.5 IDD Measurement Conditions (VDD = 1.8V ± 0.1V; VDDQ = 1.8V ± 0.1V) Symbol Parameter/Condition IDD0 Operating Current - One bank Active - Precharge tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. IDD1 Operating Current - One bank Active - Read - Precharge IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin.,tRCD = tRCDmin.,AL = 0, CL = CLmin.; CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. IDD2P Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCKmin.; IDD2N Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; IDD2Q IDD3P(0) IDD3P(1) Other control and address inputs are STABLE, Data bus inputs are FLOATING. Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Precharge Quiet Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address inputs are STABLE, Data bus inputs are FLOATING. Active Power-Down Current: All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus MRS A12 bit is set to “0” (Fast Power-down Exit); inputs are FLOATING. Active Power-Down Current: All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus MRS A12 bit is set to “1” (Slow Power-down Exit); inputs are FLOATING. IDD3N Active Standby Current: All banks open; tCK = tCKmin.; tRAS = tRASmax; tRP = tRPmin.,CKE is HIGH; CS is high between valid commands. Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. IDD4R Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4;AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0mA. IDD4W Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IDD5B Burst Auto-Refresh Current: tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. IDD5D Distributed Auto-Refresh Current: tCK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. IDD6 Self-Refresh Current: CKE ≤ 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85oC max. IDD7 All Bank Interleave Read Current: 1. All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0mA. 2. Timing pattern: - DDR2 -400: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D - DDR2 -533: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D - DDR2 -667: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D 3. Legend: A = Activate, RA = Read with Auto-Precharge, D=DESELECT Notes: 1. IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 2. Definitions for IDD: LOW is defined as VIN <= VIL(ac)max; HIGH is defined as VIN >= VIH(ac)min. STABLE is defined as inputs are stable at a HIGH or LOW level. FLOATING is defined as inputs are VREF = VDDQ / 2. SWITCHING is defined as: inputs are changing between HIGH and LOW every other clock (once per two cycles) for address and control signals, and inputs changing between HIGH and LOW every other clock (once per cycle) for DQ signals not including mask or strobes. 3. IDD1, IDD4R, and IDD7 current measurements are defined with the outputs disabled (Iout = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH. 3. For two rank modules: For all active current measurements the other rank is in Precharge Power-Down Mode IDD2P 4. RESET signal is high for all currents, except for IDD6 “Self Refresh”. 5. All current measurements includes Register and PLL current consumption. Data Sheet Preliminary 15 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 4.5 IDD Measurement Conditions (cont’d) For testing the IDD parameters, the following timing parameters are used: Parameter PC2-3200R “-5“ PC2-4300R “-3.7” 3-3-3 4-4-4 Unit Symbol CAS Latency CLmin 3 4 Clock Cycle Time tCKmin 5 3.75 ns tRCDmin 15 15 ns Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay x4 & x8 Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period Average periodic Refresh interval tCK tRCmin 60 60 ns tRRDmin 7.5 7.5 ns tRASmin 45 45 ns tRPmin 15 15 ns tRFCmin 105 105 ns tREFI 7.8 7.8 µs 4.6 ODT (On Die Termination) Current The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A6 & A2 in the EMRS(1) a “week” or “strong” termination can be selected. The current consumption for any terminated input pin, depends on the input pin is in tri-state or driving “0” or “1”, as long a ODT is enabled during a given period of time. ODT current per terminated pin: EMRS(1) State min. typ. max. Enabled ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; Data Bus inputs are FLOATING Unit A6 = 0, A2 = 1 5 6 7.5 mA/DQ A6 = 1, A2 = 0 2.5 3 3.75 mA/DQ A6 = 0, A2 = 1 10 12 15 mA/DQ A6 = 1, A2 = 0 5 6 7.5 mA/DQ IODTO Active ODT current per DQ IODTT added IDDQ current for ODT enabled; ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING. note: For power consumption calculations the ODT duty cycle has to be taken into account Data Sheet Preliminary 16 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 5.0 Electrical Characteristics & AC Timings 5.1 AC Timing Parameter by Speed Grade (Component level data, for reference only) Symbol tAC -5 DDR2-400 Parameter DQ output access time from CK / CK tDQSCK DQS output access time from CK / CK -3.7 DDR2-533 Min Max − 600 − 500 Unit Min Max + 600 -500 +500 + 500 −450 +450 ps ps tCH CK, CK high-level width 0.45 0.55 0.45 0.55 tCK 0.45 0.55 0.45 0.55 tCK tCL CK, CK low-level width tHP Clock Half Period tCK Clock cycle time min. (tCL, tCH) min. (tCL, tCH) CL = 3 5000 8000 5000 8000 ps CL = 4 & 5 5000 8000 3750 8000 ps tIS Address and control input setup time 600 - 600 - ps tIH Address and control input hold time 600 - 600 - ps tDS DQ and DM input setup time 400 - 350 - ps tDH DQ and DM input hold time 400 - 350 - ps tIPW Control and Addr. input pulse width (each input) 0.6 - 0.6 - tCK tDIPW DQ and DM input pulse width (each input) 0.35 - 0.35 - tCK tHZ - tACmax - tACmax ps tLZ(DQ) DQ low-impedance from CK / CK 2*tACmin tACmax 2*tACmin tACmax ps tLZ(DQS) DQS low-impedance from CK / CK tACmin tACmax tACmin tACmax ps - 350 - 300 ps ps tDQSQ Data-out high-impedance time from CK / CK DQS-DQ skew (for DQS & associated DQ signals) tQHS Data hold skew factor tQH Data Output hold time from DQS - 450 - 400 tHP-tQHS - tHP-tQHS - Write command to 1st DQS latching transition WL -0.25 WL +0.25 WL -0.25 WL +0.25 tCK tDQSL,H DQS input low (high) pulse width (write cycle) 0.35 - 0.35 - tCK tDSS DQS falling edge to CLK setup time (write cycle) 0.2 - 0.2 - tCK tDSH DQS falling edge hold time from CLK (write cycle) 0.2 - 0.2 - tCK tMRD Mode register set command cycle time 2 - 2 - tCK tWPRE Write preamble 0.25 - 0.25 - tCK tWPST Write postamble 0.40 0.60 0.40 0.60 tCK tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK tRPST Read postamble 0.40 0.60 0.40 0.60 tCK tRAS Active to Precharge command 45 70000 45 70000 ns tRC Active to Active/Auto-refresh command period 60 - 60 - ns tRFC Auto-refresh to Active/Auto-refresh command period 105 - 105 - ns tDQSS Data Sheet Preliminary 17 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules Symbol tRCD -5 DDR2-400 Parameter Active to Read or Write delay (with and without Auto-Precharge) delay -3.7 DDR2-533 Max Min Max 15 - 15 - tRP Precharge command period tRRD Active bank A to Active bank B command tCCD CAS A to CAS B Command Period 2 - tWR Write recovery time 15 - tDAL Auto precharge write recovery + precharge time WR+tRP - tWTR Internal write to read command delay 10 tRTP Internal read to precharge command delay 7.5 2 x4 & x8 (1k page size) tXARD Exit power down to any valid command (other than NOP or Deselect) tXARDS Exit active power-down mode to read command (slew exit, lower power) tXP Unit Min ns 15 - 15 - ns 7.5 - 7.5 - ns 2 - tCK 15 - ns WR+tRP - tCK - 7.5 - ns - 7.5 - ns - 2 - tCK 6 - AL - 6 - AL - tCK 2 - 2 - tCK tCK Exit precharge power-down to any valid command (other than NOP or Deselect) tXSRD Exit Self-Refresh to read command 200 - 200 - tXSNR Exit Self-Refresh to non-read command tRFC + 10 - tRFC + 10 - ns tCKE CKE minimum high and low pulse width 3 - 3 - tCK tOIT OCD drive mode output delay 0 12 0 12 ns tIS+tCK +tIH - tIS+tCK +tIH - ns time clocks remain ON after CKE asynchrotDELAY Minimum nously drops low tREFI o Average Periodic Refresh Interval o 0 C - 85 C - 7.8 - 7.8 85oC - 95oC - 3.9 - 3.9 µs 1. For details and notes see the relevant INFINEON component datasheet 2. Timing definition and values for tis, tih, tds and tdh may change due to actual JEDEC work. This may also effect the SPD code for these parameters. 5.2 ODT AC Electrical Characteristics and Operating Conditions (all speed bins) Symbol Parameter / Condition tAOND tAON min. max. Units 2 2 tCK DDR2-400/533 tAC(min) tAC(max) + 1 ns DDR2-667 tAC(min) tAC(max) + 0.7 ns tAC(min) + 2 ns 2 tCK + tAC(max) + 1 ns ns 2.5 2.5 tCK ns ODT turn-on delay ODT turn-on tAONPD ODT turn-on (Power-Down Modes) tAOFD tAOF ODT turn-off delay ODT turn-off ns tAC(min) tAC(max) + 0.6 ns tAOFPD ODT turn-off delay (Power-Down Modes) tAC(min) + 2 ns 2.5 tCK + tAC(max) + 1 ns ns tANPD ODT to Power Down Mode Entry Latency 3 - tCK tAXPD ODT Power Down Exit Latency 8 - tCK Data Sheet Preliminary 18 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 6.0 Serial Presence Detect Codes for Registered Modules Label Code Jedec SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used 8 Interface Voltage Level 9 tCK @ CLmax (Byte 18) [ns] 10 tAC SDRAM @ CLmax (Byte 18) [ns] 11 Error Correction Support (non-ECC, ECC) 12 Refresh Rate and Type 13 Primary SDRAM Width 14 Error Checking SDRAM Width 15 Not used 16 Burst Length Supported 17 Number of Banks on SDRAM Device 18 Supported CAS Latencies 19 Not used 20 DIMM Type Information 21 DIMM Attributes 22 Component Attributes 23 tCK @ CLmax -1 (Byte 18) [ns] 24 tAC SDRAM @ CLmax -1 [ns] 25 tCK @ CLmax -2 (Byte 18) [ns] 26 tAC SDRAM @ CLmax -2 [ns] 27 tRP.min [ns] 28 tRRD.min [ns] Data Sheet Preliminary 19 HYS72T64000GR–3.7–A HYS72T64000HR–3.7–A 2 GByte 1 GByte ×72 ×72 2 Ranks (×4) 1 Rank (×4) PC2–4300R–444 Rev. 1.1 Rev. 1.1 HEX HEX 80 80 08 08 08 08 0E 0E 0B 0B 61 60 48 48 00 00 05 05 3D 3D 50 50 02 02 82 82 04 04 04 04 00 00 0C 0C 04 04 38 38 00 00 01 01 07 05 01 01 3D 3D 50 50 50 50 60 60 3C 3C 1E 1E HYS72T128020GR–3.7–A HYS72T128020HR–3.7–A Organization HYS72T128000GR–3.7–A HYS72T128000HR–3.7–A Product Type HYS72T256020GR–3.7–A HYS72T256020HR–3.7–A 6.1 SPD Codes for PC2–4300R (–3.7) 1 GByte 512 MB ×72 ×72 2 Ranks (×8) 1 Rank (×8) Rev. 1.1 HEX 80 08 08 0E 0A 61 48 00 05 3D 50 02 82 08 08 00 0C 04 38 00 01 05 01 3D 50 50 60 3C 1E Rev. 1.1 HEX 80 08 08 0E 0A 60 48 00 05 3D 50 02 82 08 08 00 0C 04 38 00 01 04 01 3D 50 50 60 3C 1E Rev. 0.85, 2004-04 Label Code Jedec SPD Revision Byte# Description 29 tRCD.min [ns] 30 tRAS.min [ns] 31 Module Density per Rank 32 tAS.min and tCS.min [ns] 33 tAH.min and tCH.min [ns] 34 tDS.min [ns] 35 tDH.min [ns] 36 tWR.min [ns] 37 tWTR.min [ns] 38 tRTP.min [ns] 39 Analysis Characteristics 40 tRC and tRFC Extension 41 tRC.min [ns] 42 tRFC.min [ns] 43 tCK.max [ns] 44 tDQSQ.max [ns] 45 tQHS.max [ns] 46 PLL Relock Time 47 TCASE.max Delta / ∆ T4R4W Delta 48 Psi(T-A) DRAM 49 ∆ T0 50 ∆ T2N (UDIMM) or ∆ T2Q (RDIMM) 51 ∆ T2P 52 ∆ T3N 53 ∆ T3P.fast 54 ∆ T3P.slow 55 ∆ T4R / ∆ T4R4W Sign 56 ∆ T5B 57 ∆ T7 58 Psi(ca) PLL 59 Psi(ca) REG 60 ∆ TPLL Data Sheet Preliminary 20 HYS72T64000GR–3.7–A HYS72T64000HR–3.7–A 2 GByte 1 GByte ×72 ×72 2 Ranks (×4) 1 Rank (×4) PC2–4300R–444 Rev. 1.1 Rev. 1.1 HEX HEX 3C 3C 2D 2D 01 01 25 25 37 37 10 10 22 22 3C 3C 1E 1E 1E 1E 00 00 00 00 3C 3C 69 69 80 80 1E 1E 28 28 0F 0F 51 51 78 78 3E 3E 22 22 1E 1E 1E 1E 24 24 17 17 34 34 1E 1E 20 20 C4 C4 8C 8C 61 61 HYS72T128020GR–3.7–A HYS72T128020HR–3.7–A Organization HYS72T128000GR–3.7–A HYS72T128000HR–3.7–A Product Type HYS72T256020GR–3.7–A HYS72T256020HR–3.7–A HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 1 GByte 512 MB ×72 ×72 2 Ranks (×8) 1 Rank (×8) Rev. 1.1 HEX 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 0F 51 78 3E 22 1E 1E 24 17 34 1E 20 C4 8C 61 Rev. 1.1 HEX 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 0F 51 78 3E 22 1E 1E 24 17 34 1E 20 C4 8C 61 Rev. 0.85, 2004-04 Label Code Jedec SPD Revision Byte# Description 61 ∆ TREG / Toggle Rate 62 SPD Revision 63 Checksum of Bytes 0-62 64 JEDEC ID Code of Infineon (1) 65 JEDEC ID Code of Infineon (2) 66 JEDEC ID Code of Infineon (3) 67 JEDEC ID Code of Infineon (4) 68 JEDEC ID Code of Infineon (5) 69 JEDEC ID Code of Infineon (6) 70 JEDEC ID Code of Infineon (7) 71 JEDEC ID Code of Infineon (8) 72 Module Manufacturer Location 73 Product Type, Char 1 74 Product Type, Char 2 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 79 Product Type, Char 7 80 Product Type, Char 8 81 Product Type, Char 9 82 Product Type, Char 10 83 Product Type, Char 11 84 Product Type, Char 12 85 Product Type, Char 13 86 Product Type, Char 14 87 Product Type, Char 15 88 Product Type, Char 16 89 Product Type, Char 17 90 Product Type, Char 18 91 Module Revision Code 92 Test Program Revision Code Data Sheet Preliminary 21 HYS72T64000GR–3.7–A HYS72T64000HR–3.7–A 2 GByte 1 GByte ×72 ×72 2 Ranks (×4) 1 Rank (×4) PC2–4300R–444 Rev. 1.1 Rev. 1.1 HEX HEX 78 78 11 11 8E 8B C1 C1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 xx xx 37 37 32 32 54 54 32 31 35 32 36 38 30 30 32 30 30 30 47 / 48 47 / 48 52 52 33 33 2E 2E 37 37 41 41 20 20 20 20 20 20 0x 2x xx xx HYS72T128020GR–3.7–A HYS72T128020HR–3.7–A Organization HYS72T128000GR–3.7–A HYS72T128000HR–3.7–A Product Type HYS72T256020GR–3.7–A HYS72T256020HR–3.7–A HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 1 GByte 512 MB ×72 ×72 2 Ranks (×8) 1 Rank (×8) Rev. 1.1 HEX 78 11 12 C1 00 00 00 00 00 00 00 xx 37 32 54 31 32 38 30 32 30 47 / 48 52 33 2E 37 41 20 20 20 2x xx Rev. 1.1 HEX 78 11 10 C1 00 00 00 00 00 00 00 xx 37 32 54 36 34 30 30 30 47 / 48 52 33 2E 37 41 20 20 20 20 2x xx Rev. 0.85, 2004-04 Label Code Jedec SPD Revision Byte# Description 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week 95 Module Serial Number (1) 96 Module Serial Number (2) 97 Module Serial Number (3) 98 Module Serial Number (4) 99 Not used 127 Data Sheet Preliminary 22 HYS72T64000GR–3.7–A HYS72T64000HR–3.7–A 2 GByte 1 GByte ×72 ×72 2 Ranks (×4) 1 Rank (×4) PC2–4300R–444 Rev. 1.1 Rev. 1.1 HEX HEX xx xx xx xx xx xx xx xx xx xx xx xx 00 00 HYS72T128020GR–3.7–A HYS72T128020HR–3.7–A Organization HYS72T128000GR–3.7–A HYS72T128000HR–3.7–A Product Type HYS72T256020GR–3.7–A HYS72T256020HR–3.7–A HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 1 GByte 512 MB ×72 ×72 2 Ranks (×8) 1 Rank (×8) Rev. 1.1 HEX xx xx xx xx xx xx 00 Rev. 1.1 HEX xx xx xx xx xx xx 00 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 1 GByte 1 GByte 512 MB ×72 ×72 ×72 1 Rank (×4) 2 Ranks (×8) 1 Rank (×8) Rev. 1.1 HEX 80 Rev. 1.1 HEX 80 Rev. 1.1 HEX 80 08 08 08 08 08 08 0E 0B 61 08 0E 0B 61 08 0E 0B 60 08 0E 0A 61 08 0E 0A 60 48 00 05 50 60 48 00 05 50 60 48 00 05 50 60 48 00 05 50 60 48 00 05 50 60 02 02 02 02 02 82 04 04 00 0C 04 82 04 04 00 0C 04 82 04 04 00 0C 04 82 08 08 00 0C 04 82 08 08 00 0C 04 38 00 01 07 01 50 60 50 60 38 00 01 07 01 50 60 50 60 38 00 01 05 01 50 60 50 60 38 00 01 05 01 50 60 50 60 38 00 01 04 01 50 60 50 60 Label Code Jedec SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used 8 Interface Voltage Level 9 tCK @ CLmax (Byte 18) [ns] 10 tAC SDRAM @ CLmax (Byte 18) [ns] 11 Error Correction Support (nonECC, ECC) 12 Refresh Rate and Type 13 Primary SDRAM Width 14 Error Checking SDRAM Width 15 Not used 16 Burst Length Supported 17 Number of Banks on SDRAM Device 18 Supported CAS Latencies 19 Not used 20 DIMM Type Information 21 DIMM Attributes 22 Component Attributes 23 tCK @ CLmax -1 (Byte 18) [ns] 24 tAC SDRAM @ CLmax -1 [ns] 25 tCK @ CLmax -2 (Byte 18) [ns] 26 tAC SDRAM @ CLmax -2 [ns] Data Sheet Preliminary 23 HYS72T64000GR–5–A HYS72T64000HR–5–A HYS72T128020GR–5–A HYS72T128020HR–5–A 2 GByte 2 GByte ×72 ×72 2 Ranks (×4) 2 Ranks (×4) PC2–3200R–333 Rev. 1.1 Rev. 1.1 HEX HEX 80 80 HYS72T128000GR–5–A HYS72T128000HR–5–A Organization HYS72T256220GR–5–A HYS72T256220HR–5–A Product Type HYS72T256020GR–5–A HYS72T256020HR–5–A 6.2 SPD Codes for PC2–3200R (–5) Rev. 0.85, 2004-04 1 GByte 1 GByte 512 MB ×72 ×72 ×72 1 Rank (×4) 2 Ranks (×8) 1 Rank (×8) Rev. 1.1 HEX 3C 1E 3C 2D 01 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 0F 51 78 32 1D Rev. 1.1 HEX 3C 1E 3C 2D 80 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 0F 51 78 32 1D Rev. 1.1 HEX 3C 1E 3C 2D 80 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 0F 51 78 32 1D 1E 1B 1E 17 28 1B 1E C4 1E 1B 1E 17 28 1B 1E C4 1E 1B 1E 17 28 1B 1E C4 1E 1B 1E 17 28 1B 1E C4 Label Code Jedec SPD Revision Byte# Description 27 tRP.min [ns] 28 tRRD.min [ns] 29 tRCD.min [ns] 30 tRAS.min [ns] 31 Module Density per Rank 32 tAS.min and tCS.min [ns] 33 tAH.min and tCH.min [ns] 34 tDS.min [ns] 35 tDH.min [ns] 36 tWR.min [ns] 37 tWTR.min [ns] 38 tRTP.min [ns] 39 Analysis Characteristics 40 tRC and tRFC Extension 41 tRC.min [ns] 42 tRFC.min [ns] 43 tCK.max [ns] 44 tDQSQ.max [ns] 45 tQHS.max [ns] 46 PLL Relock Time 47 TCASE.max Delta / ∆ T4R4W Delta 48 Psi(T-A) DRAM 49 ∆ T0 50 ∆ T2N (UDIMM) or ∆ T2Q (RDIMM) 51 ∆ T2P 52 ∆ T3N 53 ∆ T3P.fast 54 ∆ T3P.slow 55 ∆ T4R / ∆ T4R4W Sign 56 ∆ T5B 57 ∆ T7 58 Psi(ca) PLL Data Sheet Preliminary 1E 1B 1E 17 28 1B 1E C4 24 HYS72T64000GR–5–A HYS72T64000HR–5–A HYS72T128020GR–5–A HYS72T128020HR–5–A 2 GByte 2 GByte ×72 ×72 2 Ranks (×4) 2 Ranks (×4) PC2–3200R–333 Rev. 1.1 Rev. 1.1 HEX HEX 3C 3C 1E 1E 3C 3C 2D 2D 01 01 35 35 47 47 15 15 27 27 3C 3C 28 28 1E 1E 00 00 00 00 3C 3C 69 69 80 80 23 23 2D 2D 0F 0F 51 51 78 78 32 32 1D 1D HYS72T128000GR–5–A HYS72T128000HR–5–A Organization HYS72T256220GR–5–A HYS72T256220HR–5–A Product Type HYS72T256020GR–5–A HYS72T256020HR–5–A HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules Rev. 0.85, 2004-04 Label Code Jedec SPD Revision Byte# Description 59 Psi(ca) REG 60 ∆ TPLL 61 ∆ TREG / Toggle Rate 62 SPD Revision 63 Checksum of Bytes 0-62 64 JEDEC ID Code of Infineon (1) 65 JEDEC ID Code of Infineon (2) 66 JEDEC ID Code of Infineon (3) 67 JEDEC ID Code of Infineon (4) 68 JEDEC ID Code of Infineon (5) 69 JEDEC ID Code of Infineon (6) 70 JEDEC ID Code of Infineon (7) 71 JEDEC ID Code of Infineon (8) 72 Module Manufacturer Location 73 Product Type, Char 1 74 Product Type, Char 2 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 79 Product Type, Char 7 80 Product Type, Char 8 81 Product Type, Char 9 82 Product Type, Char 10 83 Product Type, Char 11 84 Product Type, Char 12 85 Product Type, Char 13 86 Product Type, Char 14 87 Product Type, Char 15 88 Product Type, Char 16 89 Product Type, Char 17 90 Product Type, Char 18 91 Module Revision Code Data Sheet Preliminary 25 HYS72T64000GR–5–A HYS72T64000HR–5–A HYS72T128020GR–5–A HYS72T128020HR–5–A 2 GByte 2 GByte ×72 ×72 2 Ranks (×4) 2 Ranks (×4) PC2–3200R–333 Rev. 1.1 Rev. 1.1 HEX HEX 8C 8C 59 59 5C 5C 11 11 C3 C3 C1 C1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 xx xx 37 37 32 32 54 54 32 32 35 35 36 36 30 32 32 32 30 30 47 / 48 47 / 48 52 52 35 35 41 41 20 20 20 20 20 20 20 20 20 20 0x 0x HYS72T128000GR–5–A HYS72T128000HR–5–A Organization HYS72T256220GR–5–A HYS72T256220HR–5–A Product Type HYS72T256020GR–5–A HYS72T256020HR–5–A HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 1 GByte 1 GByte 512 MB ×72 ×72 ×72 1 Rank (×4) 2 Ranks (×8) 1 Rank (×8) Rev. 1.1 HEX 8C 59 5C 11 C0 C1 00 00 00 00 00 00 00 xx 37 32 54 31 32 38 30 30 30 47 / 48 52 35 41 20 20 20 20 20 2x Rev. 1.1 HEX 8C 59 5C 11 47 C1 00 00 00 00 00 00 00 xx 37 32 54 31 32 38 30 32 30 47 / 48 52 35 41 20 20 20 20 20 2x Rev. 1.1 HEX 8C 59 5C 11 45 C1 00 00 00 00 00 00 00 xx 37 32 54 36 34 30 30 30 47 / 48 52 35 41 20 20 20 20 20 20 2x Rev. 0.85, 2004-04 1 GByte 1 GByte 512 MB ×72 ×72 ×72 1 Rank (×4) 2 Ranks (×8) 1 Rank (×8) Rev. 1.1 HEX xx xx Rev. 1.1 HEX xx xx Rev. 1.1 HEX xx xx xx xx xx xx xx xx xx xx xx 00 xx xx xx xx 00 xx xx xx xx 00 xx xx xx xx 00 xx xx xx xx 00 Label Code Jedec SPD Revision Byte# Description 92 Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week 95 Module Serial Number (1) 96 Module Serial Number (2) 97 Module Serial Number (3) 98 Module Serial Number (4) 99 Not used 127 Data Sheet Preliminary 26 HYS72T64000GR–5–A HYS72T64000HR–5–A HYS72T128020GR–5–A HYS72T128020HR–5–A 2 GByte 2 GByte ×72 ×72 2 Ranks (×4) 2 Ranks (×4) PC2–3200R–333 Rev. 1.1 Rev. 1.1 HEX HEX xx xx xx xx HYS72T128000GR–5–A HYS72T128000HR–5–A Organization HYS72T256220GR–5–A HYS72T256220HR–5–A Product Type HYS72T256020GR–5–A HYS72T256020HR–5–A HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 7.0 Package Outline 7.1 Raw Card A Module Package DDR2 Registered DIMM Modules Raw Card A one physical rank, 9 components x8 organised 133.35 +- 0.15 2.7 max. Register 30.0. Front View 4.0 PLL pin 1 64 120 65 63,0 5,175 5,175 55,0 1.27 +- 0.1 PCB warpage 0.40 5.0 Backside View 184 240 185 10.0 17.80 pin 121 3 3 Detail of Contacts B 5.0 2.50 +- 0.20 0.20 +- 0.15 Detail of Contacts A 3.8 typ. 0.75R 0.8 +- 0.05 1.0 1.5 2.5 note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237) Data Sheet Preliminary 27 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 7.2 Raw Card B Module Package DDR2 Registered DIMM Modules Raw Card B two one physical rank, 18 components x8 organised 1 3 3.3 5 +- 0.15 4.0 m a x. Register Front View 30.0. 4 .0 PLL p in 1 64 1 20 65 6 3,0 5,1 75 5 ,1 7 5 55 ,0 1 .27 +- 0.1 PCB warpage 0.40 5.0 Backside View 240 185 1 84 Register 10.0 17.80 pin 1 21 3 3 D e tail o f C o nta cts B 5 .0 2.50 +- 0.20 0.20 +- 0.15 D e ta il of C on tac ts A 3.8 typ. 0 .8 0 .75 R + - 0.05 1 .0 1 .5 2.5 note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237) Data Sheet Preliminary 28 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 7.3 Raw Card C Module Package DDR2 Registered DIMM Modules Raw Card C one physical rank, 18 components x4 organised 1 3 3.3 5 +- 0.15 4.0 m a x. Register Front View 30.0. 4 .0 PLL p in 1 64 1 20 65 6 3,0 5,1 75 5 ,1 7 5 55 ,0 1 .27 -+ 0.1 PCB warpage 0.40 5.0 Backside View 240 185 1 84 Register 10.0 17.80 pin 1 21 3 3 D e tail o f C o nta cts B 5 .0 2.50 +- 0.20 0.20 +- 0.15 D e ta il of C on tac ts A 3.8 typ. 0 .8 0 .75 R + - 0.05 1 .0 1 .5 2.5 note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237) Data Sheet Preliminary 29 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 7.4 Raw Card (tbd) Module Package DDR2 Registered DIMM Modules Raw Card (tbd.) two physical ranks, 36 components x4 organised - planar version 133.35 +- 0.15 4.0 max. Register 30.0 4.0 PLL Register Front View pin 1 64 120 65 63,0 5,175 5,175 55,0 1.27 +- 0.1 PCB warpage 0.40 5.0 Backside View 184 240 185 10.0 17.80 pin 121 3 3 Detail of Contacts B 5.0 2.50 +- 0.20 0.20 +- 0.15 Detail of Contacts A 3.8 typ. 0.75R 0.8 -+ 0.05 1.0 1.5 2.5 note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO237) Data Sheet Preliminary 30 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules 8.0 Nomenclature (Modules & Components) 8.1 DDR2 DIMM Modules 1 Example: HYS 2 3 4 5 6 7 8 9 10 11 72 T 128 0 2 0 G R -5 -A 0 = standard 2 = dual die package 1 INFINEON Prefix HYS for DIMM Modules 7 Product Variations 2 Module Data Width 64 = Non-ECC Modules 72 = ECC Modules 8 Package 3 DRAM Technology 9 Module Type R = Registered DIMMs U = Unbuffered DIMMs DL = Small Outline DIMMs 4 Memory Density per I/O 64 = 64 Mb 128 = 128 Mb 256 = 256 Mb 10 Speed Grade -5 = PC2-3200 (DDR2-400) -3.7 = PC2-4300 (DDR2-533) -3 = PC2-5400 (DDR2-667) 5 Raw Card Generation 0 = first generation 11 Die Revision A = 1st Generation B = 2nd Generation C = 3rd Generation 6 Number of Memory Ranks 0 = One Rank 2 = Two Ranks Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes. T = DDR2 G= BGA components 8.2 DDR2 Memory Components 1 Example: HYB 2 3 4 5 6 7 8 9 18 T 512 40 0 A C -5 1 INFINEON Component Prefix HYB for DRAM Components 6 Product Variations 0 = standard 2 = dual die package 2 Power Supply Voltage 18 = 1.8 V Power Supply 7 Die Revision A = 1st Generation B = 2nd Generation C = 3rd Generation 3 DRAM Technology T = DDR2 8 Package Type C = BGA package F = BGA package (lead and halogen free) 4 Memory Density 256 = 256 Mb 512 = 512 Mb 1G = 1024Mb 9 Speed Grade -5 =...DDR2-400 -3.7 =.DDR2-533 -3 =...DDR2-667 5 Memory Organisation 40 = x4, 4 data in/outputs 80 = x8, 8 data in/outputs 16 = x16, 16 data in/outputs Data Sheet Preliminary 31 Rev. 0.85, 2004-04 HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules Data Sheet Preliminary 32 Rev. 0.85, 2004-04