Sharp LH1691 240-output tft-lcd gate driver ic Datasheet

LH1691
240-output TFT-LCD Gate Driver IC
LH1691
DESCRIPTION
PIN CONNECTIONS
The LH1691 is a 240-output TFT-LCD gate driver
IC.
TOP VIEW
258-PIN TCP
1 OG1
2 OG2
3 OG3
• Number of LCD drive outputs : 240
• LCD drive output sequence :
Output shift direction can be selected
OG1/OG240 or OG240/OG1
• Cascade connection :
Max. 2 cascades (internal counting system)
• Usable with both positive/negative power supplies
• Output mode selection
– Normal mode (1-pulse scanning)
– Continuous 2-pulse mode (2-pulse scanning)
– Jumping 2-pulse mode (2-pulse scanning)
• LCD drive voltage : +16.0 to +33.0 V
• Operating temperature : –30 to +85 ˚C
• Package : 258-pin TCP (Tape Carrier Package)
VDD
VEE
VSS
VCC
VLS
TEST1
TEST2
CKV
SPV
CE
R/L
MODE1
MODE2
VLS
VCC
VSS
VEE
VDD
258
257
256
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
CHIP SURFACE
FEATURES
238 OG238
239 OG239
240 OG240
NOTE :
Doesn't prescribe TCP outline.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in
catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
1
LH1691
PIN DESCRIPTION
PIN NO.
1 to 240
SYMBOL
OG1-OG240
I/O
O
DESCRIPTION
241, 258
VDD
–
Power supply pins for LCD drive
242, 257
VEE
–
Power supply pins for LCD drive
243, 256
VSS
–
Power supply pins for logic system
244, 255
VCC
–
Power supply pins for logic system
245, 254
VLS
246, 247
MODE2, MODE1
–
I
Power supply pins for input level shifter
Output mode selection pins
248
R/L
I
249
CE
I
sequence
Cascade sequence setting pin
250
251
SPV
CKV
I
I
Vertical scanning start pulse input pin
Vertical shift clock input pin
252, 253
TEST2, TEST1
I
IC test pins
LCD drive output pins
Pin for selecting bi-directional shift register and setting cascade
BLOCK DIAGRAM
BI-DIRECTIONAL SHIFT
REGISTER
MODE2 246
MODE1 247
1
R/L 248
CE 249
CONTROL
LOGIC
SPV 250
240
LEVEL SHIFTER
1
CKV 251
240
TEST2 252
TEST1 253
OUTPUT CIRCUIT
1
241 258 245 254 244 255 242 257 243 256
VDD VDD
VLS VLS
VCC VCC VEE VEE
VSS VSS
2
240
1
240
OG1
OG240
LH1691
FUNCTIONAL OPERATIONS OF EACH BLOCK
BLOCK
Control Logic
Bi-directional Shift
FUNCTION
Used to create signals necessary for mode selecting signal, cascade sequence setting
signal and for operation of bi-directional shift register.
Used as transfer circuit of LCD drive output start signal. It is possible to set LCD drive
output sequence of OG1/OG240 direction or OG240/OG1 direction.
Used as circuit which shifts LCD drive output signals transferred by bi-directional shift
Register
Level Shifter
Output Circuit
,
register to VDD-VEE level.
Configured with output buffers to output VDD-VEE level.
INPUT/OUTPUT CIRCUITS
VLS
I
To Internal Circuit
Level Shifter
Internal Logic
(VLS-0 V/VCC-VSS)
(VCC-VSS)
VSS
¿Applicable pins¡
CKV, SPV, CE, R/L,
MODE1, MODE2,
TEST1, TEST2
Fig. 1 Input Circuit
VDD
O
From Internal Circuit
(VDD-VEE)
¿Applicable pins¡
OG1-OG240
VEE
Fig. 2 Output Circuit
3
LH1691
FUNCTIONAL DESCRIPTION
Pin Functions
SYMBOL
VDD
FUNCTION
Used as power supply pin for high level LCD drive.
VLS
Used as power supply pin for input level shifters.
VCC
Used as power supply pin for logic system, normally connected to VSS + 5.0 V.
VEE
Used as power supply pin for low level LCD drive.
Used as logic system power supply pin.
VSS
CKV
Used as vertical shift clock pulse input pin.
SPV
Used as vertical scanning start pulse input pin. (At least, input one cycle of CKV during "L"
period of SPV.)
Used as input pins for selecting output mode.
Output mode is set as shown in the table below by setting MODE1 pin and MODE2 pin.
MODE1
MODE2
H
L
H
H
Normal mode (1-pulse scanning)
Continuous 2-pulse mode
H
L
L
L
Jumping 2-pulse mode
Set all outputs to VEE level.
MODE1
MODE2
Output mode
Used as input pin for selecting the shift direction of bi-directional shift register and for
setting the sequence of cascade connection.
R/L
LCD drive outputs shift from OG1 to OG240 when set to "H". LCD drive outputs shift from
OG240 to OG1 when set to "L". At the same time, cascade sequence is set as shown in
the table below.
CE
Used as input pin for setting of chip cascade sequence. (Max. 2 cascades)
Cascade sequence
CE
R/L = "H"
R/L = "L"
H
L
1st
2nd
2nd
1st
TEST1
With above setting, sets the cascade sequence signal inside the IC.
Used as input pins for IC testing.
TEST2
Must be set to "H".
Used as output pins for LCD drive output, and which output data at 2 levels.
OG1-OG240
• Selecting data is output at VDD level .
• Non-selecting data is output at VEE level .
4
LH1691
Functional Operations
(1) Example of Cascade Sequence
OG1
CE = "H"
OG240
TFT-LCD Panel
OG1
CE = "L"
OG240
Scanning Direction When R/L = "L".
Scanning Direction When R/L = "H".
* At this time, normal mode (scanning with 1 pulse) is set when MODE1 = "H" and MODE2 = "H",
jumping 2-pulse mode (scanning with 2 pulses) is set when MODE1 = "H" and MODE2 = "L",
continuous 2-pulse mode (scanning with 2 pulses) is set when MODE1 = "L" and MODE2 = "H", and
output VEE level is set when MODE1 = "L" and MODE2 = "L".
5
LH1691
(2) Example of Input/Output Timing (For 1st Cascade Sequence)
CKV
SPV
OG1
OG240
OG2
OG239
OG3
OG238
OG1
OG240
OG2
OG239
OG3
OG238
OG1
OG240
OG2
OG239
OG3
OG238
(1-pulse Mode)
(Jumping 2-pulse Mode)
(Continuous 2-pulse Mode)
R/L = "H" R/L = "L"
6
LH1691
PRECAUTIONS
Logic system power supply (VLS), internal logic
system power supply (VSS, VCC; VCC > VSS)
and low-level LCD drive power supply (VEE) /
logic input / high-level LCD drive power supply
(VDD)
Precautions when connecting or disconnecting
the power supply
This IC has a high-voltage LCD driver, so it may be
permanently damaged by a high current which may
flow if voltage is supplied to the LCD drive power
supply while the logic system power supply is
floating. Therefore, when connecting the power
supply, observe the following sequence.
When disconnecting the power supply, follow the
reverse sequence.
Since the logic state of the internal circuit is
unstable immediately after the logic system power
is supplied, input CKV and SPV while initializing the
internal circuit (minimum input clock number is 240
CKV).
MODE1 and MODE2 should be set to "L" during
the initializing period for setting the LCD drive
output to VEE level.
Logic system power supply (VLS) or internal
logic system power supply (VSS, VCC; VCC >
VSS) / logic input / LCD drive power supply
(VEE, VDD)
It is possible to set voltage VEE to the same as
VSS. When connecting the power supply when VEE
= VSS, observe the following sequence and the
recommended sequence figure shown below.
VDD
VLS
Input
0V
VCC
VSS, VEE
Maximum ratings
When connecting or disconnecting the power, this
IC must be used within the range of the absolute
maximum ratings.
Input pin setting
Input pins other than CKV and SPV must be set to
"H" or "L" level.
7
LH1691
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply voltage
SYMBOL
VDD
APPLICABLE PINS
VDD
RATING
–0.3 to +35.0
UNIT
V
VLS
VLS
–0.3 to +7.0
V
VCC – VSS
VCC, VSS
–0.3 to +7.0
V
VEE – VSS
VEE, VSS
–0.3 to +35.0
V
VDD, VEE, VSS
–0.3 to +35.0
V
–0.3 to VLS + 0.3
V
–45 to +125
˚C
VDD – VEE
(VSS)
Input voltage
Storage temperature
VIN
CKV, SPV, CE, R/L, MODE1,
MODE2, TEST1, TEST2
TSTG
NOTES :
1. TA = +25 ˚C
2. The maximum applicable voltage on any pin with respect to 0 V.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply voltage
MIN.
+5.5
+3.0
TYP.
+9.0
+5.0
VCC – VSS +3.0
+5.0
SYMBOL
VDD
VLS
VEE – VSS
VDD – VEE
Input voltage
(VSS)
VIN
Operating temperature
TOPR
0
+16.0
+25.0
MAX.
+33.0
+5.5
UNIT
V
V
+5.5
V
+11.0
V
+33.0
V
0
VLS
V
–30
+85
˚C
NOTES :
1. The applicable voltage on any pin with respect to 0 V.
2. Ensure that voltages are set as follows.
VSS, VEE ≤ 0 V
VCC – VSS = VLS±0.2 V (For 3.3 V specifications)
VCC – VSS = VLS±0.3 V (For 5.0 V specifications)
VCC ≤ VLS
8
NOTE
1, 2
NOTE
1, 2
LH1691
When power supply pins are set as shown below,
the LH1691 can output positive voltage and
negative voltage to LCD drive output.
Example 1 : For Positive Voltage Output
LCD Drive Output
VDD
VLS, VCC
Input
Internal Logic
VSS, VEE (0 V)
Example 2 : For Negative Voltage Output
VDD, VLS
LCD Drive Output
Input
0V
VCC
Internal Logic
VSS, VEE
9
LH1691
ELECTRICAL CHARACTERISTICS
DC Characteristics
PARAMETER
Input "Low" voltage
Input "High" voltage
VIH
Output "Low" voltage
VOL
Output "High" voltage
VOH
Input "Low" current
Input "High" current
(VLS = +3.3±0.3 V (= VCC – VSS), TOPR = –30 to +85 ˚C)
SYMBOL CONDITIONS
VIL
IIL
IIH
APPLICABLE PINS
CKV, SPV, MODE1,
MODE2, CE, R/L
OG1-OG240
IOH = –0.4 mA
VI = 0 V
CKV, SPV, MODE1,
VI = VLS
MODE2, CE, R/L
UNIT
V
V
5.0
V
µA
5.0
µA
50
100
µA
µA
µA
µA
VDD – 0.4
For
1-pulse mode
50
40
100
µA
For jumping
2-pulse mode
200
60
µA
µA
IEE
40
µA
IDD
100
µA
ILS
ICC
ILS
For continuous
200
µA
ICC
2-pulse mode
60
40
µA
µA
IEE
NOTE
V
VEE + 0.4
ILS
IDD
Supply current (3)
MAX.
0.2VLS
ICC
IEE
Supply current (2)
TYP.
0.8VLS
IOL = 0.4 mA
IDD
Supply current (1)
MIN.
1
2
3
4
NOTES :
1. All input pins : 3.3 V
2. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 µs
SPV : Frequency = 60 Hz
Other input pins : 3.3 V
All output pins are opened.
3. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 µs
SPV : Frequency = 60 Hz
MODE2 : 0 V
Other input pins : 3.3 V
All output pins are opened.
4. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 µs
SPV : Frequency = 60 Hz
MODE1 : 0 V
Other input pins : 3.3 V
All output pins are opened.
10
LH1691
(VLS = +5.0±0.5 V (= VCC – VSS), TOPR = –30 to +85 ˚C)
PARAMETER
Input "Low" voltage
Input "High" voltage
SYMBOL CONDITIONS
VIL
VIH
MODE2, CE, R/L
Output "Low" voltage
VOL
IOL = 0.4 mA
Output "High" voltage
VOH
IOH = –0.4 mA
IIL
VI = 0 V
IIH
VI = VLS
Input "Low" current
Input "High" current
APPLICABLE PINS
CKV, SPV, MODE1,
0.8VLS
UNIT
V
5.0
µA
MODE2, CE, R/L
5.0
µA
50
µA
VDD – 0.4
V
ILS
For
150
µA
ICC
1-pulse mode
80
40
µA
µA
ILS
For jumping
100
300
µA
µA
ICC
2-pulse mode
100
µA
IEE
40
µA
IDD
100
µA
300
100
µA
µA
40
µA
ILS
ICC
For continuous
2-pulse mode
IEE
NOTE
V
CKV, SPV, MODE1,
IEE
Supply current (3)
MAX.
0.2VLS
V
IDD
Supply current (2)
TYP.
VEE + 0.4
OG1-OG240
IDD
Supply current (1)
MIN.
1
2
3
4
NOTES :
1. All input pins : 5 V
2. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 µs
SPV : Frequency = 60 Hz
Other input pins : 5 V
All output pins are opened.
3. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 µs
SPV : Frequency = 60 Hz
MODE2 : 0 V
Other input pins : 5 V
All output pins are opened.
4. CKV : Frequency = 31 kHz, "L" period width tWL = 16.2 µs
SPV : Frequency = 60 Hz
MODE1 : 0 V
Other input pins : 5 V
All output pins are opened.
11
LH1691
AC Characteristics
PARAMETER
Clock frequency
"L" clock pulse width
(VLS = +3.3±0.3 V (= VCC – VSS), TOPR = –30 to +85 ˚C)
SYMBOL CONDITIONS
fCKV
tWL
Clock rise time
tRCKV
Clock fall time
tFCKV
Data setup time
tSU
Data hold time
tH
Pulse rise time
tRSPV
Pulse fall time
tFSPV
Output transfer delay
time
tD
Output rise time
tR
Output fall time
tF
APPLICABLE PINS
CKV
CKV, SPV
MIN.
TYP.
0.5
UNIT
kHz
µs
100
ns
100
ns
ns
100
300
ns
SPV
CL = 500 pF
MAX.
100
OG1-OG240
100
100
ns
ns
3.0
µs
1.0
µs
1.0
µs
(VLS = +5.0±0.5 V (= VCC – VSS), TOPR = –30 to +85 ˚C)
PARAMETER
Clock frequency
"L" clock pulse width
SYMBOL CONDITIONS
fCKV
tWL
Clock rise time
tRCKV
Clock fall time
tFCKV
Data setup time
tSU
Data hold time
tH
Pulse rise time
tRSPV
Pulse fall time
tFSPV
Output transfer delay
time
tD
Output rise time
tR
Output fall time
tF
APPLICABLE PINS
CKV
CKV, SPV
SPV
CL = 500 pF
OG1-OG240
12
MIN.
TYP.
MAX.
100
0.5
UNIT
kHz
µs
100
ns
100
ns
ns
100
300
ns
100
100
ns
ns
2.0
µs
1.0
µs
1.0
µs
LH1691
Timing Chart
tFCKV
CKV
tRCKV
90%
10%
tSU
tH
tFSPV
SPV
tWL
90%
10%
90%
10%
50%
50%
50%
50%
50%
50%
tRSPV
tD
90%
tD
10%
90%
50%
OG1-OG240
(1-pulse Mode)
tD
50%
OG1-OG240
(Continuous 2-pulse Mode)
tD
50%
OG1-OG240
(Jumping 2-pulse Mode)
13
tD
50%
10%
tR
tD
50%
90%
50%
10%
tF
Ø2.0
(Good device hole)
LH1691F
VDD
COM2
2.2 (SR)
2.0 (SL)
8.5 (SL)
5.0±0.7
[5.0 (E.L.)]
COM1
2.5 (SL)
3.5 (SL)
5.7 (SR)
7.7±0.05
[9.2 (E.L.)]
[14.2 (E.L.)]
5.5
UPILEX is a trademark of UBE INDUSTRIES, LTD..
14
[3.5TYP. (3.2MIN.)]
0.083 (SL)
0.4±0.02
0.6±0.02
VEE
VSS
VCC
VSS
VEE
COM1
OG238
OG239
OG240
DUMMY
COM2
COM1
COM1
Substrate
Adhesive
Cu foil [thickness]
Solder resist
ø Tape Material
21.8 (SL)
UPILEX S75
#7100
SLP 18 µm
Epoxy resin
COM4
COM4
COM3
DUMMY
OG1
OG2
OG3
70 mm
Wide
4 pitches
(47.0)
[44.0 (E.L.)]
4.7 MAX.
(Resin area)
21.4 (SR)
VDD
42.9±0.08 (Mark)
0.9 (SL)
Chip
center
Sprocket
center
2-Ø1.5 (Cu hole)
2-Ø1.9 (PI)
2-Ø2.7 (Cu)
0.05
0.095
1.981±0.05
1.2MAX.
Total
0.75MAX.
Backside
0.3MAX.
Pattern side
PACKAGE
Tape width
Tape type
Perforation pitch
VLS
P0.17 x (248 – 1) = 41.99±0.08 W0.095±0.02
COM4
ø Tape Specification
MODE2
19.1MAX. (Resin area)
W0.40±0.02
VLS
26.4±0.05
TEST2
P1.20 x (23 – 1) =
MODE1
28.0 (SL)
VCC
1.981±0.05
0.6±0.02
CE
36.0±0.06
[34.0 (E.L.)]
4.75±0.05
21.8 (SL)
R/L
21.4 (SR)
SPV
63.949±0.12
COM3
0.4±0.02
0.9 (SL)
45˚
Device center
CKV
26.75±0.7
Film center
PACKAGES FOR LCD DRIVERS
(Unit : mm)
[0.15]
COM4
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