ASAHIKASEI [AK8811/12] AK8811/12 NTSC/PAL Digital Video Encoder GENERAL DESCRIPTION The AK8811 and AK8812 are low voltage, low power and small packaged Digital Video Encoder. They are suitable for a portable DVD or VCD player. They convert ITU-R.BT601/656 standard 8bit parallel data into analog composite video, S-Video or analog component signals Y/Cb/Cr in NTSC and PAL formats. AK8812 and AK8811 support Macrovision Copy Protection Rev.7.1(only AK8812), Closed captioning and Video Blanking ID(CGMS). These functions are controlled by high-speed I2C Bus interface. FEATURES • NTSC-M, PAL-B,D,G,H,I,M,N encoding. • Simultaneous composite video signal and S-video signal outputs • Y/Cb/Cr Component output (Based on EIAJ Guideline) • CCIR-656 4:2:2 8-bit Parallel Input - EAV Decoding • Master/Slave Operation - Digital Field Sync I/O - Digital Vertical/Horizontal Sync I/O • Y filtering 2 x over-sampling • C filtering 4 x over-sampling • Single 27MHz Clock (The polarity could be inverted by SYSINV pin) • Triple 10-bit DACs • I2C Interface (400kHz) • Closed Caption encoding (NTSC: line 21,284-SMPTE • Macrovision Copy Protection PAL: line 21,334-CCIR) Rev. 7.1* (Only for AK8812) • VBID, CGMS(EIAJ CPR-1024) • On-chip Color bar generator • Low Power Consumption • 3.3V only, CMOS Monolithic • 48pin LQFP Package * This device is protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098, and other intellectual rights. The use of Macrovision’s copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-per -view use only, unless otherwise authorized in written by Macrovision. Reverse engineering or disassembly is prohibited. Rev.1.1 -1- 2000/01 ASAHI KASEI [AK8811/12] x2 LPFLuma DATA 10-bit DAC YCbCr (4:2:2) D7 - D0 To LPF U,V Chroma-1 MOD x2 LPFChroma-2 Selector YUV (4:4:4) 10-bit DAC Video timing CHROMA / V Sub Carrier & Run in Clock Base Wave HSYNC Y DAC 10-bit FID/VSYNC COMPOSITE / U VREFIN Generator SYSINV VREF I2C VREFOUT Interface SYSCLK IREF /RESET DVDD Rev.1.1 DVSS SCL SDA 2 SELA AVDD AVSS 2000/01 ASAHI KASEI [AK8811/12] PIN LAYOUT PD5 PD6 PD7 DVSS SYSCLK DVDD PD8 DVDD HSYNC DVSS SYSINV FID/VSYNC 48pin LQFP 48 47 46 45 44 43 42 41 40 39 38 37 1 36 PD4 D7 2 35 PD3 D6 3 34 PD2 D5 4 33 PD1 D4 5 32 PD0 DVDD 6 31 DVDD DVSS 7 30 DVSS D3 8 29 IREF D2 9 28 VREFIN D1 10 27 VREFOUT D0 11 26 AVDD TEST1 12 25 AVSS AK8811/12 PD9 13 14 15 16 17 18 19 20 21 22 23 24 COMPOSITE / U AVSS CHROMA / V AVDD 3 Y AVSS /RESET DVSS SDA SCL SELA TEST2 Rev.1.1 2000/01 ASAHI KASEI [AK8811/12] PIN/FUNCTION No. Pin Name 2-5, 8-11 D7 - D0 41 SYSCLK 48 SYSINV I/O I I I I 18 /RESET 45 FID /VSYNC 46 HSYNC 15 SCL I 16 SDA I/O 14 SELA 27 VREFOUT 28 VREFIN 29 IREF 24 I/O I/O I O I Description 27MHz 8-Bit 4:2:2 multiplexed Y,Cb,Cr Data Input. For Rec.656 format, AK8811/12 decodes EAV. For non-Rec.656 format (without EAV), AK8811/12 operates in Master or Slave mode. 27MHz Clock Input. The polarity could be inverted by SYSINV. “L “ : data is latched with rising edge. “H” : data is latched with falling edge. After this pin becomes “L”, AK8811/12 starts the internal initializing sequence. After initializing sequence, AK8811/12 is set NTSC mode, Rec.656 decoding mode. All DACs Off condition. Either of FID or VSYNC selected by the register. Rec.656 decode mode :Output Master mode : Output Slave mode : Input FID shows that “L” is odd field and ”H” is even field. Rec.656 decode mode : Output Master mode : Output Slave mode : Input Serial interface clock Serial interface data The slave address is set with this pin. “L”:40H “H”:42H Output of the Internal Vref. Terminate with 0.1uF or more capacitor. Input of the Reference Voltage O The currents flow this pin adjusts the full-scale output current of the DAC. COMPOSITE/U O Output of Composite Video signal or component U 22 CHROMA/V Output of the C signal or component V 20 Y O O 21,26 AVDD P Analog +3.3V 6,31, 42,44 DVDD P Digital +3.3V 19,23,25 7,17,47, 40,30 AVSS G Analog Ground DVSS G Digital Ground 12,13 TEST1 TEST2 I Test pin. Ground for normal operation 1, 3239,43 PD[9:0] I/O Rev.1.1 Output of Luminance Signal. Test pin. Open for normal operation 4 2000/01 ASAHI KASEI [AK8811/12] ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Min Supply Voltage (VDD) Max Units -0.3 4.6V V -0.3 VDD+0.3 V Input Pin Current (Iin) - ±10 mA Analog Reference Current (IREF) - 0.21 mA Analog Output Current - 6.5 mA 1000 mW 125 °C DVDD, PVDD, AVDD Input Pin Voltage (Vin) Power Dissipation Storage Temperature -40 (Note)When all Ground pins(DVSS, AVSS) are set to 0V. Recommended Operating Conditions Parameter Min Typ. Max Units (VDD) 3.0 3.3 3.6 V Operating Temperature -40 85 °C Supply Voltage Rev.1.1 5 2000/01 ASAHI KASEI [AK8811/12] [Power Supply:3.3V Temperature:25°C] DC Characteristics Parameter Symbol Min Digital Input High Voltage VIH1 0.7VDD Digital Input Low Voltage VIL1 Digital Input leak Current IL Digital Output High Voltage VOH Digital Output Low Voltage Digital Maximum Load Capacitance I2C Input High Voltage I2C(SDA,SCL) VOL1 VIH2 Max Units Conditions V Note1) 0.3VDD V Note1) ±10 uA Note1) V IOH =-1mA Note 2) 0.4 V IOL = 2mA Note 2) 20 pF 2.4 0.7VDD V I2C Input Low Voltage I2C(SDA,SCL) VIL2 0.3VDD V I2C(SDA) Output Voltage VOL2 0.4 V IOL = 3mA Note 1) D[9:0],FID/VSYNC, HSYNC, SYSCLK, /RESET pin Note 2) FID/VSYNC, HSYNC pin Note ) Connected Test Pin to Ground, SELA and SYSINV Pin are desired polarity. Analog Characteristics and Dissipation Current [Power Supply:3.3V Temperature:25°C] Parameter Min DAC Resolution Typ Max 10 Units Conditions bit DAC Integral linearity error ±0.6 ±2 LSB DAC Differential linearity error ±0.4 ±1 LSB 1.28 1.38 V Note1) 5.0 mV Note2) ±5 % Note3) dB 1MHz Full Scale 30 pF Note4) 1.33 V DAC Output Full Scale Voltage 1.21 DAC Output offset Voltage Unbalances between DACs ±1 Isolation between DACs 50 DAC Load Capacitance Internal Reference Voltage 1.17 1.235 Internal Reference Drift 50 ppm/°C DAC Current (Active mode) 15 mA Note5) DAC Current (Sleep mode) 10 uA Note6) Total Current 50 mA Note7) 72 Note 1) Under the condition of output load 390Ω, IREF pin with 12kΩ, using internal reference. The output full-scale current IOUT is calculated as Full scale output voltage (typ. 1.28V) /390Ω=typ. 3.3mA. Note 2) DAC output when feeding code of 0 (Decimal). Note 3) Deviation between the DAC output when feeding 1V generating code of 800(Decimal). Note 4) The value is a design target. This value is not tested. Note 5) All DACs are operating. Note 6) All DACs are turned off with no system clock. Note 7) NTSC internal color bar with 3ch DACs operation and slave mode operation. DAC output pins is connected with only 390Ω load. Rev.1.1 6 2000/01 ASAHI KASEI [AK8811/12] AC Characteristic 1. SYSCLK Mid-points between fSYSCLK VIH and VIL. tCLKH tCLKL VIH SYSCLK VIL [ 3.3V Temperature 25°C ] Parameter SYSCLK Symbol Min. fSYSCLK Typ. 27 Max Unit MHz SYSCLK Pulse width H tCLKH 15 nsec SYSCLK Pulse width L tCLKL 15 nsec Rev.1.1 7 2000/01 ASAHI KASEI [AK8811/12] 2. In case of SYSINV = L (2-1). Pixel Data Input Pixel Data Input Timing VIH SYSCLK VIL tDH tDS D7 - D0 [ 3.3V Temperature 25°C ] Parameter Symbol Min Typ Max Units Data Setup Time tDS 5 nsec Data Hold Time tDH 8 nsec (2-2). Synchronizing Signal ( FID/VSYNC, HSYNC ) (2-2-1) Input Synchronizing Signal Timing VIH SYSCLK VIL tDH tDS FID/VSYNC, HSYNC [ 3.3V Temperature 25°C ] Parameter Symbol Min Data Setup Time tDS 5 nsec Data Hold Time tDH 8 nsec Rev.1.1 8 Typ. Max Units 2000/01 ASAHI KASEI (2-2-2) [AK8811/12] Output Synchronizing Signal Timing VIH SYSCLK tDEL FID/VSYNC, HSYNC [ 3.3V Temperature 25°C ] Parameter Delay from SYSCLK Symbol Min Typ. tDEL Max Units 27 nsec (2-3). Reset (Initialize) Reset Timing /RESET pRES SYSCLK [ 3.3V Temperature 25°C ] Parameter /RESET Pulse Width Rev.1.1 Symbol Min pRES 10 9 Typ. Max Units SYSCLK 2000/01 ASAHI KASEI [AK8811/12] (3). In case of SYSINV = H (3-1). Pixel Data Input Pixel Data Input Timing VIH SYSCLK VIL tDS tDH D7 - D0 [ 3.3V Temperature 25°C ] Parameter Symbol Min Typ Max Units Data Setup Time tDS 5 nsec Data Hold Time tDH 8 nsec (3-2). Synchronizing Signal ( FID/VSYNC, HSYNC ) (3-2-1) Input Synchronizing Signal Timing VIH SYSCLK VIL tDH tDS FID/VSYNC, HSYNC [ 3.3V Temperature 25°C ] Parameter Symbol Min Data Setup Time tDS 5 nsec Data Hold Time tDH 8 nsec Rev.1.1 10 Typ. Max Units 2000/01 ASAHI KASEI (3-2-2) [AK8811/12] Output Synchronizing Signal Timing VIL SYSCLK tDEL FID/VSYNC, HSYNC [ 3.3V Temperature 25°C ] Parameter Delay from SYSCLK Symbol Min Typ. tDEL Max Units 27 nsec (3-3). Reset (Initialize) Reset Timing /RESET pRES SYSCLK [ 3.3V Temperature 25°C ] Parameter /RESET Pulse Width Rev.1.1 Symbol Min pRES 10 11 Typ. Max Units SYSCLK 2000/01 ASAHI KASEI [AK8811/12] 2 (4). I C Bus (SCL 400kHz cycle mode) (4-1) I/O Timing 1 tBuf tHD:STA tF tR tSU:STO SDA tF tR SCL tSU:STA tLOW [ 3.3V Temperature 25°C ] Parameter Symbol Min tBUF 1.3 usec tHD:STA 0.6 usec Clock Pulse Low Time tLOW 1.3 usec Bus Signal Rise Time tR 300 nsec Bus Signal Fall Time tF 300 nsec Bus Free Time Hold Time (Start Condition) Max Units Setup Time(Start Condition) tSU:STA 0.6 usec Setup Time(Stop Condition) tSU:STO 0.6 usec All the figures shown above list are not restricted by AK8811/12 but are restricted by I2C Bus standard. Please see the I2C Bus standard for further details. (4-2) I/O Timing 2 tHD:DAT SDA tHIGH SCL tSU:DAT [ 3.3V Temperature 25°C ] Parameter Symbol Min. Data Setup Time tSU:DAT 100 (1) Data Hold Time tHD:DAT 0.0 tHIGH 0.6 Clock Pulse High Time Max. Unit. nsec 0.9 (2) usec usec (1) In case of normal I C bus mode tSU:DAT ≥250nsec (2) Using under minimum tLOW, this value must be satisfied. 2 Rev.1.1 12 2000/01 ASAHI KASEI [AK8811/12] FUNCTIONAL DESCRIPTION ♦ Reset When the reset pin [ /RESET ] set to “L”, AK8811/12 is in reset state. AK8811/12 starts in the internal initializing sequence at the trailing edge of the first SYSCLK after the reset pin is “L”. All internal registers are set to be default value by this initializing sequence. AK8811/12 needs at least 10 clock counts of SYSCLK for this reset operation. After the reset operation, the video output pins are in high-impedance. AK8811/12 requires SYSCLK for the reset operation. ♦ Master-Clock AK8811/12 requires 27MHz clock at SYSCLK pin for operation. Video input data (ITU-R BT.656) is sampled at the trailing edge of this 27MHz. SYSINV decides the edge direction. SYSINV = L Data is sampled at rising edge of SYSCLK. SYSINV = H Data is sampled at falling edge of SYSCLK. ♦ Video Signal Interface AK8811/12 can interface with the video input data by the following 3 modes. The mode is set by the register [ Interface mode register(00H) ]. 1. ITU-R BT.656 Format AK8811/12 decodes EAV in stream data and manages an internal synchronization. In this case, AK8811/12 outputs FID (odd : “L” even : “H”)/ VSYNC and HSYNC. CCIR-bit of [ Interface mode register (00H) ] should be set “1” . 2. ITU-R BT.656 like Format (4:2:2 Y/Cb/Cr) There are Master and Slave modes, for ITU-R BT.656 like Format which does not include EAV. In this mode, CCIR-bit of [ Interface mode register(00H) ] should be set “0” . <Master Mode> AK8811/12 provides FID/VSYNC and HSYNC to an external device according to the AK8811/12 internal timing counter. AK8811/12 starts to sample the input data at the fixed value on the internal pixel counter. In this mode, following setting should be done to [Interface mode register(00H)]. CCIR-bit = 0 MAS-bit = 1 <Slave Mode> FID/VSYNC and HSYNC are supplied by an external device. AK8811/12 samples the data as same manner of Master mode. In this mode, following setting should be done to [Interface mode register(00H)]. CCIR-bit = 0 MAS-bit = 0 Rev.1.1 13 2000/01 ASAHI KASEI [AK8811/12] ♦ Video Signal Conversion Video reconstruction module converts the multiplexed data (ITU-R. BT601 Y/Cb/Cr) to the interlace format of NTSC-M, PAL-M, PAL-B,D,G,H,I,N and other formats (ex. NTSC-4.43 and PAL60). The video reconstruction format, the line number, the color encode way(NTSC or PAL) and the frequency of Color Sub-carrier is specified by [Video Process 1 register(01H)]. (cf. Burst Signal Table) The frequency and the phase of Color Sub-carrier are also adjustable by [Sub C. Freq. register(06H)] and [Sub C. Phase register(07H)]. The Sub-carrier has a free-running mode and a reset-mode. In the reset-mode, the Sub-carrier is reset automatically to the initial phase for every 4 fields (NTSC) or 8 fields (PAL). ♦ Component Video Output Video output mode is set by VS-bit of [ Video Process 3 register (03H) ]. AK8811/12 can output not only the set of composite video signal and S-video signal but also can output component video signals(Y/Cb/Cr). The component video signals are complied with EIAJ guideline 1998/3. VS-bit = 0 : composite video signal and S-video signal output VS-bit = 1 : component video signal output ♦ Luminance Filter Luminance signal passes through the 2x Low Pass filter Fig.1 is the characteristic of Luminance Filter. 0.0 1.0 2.0 3.0 4.0 Frequency [MHz] 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 10 0 Gain [dB] -10 -20 -30 -40 -50 -60 -70 Fig. 1 Rev.1.1 Luminance Filter 14 2000/01 ASAHI KASEI [AK8811/12] ♦ Chroma Filter Chroma signals (Cb,Cr) before Sub-carrier modulation pass through the 1.3 MHz Low pass filter shown in Fig.2. Chroma signal modulated by Sub-carrier passes through the filter shown in Fig.3. Frequency [MHz] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 10 0 Gain [dB] -10 -20 -30 -40 -50 -60 -70 Fig. 2 0.0 1.0 2.0 3.0 4.0 Chroma-1 LPF Frequency [MHz] 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 10 0 Gain [dB] -10 -20 -30 -40 -50 -60 -70 Fig. 3 Chroma-2 LPF Rev.1.1 15 2000/01 ASAHI KASEI [AK8811/12] ♦ Color burst signal Color burst signal is generated by 24bits-length Digital Frequency Synthesizer. The Default frequency of the color burst is selected by [Video Process 1 Register(0x01)]. Standard NTSC-M Sub-carrier Freq. Video Process 1 [MHz] [VM1,VM0] [0,0] 3.57954545 PAL-M 3.57561188 [0,1] PAL-B,D,G,H,I PAL-N(Arg.) PAL-N(non-Arg.) PAL60 NTSC-4.43 4.43361875 3.5820558 4.43361875 4.43361875 4.43361875 [1,1] [1,0] [1,1] [1,1] [1,1] Burst Signal Table Sub-carrier frequency 3.57561188MHz is allowed when PAL-M mode is selected. The burst frequency and initial phase resolution are as follows. Frequency resolution SCH Phase resolution 0.8046Hz 360°/256 ♦ Video DAC AK8811/12 has the three current driven 10bits-DACs at 27MHz operation. The full scale voltage of DAC is determined by the current output from IREF pin. Typical output voltage is 1.28Vo-p under the condition of VREFIN 1.235V, 12KΩ between IREF pin and Ground(AVSS) and DAC load resistance of 390Ω. This full-scale voltage should be set in the range of 1.17V to 1.33V by adjusting the resistor which terminates IREF pin. Each DAC output can be set to “active state” or to “inactive state” individually by [DAC Mode register(05H)]. When DAC is in “inactive state”, the output is Hi-impedance. When all DACs are set to “inactive state”, the analog part of AK8811/12 goes into sleep mode. In this case AK8811/12 stops outputing the reference voltage(VREF) output. When any DAC is switched over in “active state” from sleep mode, AK8811/12 starts outputing reference voltage. In this case AK8811/12 needs several milisecond for VREF wake-up time. Using internal VREF as the reference voltage, connect [VREF OUT] pin with [VREF IN] pin and [VREF OUT] pin is terminated with more than 0.1uF capacitor. ♦ Use external Reference Voltage In order to improve the accuracy of DAC output, external reference voltage may be used. In this case, VREFOUT pin still needs to be terminated with more than 0.1uF capacitor. Rev.1.1 16 2000/01 ASAHI KASEI [AK8811/12] ♦ Copy Protection Macrovision Copy Protection Rev.7.1 Information about the Macrovision encoding functions of the AK8812 is available to Macrovision licensees. Macrovision may be contacted at: Macrovision Corporation 1341 Orleans Drive Sunnyvale, California 94089 USA Attention: ACP-PPV Technical Support FAX: (408) 743 – 8610 Rev.1.1 17 2000/01 ASAHI KASEI [AK8811/12] ♦ Closed Caption and Extended Data AK8811/12 supports both Closed Captioning and Extended Data. They are controlled “ON” or ”OFF” respectively by [ Video Process 2 Register(02H) ]. Each data consists of 2 continuous bytes register( Closed Caption R (16H,17H) ), and it is recognized as the data is renewed when the second byte(17H register) is written in the register. After the data is renewed, AK8811/12 encodes Closed Captioning and Extended Data at the designated line. If the data isn’t renewed, AK8811/12 outputs “ASCII-NULL” code. The data is supposed as Odd Parity and 7 bit USASCII code. Host should provide a parity bit. *In PAL encoding mode, AK8811/12 outputs them at the same timing and same pattern as NTSC. *The line where Closed Captioning data is encoded is as follows. 525/60 System (SMPTE) 625/50 System (CCIR) Closed Caption 21 Line default 21 Line default Extended Data 284 Line default 334 Line default 10.5±0.25uS TWO 7-Bit+PARITY ASCII Characters (DATA) 12.91 uS S T 50±2IRE A 7 Cycles of 0.5035MHz (Clock RUN-IN) 40IRE P A R I T Y P A R I T Y 240±48nsec RISE/FALL TIMES (2T BAR SHAPING) 10.003±0.25uS 27.382 uS ( 33.764 uS ) 61 uS Fig. 4 Closed Captioning Wave form Rev.1.1 18 2000/01 ASAHI KASEI [AK8811/12] ♦ Video ID AK8811/12 supports Video ID (EIAJ standard, CPR-1204) encoding for the distinction of an aspect ratio, etc. Setting or Resetting the VBID-bit of [ Video Process 2 Register(02H) ], this function is switched On/Off. The data is set by using [ Video ID Data Register(1AH, 1BH) ]. VBID Data Renewal Timing. VSYNC Set Control Register NEW DATA SI/SDA Data #1 OLD DATA NEW DATA Fig. 5 VBID Data renewal Timing VBID Data Layout VBID is consists of 20 bits and its format is shown as follows. AK8811/12 generates CRC code automatically and appends it to the data. Initial value of the Polynomial is 1. bit 20 bit 1 DATA WORD 0 2 bit WORD 1 4 bit WORD 2 8 bit CRC 6 bit Fig. 6 VBID code assignment Rev.1.1 19 2000/01 ASAHI KASEI [AK8811/12] VBID Waveform IRE 100 Ref. ••••• bit 20 bit 1 bit 2 bit 3 70 IRE ± 10 IRE 0 IRE -5 IRE / +10 IRE 0 2.235 usec ± 50ns -40 11.2 usec ± 0.3 usec 49.1 usec ± 0.44 usec Fig. 7 VBID Wave Form 525/60 system 625/50 system Amplitude 70 IRE 490 mV Encode Line 20/283 20/333 VBID parameter table Rev.1.1 20 2000/01 ASAHI KASEI [AK8811/12] ♦ AK8811/12 Interface Timing (Part 1) Master mode & ITU-R BT. 656 mode On ITU-R BT.656 decoding mode or master mode operation, AK8811/12 outputs HSYNC and FID or VSYNC (selected by register). When AK8811/12 receives ITU-R BT. 656 signal, AK8811/12 decodes [EAV] code in the data for synchronization then outputs the HSYNC. AK8811/12 outputs HSYNC at the rising edge of SYSCLK in the timing of the 32nd/24th(NTSC/PAL) data slot, which is counted from the [EAV] starting point as below. (See also AC Characteristics 2-2[Input Synchronizing Signal]) On master mode operation, the front device connected with AK8811/12 (ex. MPEG Decoder) starts to set Cb on the 276th/288th(NTSC/PAL) slot, after starting to count HSYNC falling edge as 32nd/24th(NTSC/PAL) slot. FID/VSYNC is output synchronously with HSYNC at the timing of solid line as in Fig. 10 Video Field. 244T (264T) Cb Y Cr Y ITU-R. BT601(656) HSYNC 27MHz SYSCLK 32 (24) 276 (288) NTSC(PAL) T=1/27MHz * Uncertainty of 1T occurs according to the Reset timing. Fig. 8 Interface Timing (ITU-R BT.656 or Master mode) Rev.1.1 21 2000/01 ASAHI KASEI [AK8811/12] ♦ AK8811/12 Interface Timing (Part 2) Slave mode On slave mode operation, HSYNC and FID or VSYNC (Selected by register) are input to AK8811/12. AK8811/12 monitors the transition of HSYNC at the timing of the rising edge of SYSCLK. (Refer to AC Characteristic 2-1. [Input Synchronizing Signal]) After AK8811/12 recognizes HSYNC is Low-logic, AK8811/12 sets the slot number to the 32nd/24th(NTSC/PAL), internally, then AK8811/12 starts to sample the data as Cb on 276th/288th(NTSC/PAL) slot. Video field is recognized the transition timing between FID/VSYNC and HSYNC. (Fig.10. Video Field) As in the figure, there is a toreralnce of ±1/4H. 244T (264T) Cb Y Cr Y ITU-R. BT601(656) HSYNC 27MHz SYSCLK 276 (288) 32 (24) NTSC(PAL) T=1/27MHz * Uncertainty of 1T occurs according to the Reset timing. Fig. 9. Interfacing timing (Slave mode) 1H 1/2 H 1/2 H HSYNC 1/2 H ODD Field Start FID/VSYNC 1/2 H EVEN Field Start FID/VSYNC Fig. 10. Video Field Rev.1.1 22 2000/01 ASAHI KASEI [AK8811/12] ♦ HSYNC FID/VSYNC Timing 3 4 5 6 7 HSYNC EVEN FID ODD VSYNC 266 267 268 269 270 HSYNC ODD FID EVEN VSYNC Fig. 11. NTSC 625 1 / PAL/M 2 3 4 HSYNC FID ODD EVEN VSYNC 313 314 315 316 317 HSYNC ODD FID EVEN VSYNC Fig. 12 Rev.1.1 PAL 23 2000/01 ASAHI KASEI [AK8811/12] ♦ Color Bars AK8811/12 generates the Common Color Bar signal for NTSC and PAL internally. The generated Color Bar is “100% Amplitude, 100% Saturation”. BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE Luminance White level Blank level Sync level Chrominace The following values are code for ITU-R. BT601 Cb Y Cr Rev.1.1 WHITE 128 235 128 YELLOW 16 210 146 CYAN 166 170 16 GREEN 54 145 34 24 MAGENTA 202 106 222 RED 90 81 240 BLUE 240 41 110 BLACK 128 16 128 2000/01 ASAHI KASEI [AK8811/12] ♦ Component video output The levels of each Component video outputs are following. ( Color bar NTSC 100/0/100/0 ) Magnitude is compliant to the guideline of EIAJ CPR-1024. White 714mV (100 IRE) Yellow Cyan Green Magenta Red Blue Black 286mV 350mV -350mV 350mV -350mV [mV] Cb Y Cr WHITE 0 714 0 Y Signal Level YELLOW -350 632 57 : CYAN 118 500 -350 GREEN -232 418 -293 MAGENTA 232 296 293 RED -118 213 350 BLUE 350 82 -57 BLACK 0 0 0 1.00Vpp Y ( Video Signal Level ) : 0.714V Y ( Sync level ) : 0.286V Setup : None Cb/Cr Signal Level : Rev.1.1 ± 0.350V 25 2000/01 ASAHI KASEI [AK8811/12] ♦ I2C Control Sequence AK8811/12 is controlled by I2C bus. The slave address can be selected as 40H or 42H by selecting SELA pin. SELA pull-down Pull-up 40H 42H Operation : Write Sequence: S Slave Address W A Sub Address A Data_1 A Data_n A/A Stp *Continuous data writing is capable for the all registers. Sequential Read: (Only Sub Address of 24H, 25H, 26H could be read ) S Slave W A Sub Address DATA_24H 24H A rS Slave A DATA_25H S : Start Condition A R A DATA_26H A Stp by Host A : Acknowledge(SDA LOW) A: Not Acknowledge(SDA HIGH) Stp : Stop Condition by AK8811/12 R/W: 1: Read 0:Write - It ignores the general call Rev.1.1 26 2000/01 ASAHI KASEI [AK8811/12] AK8811/12 REGISTER MAP Sub Address 00H 01H 02H 03H 04H 05H 06H 07H 08H-15H 16H 17H 18H 19H 1AH 1BH 1CH-23H 24H 25H 26H 27H-29H Rev.1.1 Name Interface Mode Video Process 1 Video Process 2 Video Process 3 RESERVED DAC Mode Sub C. Freq. Sub C. Phase RESERVED Closed Caption R Closed Caption R Closed Caption R Closed Caption R Video ID Data Video ID Data RESERVED STS Data Device ID Device REV RESERVED R/W Explanation W W W W Setting Interface mode Setting Standard (NTSC, PAL etc.) Setting Closed Caption/Extended Data/VBID Setting Composite signal or Component Signal Adjusting chroma/Luma Delay W W W Each DAC On/Off Switch Adjusting Sub-carrier frequency Adjusting Sub-carrier phase W W W W W W Closed Caption Lower byte Data Closed Caption Upper byte Data Extended Lower byte Data Extended Upper byte Data Video ID Lower byte Data Video ID Upper byte Data R R R Status Device ID Revision 27 2000/01 ASAHI KASEI [AK8811/12] Interface Mode Register (W only default A4H) Sub Add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00H BLN4 BLN3 BLN2 BLN1 BLN0 FID MAS CCIR Symbol BLN4 - BLN0 Value ***** FID 0 1 0 1 MAS CCIR 0 1 Description Line Blanking No. Select VSYNC Select FID Slave mode Master mode When CCIR=0,it’s valid CCIR656 non-decode CCIR656 decode default 10100 default default default Video Process 1 Register (W only default 18H) Sub Add 01H bit 7 Reserved bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 CBG SETUP SCR VM3 VM2 VM1 VM0 Symbol CBG SETUP SCR VM3 – VM2 VM1-VM0 Value 0 1 0 1 0 1 00 01 10 11 00 01 10 11 Description Video Encode Generates color bar No Set-up 7.5 IRE Set-up Sub C. Phase Reset off Standard Field Reset 525/60 525/60 PAL (PAL-M etc.) Reserved PAL 3.57954545 MHz 3.57561188 MHz (PAL-M only) 3.5820558 MHz 4.43361875 MHz default default default default default Register Setting of each standard is showend as following ; VM3-VM0 NTSC-M 0000 PAL-B,D,G,H,I 1111 PAL-M 0101 PAL-60 0111 NTSC4.43 0011 • When SCR is “ON”, the Subcarrier Phase is reset every 4 fields for NTSC, every 8 fields for PAL. • Even when SETUP is “ON”, there is no Set-up (Pedestal) during the blanking lines. Rev.1.1 28 2000/01 ASAHI KASEI [AK8811/12] Video Process 2 Register (W only default 00H) Sub Add 02H bit 7 bit 6 bit 5 bit 4 bit 3 Reserved Reserved Reserved Reserved Reserved Symbol CC284 CC21 VBID Value 0 1 0 1 0 1 bit 2 bit 1 bit 0 CC284 CC21 VBID Description Extended Data OFF ON Closed Caption OFF ON Video ID OFF ON default default default Video Process 3 Register (W only default 00H) Sub Add 03H bit 7 Reserved bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 VS SYD2 SYD1 SYD0 CYD2 CYD1 CYD0 Symbol Video Set SYD2 - SYD0 CYD2 - CYD0 Value 0 1 Description Composite, S-Video set Component set S-Video Y Component delay no. from Chroma: 2's comp. Composite Y Component delay no. from Chroma: 2's comp. default default 000 default 000 • VS-bit selects the one of the setting of signals from the 2 signal sets (Composite, Y /C or Y/Cb/Cr) • S video and Y component of the composite signal can be shifted for the chroma signal independently at ±3-system clock (27MHz). Rev.1.1 29 2000/01 ASAHI KASEI [AK8811/12] DAC Mode Register (W only default 00H) Sub Add 05H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 Reserved Reserved Reserved Reserved Reserved OUTCP Symbol OUTCP OUTC OUTY Value 0 1 0 1 0 1 bit 1 bit 0 OUTC OUTY Description Composite video signal or U signal output : OFF default Composite video singal or U signal output : ON Chroma signal or V signal output : OFF default Chroma signal or V signal output : ON Y signal output : OFF default Y signal output : ON • Video output of AK8811/12 (DAC) can be forced “OFF” independently. The output of DAC that is forced “OFF” is Hi-impedance. When three DACs are forced “OFF”, then the internal VREF is also forced “OFF”. In this case, it takes several miliseconds before the internal VREF reaches the proper voltage after any DAC becomes “ON”. SubC Freq. Register (W only default 00H) Sub Add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 06H SUBF7 SUBF6 SUBF5 SUBF4 SUBF3 SUBF2 SUBF1 SUBF0 Symbol SUBF7-SUBF0 Value Description Adjustment of frequency between +127 and –128 step of 0.8Hz default 0 • AK8811/12 generates the necessary sub-carrier frequency from a system clock by DFS (Digital Frequency Synthesizer) • Frequency of default is adjustable by specifying this bit. This bit adjusts the default frequency. SubC Phase Register (W only default 00H) Sub Add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 07H SUBP7 SUBP6 SUBP5 SUBP4 SUBP3 SUBP2 SUBP1 SUBP0 Symbol SUBP7 – SUBP0 Value description Step: (360° /256°) default 0 • Sub- carrier phase is adjustable by (360° /256) step. Rev.1.1 30 2000/01 ASAHI KASEI [AK8811/12] Closed Caption Register (W only default 00H) Sub Add bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 16H 17H 18H 19H CC1[7] CC2[7] CC3[7] CC4[7] CC1[6] CC2[6] CC3[6] CC4[6] CC1[5] CC2[5] CC3[5] CC4[5] CC1[4] CC2[4] CC3[4] CC4[4] CC1[3] CC2[3] CC3[3] CC4[3] CC1[2] CC2[2] CC3[2] CC4[2] CC1[1] CC2[1] CC3[1] CC4[1] CC1[0] CC2[0] CC3[0] CC4[0] Symbol CC1[7] – CC1[0] CC2[7] – CC2[0] CC3[7] – CC3[0] CC4[7] – CC4[0] Description Line 21 –1 Line 21 –2 Line 284 -1 Line 284 -2 Closed Caption Extended Data • When the 2nd byte of Closed Caption Data and Extended Data is written in, AK8811/12 recognizes the renewed data and encodes it in the video line. When the data is not renewed AK8811/12 outputs NULL code. Video ID Data Register (W only default 00H) Sub Add 1AH 1BH bit 7 bit 6 Reserved Reserved bit 7 bit 8 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 1 bit 9 bit 2 bit 10 bit 3 bit 11 bit 4 bit 12 bit 5 bit 13 bit 6 bit 14 • Please write value 0 at Reserved bit. • Bit numbers correspond to Fig. 5 VBID code assignment. • AK8811/12 generates CRC 6 bit data automatically. Rev.1.1 31 2000/01 ASAHI KASEI [AK8811/12] Followings are read only register STATUS REGISTER (R only) Sub Add bit7 bit6 Reserved Reserved 24H Symbol EN284 EN21 SYNC STS2 - STS 0 bit5 EN284 Value 0 1 0 1 0 1 *** bit4 EN21 bit3 SYNC bit2 STS2 bit1 STS1 bit0 STS 0 Description Wait for the appointed video line to encode. Ready for the C.C. data input to the register. Wait for the appointed video line to encode. Ready for the C.C. data input to the register. Missing synchronization in slave mode. Synchronization was achieved. Shows the processing field No. • Status Register becomes effective when SYNC bit turns to “1”. When in master mode operation, this bit is ”1”. • STS2-STS2 holds the field number of processing. Some time lag is inevitable for the I2C acquisition. • Closed caption data should be renewed after firm that the EN* flag is “1”. EN* flag bit is cleared after the second byte( Sub address 17H,19H) was accessed. • Reserved-bit is always value 0. Device ID (R only default 21H) Sub Add 25H bit7 0 bit6 0 bit5 0 bit4 1 Bit3 0 bit2 0 bit1 0 bit0 1 bit2 0 bit1 1 bit0 0 bit2 0 bit1 0 bit0 1 • Represents device ID. AK8811 is assigned 11H. Sub Add 25H bit7 0 bit6 0 bit5 0 bit4 1 Bit3 0 • Represents device ID. AK8811/12 is assigned 12H. Device REV (R only default 01H) Sub Add 26H bit7 0 bit6 0 bit5 0 bit4 0 Bit3 0 • Represents device revision. Initial is 01H. Rev.1.1 32 2000/01 ASAHI KASEI [AK8811/12] SYSTEM CONNECTION EXAMPLE COMPOSITE D0 - D7 MPEG2 SYSCLK LUMA - CHROMA - Amp + Filter 390 Ω 75 Ω Decoder FID/ VSYNC HSYNC VREFIN SCL Digital 3.3V 0.1u AK8811/12 SDA I2C Bus VREFOUT 10uF IREF DVDD DVSS AVSS 12 kΩ AVDD Analog 3.3V 10u 0.1u 0.1u 10u Digital GND Rev.1.1 33 Analog GND 2000/01 ASAHI KASEI [AK8811/12] PACKAGE 48pin LQFP 1.70 Max 9.0 ± 0.2 1.4 TYP 7.0 9.0 ± 0.2 0.13 ± 0.13 48 1 0.5 0.22 ± 0.08 0.17 ± 0.08 0.10 M 0°∼10° Units = mm 0.5 ± 0.2 0.10 Package & Lead frame material Package molding compound : Epoxy Lead frame material : Cu Lead frame surface treatment : Rev.1.1 34 Solder plate 2000/01 ASAHI KASEI [AK8811/12] MARKING 1) Pin #1 indication 2) Date Code : XXXXXXX (7 digits) 3) Marketing Code : AK8811/AK8812 4) Country of Origin 5) Asahi Kasei Logo Rev.1.1 35 2000/01 ASAHI KASEI [AK8811/12] IMPORTANT NOTICE ● These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. ● AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ● Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ● AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, unclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ● It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. Rev.1.1 36 2000/01