NCP5104 High Voltage, Half Bridge Driver The NCP5104 is a High Voltage Power gate Driver providing two outputs for direct drive of 2 N-channel power MOSFETs or IGBTs arranged in a half-bridge configuration. It uses the bootstrap technique to insure a proper drive of the High-side power switch. http://onsemi.com Features •High Voltage Range: up to 600 V •dV/dt Immunity ±50 V/nsec •Gate Drive Supply Range from 10 V to 20 V •High and Low Drive Outputs •Output Source / Sink Current Capability 250 mA / 500 mA •3.3 V and 5 V Input Logic Compatible •Up to VCC Swing on Input Pins •Extended Allowable Negative Bridge Pin Voltage Swing to -10 V for Signal Propagation •Matched Propagation Delays between Both Channels •1 Input with Internal Fixed Dead Time (520 ns) •Under VCC LockOut (UVLO) for Both Channels •Pin to Pin Compatible with Industry Standards •These are Pb-Free Devices MARKING DIAGRAMS 1 SOIC-8 D SUFFIX CASE 751 •Half-Bridge Power Converters P5104 ALYW G 1 NCP5104 AWLG YYWW 1 PDIP-8 P SUFFIX CASE 626 NCP5104 A L or WL Y or YY W or WW G or G Typical Applications 8 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package PINOUT INFORMATION VCC IN SD GND 1 2 3 4 VBOOT DRV_HI BRIDGE DRV_LO 8 7 6 5 8 Pin Package ORDERING INFORMATION Device Package Shipping† NCP5104PG PDIP-8 (Pb-Free) 50 Units / Rail NCP5104DR2G SOIC-8 (Pb-Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. © Semiconductor Components Industries, LLC, 2008 March, 2008 - Rev. 2 1 Publication Order Number: NCP5104/D NCP5104 Vbulk + C1 D4 GND Q1 Vcc T1 C3 U1 8 VBOOT Vcc 2 7 IN DRV_HI 3 6 SD Bridge 4 5 GND DRV_LO 1 GND NCP1395 L1 Out+ + C4 C3 Lf OutD2 C6 Q2 NCP5104 GND D1 GND GND R1 D3 GND U2 Figure 1. Typical Application Resonant Converter (LLC type) Vbulk + C1 C5 D4 GND Q1 Vcc C3 GND T1 1 SG3526 MC34025 TL594 NCP1561 2 3 4 U1 8 VBOOT Vcc 7 IN DRV_HI 6 Bridge SD 5 GND DRV_LO L1 C4 Out+ + C3 Out- D2 C6 NCP5104 GND D1 Q2 GND GND R1 D3 GND U2 Figure 2. Typical Application Half Bridge Converter VCC VCC VBOOT UV DETECT IN DEAD TIME GENERATION PULSE TRIGGER S Q R Q LEVEL SHIFTER GND UV DETECT DRV_HI BRIDGE VCC GND SD DRV_LO DELAY GND GND GND Figure 3. Detailed Block Diagram http://onsemi.com 2 NCP5104 PIN DESCRIPTION ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Pin Name Description VCC Low Side and Main Power Supply IN Logic Input SD Logic Input for Shutdown GND Ground DRV_LO Low Side Gate Drive Output VBOOT Bootstrap Power Supply DRV_HI High Side Gate Drive Output BRIDGE Bootstrap Return or High Side Floating Supply Return MAXIMUM RATINGS Rating VCC VCC_transient Symbol Main power supply voltage Main transient power supply voltage: IVCC_max = 5 mA during 10 ms Value Unit -0.3 to 20 V 23 V VBOOT VHV: High Voltage BOOT Pin -1 to 620 V VBRIDGE VHV: High Voltage BRIDGE pin -1 to 600 V VBRIDGE Allowable Negative Bridge Pin Voltage for IN Signal Propagation to DRV_LO -10 V VBOOT-VBRIDGE VHV: Floating supply voltage -0.3 to 20 V VDRV_HI VHV: High side output voltage VBRIDGE - 0.3 to VBOOT + 0.3 V VDRV_LO Low side output voltage -0.3 to VCC + 0.3 V 50 V/ns -1.0 to VCC + 0.3 V 2 200 kV V dVBRIDGE/dt VIN, VSD Allowable output slew rate Inputs IN & SD ESD Capability: - HBM model (all pins except pins 6-7-8 in 8) - Machine model (all pins except pins 6-7-8) Latch up capability per JEDEC JESD78 RqJA TJ_max °C/W Power dissipation and Thermal characteristics PDIP-8: Thermal Resistance, Junction-to-Air SO-8: Thermal Resistance, Junction-to-Air 100 178 Maximum Operating Junction Temperature +150 °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. http://onsemi.com 3 NCP5104 ELECTRICAL CHARACTERISTIC (VCC = Vboot = 15 V, VGND = Vbridge, -40°C < TJ < 125°C, Outputs loaded with 1 nF) TJ -40°C to 125°C Symbol Min Typ Max Units Output high short circuit pulsed current VDRV = 0 V, PW v 10 ms (Note 1) IDRVsource - 250 - mA Output low short circuit pulsed current VDRV = Vcc, PW v 10 ms (Note 1) IDRVsink - 500 - mA Output resistor (Typical value @ 25°C) Source ROH - 30 60 W Output resistor (Typical value @ 25°C) Sink ROL - 10 20 W High level output voltage, VBIAS-VDRV_XX @ IDRV_XX = 20 mA VDRV_H - 0.7 1.6 V Low level output voltage VDRV_XX @ IDRV_XX = 20 mA VDRV_L - 0.2 0.6 V Turn-on propagation delay (Vbridge = 0 V) (Note 2) tON - 620 800 ns Turn-off propagation delay (Vbridge = 0 V or 50 V) (Note 3) tOFF - 100 170 ns Shutdown propagation delay, when Shutdown is enabled tsd_en - 100 170 ns Shutdown propagation delay, when Shutdown is disabled tsd_dis - 620 800 ns tr - 85 160 ns Output voltage fall time (from 90% to 10% @ VCC = 15 V) with 1 nF load tf - 35 75 ns Propagation delay matching between the High side and the Low side @ 25°C (Note 4) Dt - 10 45 ns Internal fixed dead time (Note 5) DT 400 520 650 ns Low level input voltage threshold VIN - - 0.8 V Input pull-down resistor (VIN < 0.5 V) RIN - 200 - kW High level input voltage threshold VIN 2.3 - - V Logic “1” input bias current @ VIN = 5 V @ 25°C IIN+ - 5 25 mA Logic “0” input bias current @ VIN = 0 V @ 25°C IIN- - - 2.0 mA Vcc_stup 8.0 8.9 9.8 V Vcc_shtdwn 7.3 8.2 9.0 V Vcc_hyst 0.3 0.7 - V Vboot_stup 8.0 8.9 9.8 V Vboot UV Shut-down voltage threshold Vboot_shtdwn 7.3 8.2 9.0 V Hysteresis on Vboot Vboot_shtdwn 0.3 0.7 - V IHV_LEAK - 5 40 mA Consumption in active mode (Vcc = Vboot, fsw = 100 kHz and 1 nF load on both driver outputs) ICC1 - 4 5 mA Consumption in inhibition mode (Vcc = Vboot) ICC2 - 250 400 mA Vcc current consumption in inhibition mode ICC3 - 200 - mA Vboot current consumption in inhibition mode ICC4 - 50 - mA Rating OUTPUT SECTION DYNAMIC OUTPUT SECTION Output voltage rise time (from 10% to 90% @ VCC = 15 V) with 1 nF load INPUT SECTION SUPPLY SECTION Vcc UV Start-up voltage threshold Vcc UV Shut-down voltage threshold Hysteresis on Vcc Vboot Start-up voltage threshold reference to bridge pin (Vboot_stup = Vboot - Vbridge) Leakage current on high voltage pins to GND (VBOOT = VBRIDGE = DRV_HI = 600 V) 1. 2. 3. 4. 5. Parameter guaranteed by design. TON = TOFF + DT Turn-off propagation delay @ Vbridge = 600 V is guaranteed by design. See characterization curve for Dt parameters variation on the full range temperature. Timing diagram definition see: Figure 4, Figure 5 and Figure 6. http://onsemi.com 4 NCP5104 IN SD DRV_HI DRV_LO Figure 4. Input/Output Timing Diagram Note: DRV_HI output is in phase with the input IN 50% 50% tr ton 90% Dead time DRV_HI 90% 10% toff tf toff 10% tf Dead time tr 90% 90% ton DRV_LO 10% Ton = Toff + DT Figure 5. Timing Definitions http://onsemi.com 5 10% NCP5104 IN 50% 50% toff_HI DeadTime1 90% DRV_HI 10% toff_LO DeadTime2 90% DRV_LO Matching Delay1=toff_HI-toff_LO Matching Delay 2=(toff_LO+DT1)-(toff_HI+DT2) 10% Figure 6. Matching Propagation Delay Definition 50% 50% SD tsd_en DRV_HI tsd_dis 90% 10% DRV_LO Figure 7. Shutdown Waveform Definition http://onsemi.com 6 NCP5104 CHARACTERIZATION CURVES 900 TON, PROPAGATION DELAY (ns) TON, PROPAGATION DELAY (ns) 800 750 700 TON Low Side 650 600 550 TON High Side 500 450 12 14 16 VCC, VOLTAGE (V) 18 800 750 TON Low Side 700 650 600 550 TON High Side 500 450 400 -40 400 10 850 20 Figure 8. Turn ON Propagation Delay vs. Supply Voltage (VCC = VBOOT) 20 40 60 80 TEMPERATURE (°C) 100 120 160 140 TOFF, PROPAGATION DELAY (ns) TOFF, PROPAGATION DELAY (ns) 0 Figure 9. Turn ON Propagation Delay vs. Temperature 160 TOFF High Side 120 100 80 TOFF Low Side 60 40 20 10 12 14 16 VCC, VOLTAGE (V) 18 140 TOFF High Side 120 TOFF Low Side 100 80 60 40 20 0 -40 0 20 Figure 10. Turn OFF Propagation Delay vs. Supply Voltage (VCC = VBOOT) -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 Figure 11. Turn OFF Propagation Delay vs. Temperature 160 TOFF, PROPAGATION DELAY (ns) 800 TON, PROPAGATION DELAY (ns) -20 700 600 500 400 300 200 100 0 140 120 100 80 60 40 20 0 0 10 20 30 40 50 0 10 20 30 40 VBRIDGE VOLTAGE (V) VBRIDGE VOLTAGE (V) Figure 12. High Side Turn ON Propagation Delay vs. VBRIDGE Voltage (VCC = VBOOT) Figure 13. High Side Turn OFF Propagation Delay vs. VBRIDGE Voltage (VCC = VBOOT) http://onsemi.com 7 50 NCP5104 CHARACTERIZATION CURVES 160 160 TON, RISETIME (ns) 140 TON, RISETIME (ns) 120 100 80 tr High Side 60 40 120 100 0 10 80 60 40 12 14 16 VCC, VOLTAGE (V) 18 0 -40 20 Figure 14. Turn ON Risetime vs. Supply Voltage (VCC = VBOOT) -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 Figure 15. Turn ON Risetime vs. Temperature 60 80 70 tf High Side 50 60 TOFF, FALLTIME (ns) TOFF, FALLTIME (ns) tr Low Side 20 20 50 tf Low Side 40 tf High Side 30 20 40 tf Low Side 30 20 10 10 0 -40 0 10 12 14 16 VCC, VOLTAGE (V) 18 20 Figure 16. Turn OFF Falltime vs. Supply Voltage (VCC = VBOOT) -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 Figure 17. Turn OFF Falltime vs. Temperature 20 600 15 10 550 5 DEAD TIME (ns) PROPAGATION DELAY MATCHING (ns) tr High Side 140 tr Low Side Delay Matching 1 0 -5 -10 500 450 Delay Matching 2 -15 -20 -40 -20 0 20 40 60 80 100 400 -40 120 -20 0 20 40 60 80 100 TEMPERATURE (°C) TEMPERATURE (°C) Figure 18. Propagation Delay Matching Between High Side and Low Side Driver vs. Temperature Figure 19. Dead Time vs. Temperature http://onsemi.com 8 120 NCP5104 1.4 1.6 1.2 1.4 LOW LEVEL INPUT VOLTAGE THRESHOLD (V) LOW LEVEL INPUT VOLTAGE THRESHOLD (V) CHARACTERIZATION CURVES 1.0 0.8 0.6 0.4 0.2 0 10 12 14 16 18 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 20 Figure 20. Low Level Input Voltage Threshold vs. Supply Voltage (VCC = VBOOT) 0 100 120 2.5 HIGH LEVEL INPUT VOLTAGE THRESHOLD (V) HIGH LEVEL INPUT VOLTAGE THRESHOLD (V) 20 40 60 80 TEMPERATURE (°C) Figure 21. Low Level Input Voltage Threshold vs. Temperature 2.5 2.0 1.5 1.0 0.5 0 10 12 14 16 VCC, VOLTAGE (V) 18 2.0 1.5 1.0 0.5 0 -40 20 Figure 22. High Level Input Voltage Threshold vs. Supply Voltage (VCC = VBOOT) -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 Figure 23. High Level Input Voltage Threshold vs. Temperature 10 LOGIC “0” INPUT CURRENT (mA) 4.0 LOGIC “0” INPUT CURRENT (mA) -20 VCC, VOLTAGE (V) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 10 12 14 16 VCC, VOLTAGE (V) 18 8.0 6.0 4.0 2.0 0 -40 -20 20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 25. Logic “0” Input Current vs. Temperature Figure 24. Logic “0” Input Current vs. Supply Voltage (VCC = VBOOT) http://onsemi.com 9 120 NCP5104 CHARACTERIZATION CURVES 10 LOGIC “1” INPUT CURRENT (mA) LOGIC “1” INPUT CURRENT (mA) 8 7 6 5 4 3 2 1 0 10 12 14 16 VCC, VOLTAGE (V) 18 8.0 6.0 4.0 2.0 0 -40 20 20 40 60 80 100 120 Figure 27. Logic “1” Input Current vs. Temperature 1.0 LOW LEVEL OUTPUT VOLTAGE (V) 1.0 LOW LEVEL OUTPUT VOLTAGE THRESHOLD (V) 0 TEMPERATURE (°C) Figure 26. Logic “1” Input Current vs. Supply Voltage (VCC = VBOOT) 0.8 0.6 0.4 0.2 0 10 12 14 16 VCC, VOLTAGE (V) 18 20 0.8 0.6 0.4 0.2 0 -40 Figure 28. Low Level Output Voltage vs. Supply Voltage (VCC = VBOOT) -20 0 20 40 60 80 TEMPERATURE (°C) 100 120 Figure 29. Low Level Output Voltage vs. Temperature 1.0 HIGH LEVEL OUTPUT VOLTAGE (V) 1.6 HIGH LEVEL OUTPUT VOLTAGE THRESHOLD (V) -20 1.2 0.8 0.4 0 10 12 14 16 VCC, VOLTAGE (V) 18 20 0.8 0.6 0.4 0.2 0 -40 -20 0 20 40 60 80 TEMPERATURE (°C) 100 Figure 31. High Level Output Voltage vs. Temperature Figure 30. High Level Output Voltage vs. Supply Voltage (VCC = VBOOT) http://onsemi.com 10 120 NCP5104 CHARACTERIZATION CURVES 400 OUTPUT SOURCE CURRENT (mA) OUTPUT SOURCE CURRENT (mA) 400 Isrc High Side 350 300 Isrc Low Side 250 200 150 100 50 350 300 250 200 12 14 16 VCC, VOLTAGE (V) 18 100 50 0 -40 -20 20 0 40 60 80 100 120 Figure 33. Output Source Current vs. Temperature 600 600 Isink High Side OUTPUT SINK CURRENT (mA) Isink High Side 500 Isink Low Side 400 300 200 100 500 10 12 14 16 18 Isink Low Side 400 300 200 100 0 0 -40 -20 20 0 VCC, VOLTAGE (V) 20 40 60 80 100 120 TEMPERATURE (°C) Figure 34. Output Sink Current vs. Supply Voltage (VCC = VBOOT) Figure 35. Output Sink Current vs. Temperature 0.20 20 LEAKAGE CURRENT ON HIGH VOLTAGE PINS (600 V) to GND (mA) HIGH SIDE LEAKAGE CURRENT ON HV PINS TO GND (mA) 20 TEMPERATURE (°C) Figure 32. Output Source Current vs. Supply Voltage (VCC = VBOOT) OUTPUT SINK CURRENT (mA) Isrc Low Side 150 0 10 Isrc High Side 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 0 100 200 300 400 500 600 15 10 5.0 0 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) HV PINS VOLTAGE (V) Figure 36. Leakage Current on High Voltage Pins (600 V) to Ground vs. VBRIDGE Voltage (VBRIDGE = VBOOT = VDRV_HI) Figure 37. Leakage Current on High Voltage Pins (600 V) to Ground vs. Temperature (VBRIDGE = VBOOT = VDRv_HI = 600 V) http://onsemi.com 11 NCP5104 CHARACTERIZATION CURVES 100 VBOOT CURRENT SUPPLY (mA) VBOOT SUPPLY CURRENT (mA) 100 80 60 40 20 0 0 4.0 8.0 12 16 80 60 40 20 0 -40 20 -20 0 60 80 100 120 Figure 39. VBOOT Supply Current vs. Temperature 400 VCC CURRENT SUPPLY (mA) 240 VCC SUPPLY CURRENT (mA) 40 TEMPERATURE (°C) VBOOT, VOLTAGE (V) Figure 38. VBOOT Supply Current vs. Bootstrap Supply Voltage (VCC = VBOOT) 200 160 120 80 40 0 4.0 8.0 12 16 350 300 250 200 150 100 50 0 -40 0 20 -20 0 VCC, VOLTAGE (V) 40 60 80 100 120 Figure 41. VCC Supply Current vs. Temperature 10 UVLO SHUTDOWN VOLTAGE (V) 9.0 9.8 9.6 9.4 9.2 VCC UVLO Startup 9.0 8.8 VBOOT UVLO Startup 8.6 8.4 8.2 8.0 -40 20 TEMPERATURE (°C) Figure 40. VCC Supply Current vs. VCC Supply Voltage (VCC = VBOOT) UVLO STARTUP VOLTAGE (V) 20 -20 0 20 40 60 80 100 120 8.8 8.6 VCC UVLO Shutdown 8.4 8.2 8.0 VBOOT UVLO Shutdown 7.8 7.6 7.4 7.2 7.0 -40 TEMPERATURE (°C) -20 0 20 40 60 80 100 TEMPERATURE (°C) Figure 42. UVLO Startup Voltage vs. Temperature Figure 43. UVLO Shutdown Voltage vs. Temperature http://onsemi.com 12 120 NCP5104 CHARACTERIZATION CURVES 40 ICC+ IBOOT CURRENT SUPPLY (mA) ICC+ IBOOT CURRENT SUPPLY (mA) 25 CLOAD = 1 nF/Q = 15 nC 20 15 10 5.0 RGATE = 0 R to 22 R 0 RGATE = 10 R 30 25 RGATE = 22 R 20 15 10 5.0 0 0 100 200 300 400 500 0 600 100 SWITCHING FREQUENCY (kHz) Figure 44. ICC1 Consumption vs. Switching Frequency with 15 nC Load on Each Driver @ VCC = 15 V 200 300 400 500 SWITCHING FREQUENCY (kHz) 600 Figure 45. ICC1 Consumption vs. Switching Frequency with 33 nC Load on Each Driver @ VCC = 15 V 80 CLOAD = 3.3 nF/Q = 50 nC ICC+ IBOOT CURRENT SUPPLY (mA) 60 ICC+ IBOOT CURRENT SUPPLY (mA) RGATE = 0 R CLOAD = 2.2 nF/Q = 33 nC 35 RGATE = 0 R 50 RGATE = 10 R 40 RGATE = 22 R 30 20 10 0 CLOAD = 6.6 nF/Q = 100 nC 70 RGATE = 0 R 60 50 RGATE = 10 R 40 RGATE = 22 R 30 20 10 0 0 100 200 300 400 500 600 0 SWITCHING FREQUENCY (kHz) Figure 46. ICC1 Consumption vs. Switching Frequency with 50 nC Load on Each Driver @ VCC = 15 V 100 200 300 400 500 SWITCHING FREQUENCY (kHz) 600 Figure 47. ICC1 Consumption vs. Switching Frequency with 100 nC Load on Each Driver @ VCC = 15 V http://onsemi.com 13 NCP5104 PACKAGE DIMENSIONS SOIC-8 NB CASE 751-07 ISSUE AJ NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. -XA 8 5 S B 0.25 (0.010) M Y M 1 4 K -YG C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE -Z- 0.10 (0.004) H M D 0.25 (0.010) M Z Y S X J S SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. http://onsemi.com 14 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 _ 8 _ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 NCP5104 PACKAGE DIMENSIONS 8 LEAD PDIP CASE 626-05 ISSUE L 8 5 -B1 4 F -A- NOTE 2 L C J -T- DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --10_ 0.030 0.040 N SEATING PLANE D H NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. M K G 0.13 (0.005) M T A M B M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. 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American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 http://onsemi.com 15 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative NCP5104/D