CBTU0808 Dual lane PCI Express port multiplexer Rev. 02 — 6 September 2007 Product data sheet 1. General description The CBTU0808 is a dual lane port multiplexer designed to provide convenient and reliable path switching for PCI Express signals. It is organized as two PCI Express lanes, each consisting of a Transmit and Receive channel. Each channel has four ports, two (A and B) on the source (or host) side and two (A and B) on the destination (or device) side. Each port provides a pair of signal lines to support PCIe differential signaling. Using specially designed high-bandwidth and high off-isolation switch elements, source and destination ports can be connected or isolated in three possible configurations: source A and B to destinations A and B respectively; or source A to destination B (remaining ports isolated), or all ports isolated. The switch elements are controlled by internal control logic to set switch positions in accordance with these three configurations, selectable by CMOS inputs CTRL0 and CTRL1 for lanes 0 and 1 respectively. Within a lane, the switch configuration is always applied identically to both transmit and receive channels. The CBTU0808 is packaged in a 48-ball, depopulated 9 × 9 grid, 0.5 mm ball pitch, thin profile fine-pitch ball grid array (TFBGA) package, which (while requiring a minimum 5 mm × 5 mm of board space) allows for adequate signal routing and escape using conventional board technology. 2. Features n n n n n n n n n n n 2-lane wide PCI Express port multiplexer One transmit and one receive differential channel per lane Four ports per channel PCI Express signaling compliant High bandwidth: > 1 GHz Low OFF-feedthrough of < −35 dB at 1.25 GHz Low channel crosstalk of < −35 dB at 1.25 GHz Designed to match characteristic impedance of PCIe signaling environment Single 1.8 V supply operation ESD resilience of 8 kV HBM Available in 48-ball, 5 mm × 5 mm, 0.5 mm ball pitch TFBGA package, Pb-free/Green 3. Applications n High-performance computing applications n Port switching and docking applications CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer 4. Ordering information Table 1. Ordering information Type number Solder process Package CBTU0808EE/G Pb-free (SnAgCu solder ball compound) Name Description Version TFBGA48 plastic thin fine-pitch ball grid array package; 48 balls; body 5 × 5 × 0.8 mm SOT918-1 5. Functional diagram CBTU0808 CTRL[1:0] TEST[1:0] CONTROL AND CONFIGURATION TXSA0P TXDA0P TXSA0N TXDA0N TXSB0P TXDB0P channel Tx0 TXSB0N TXDB0N LANE 0 RXSA0P RXDA0P RXSA0N RXDA0N channel Rx0 RXSB0P RXDB0P RXSB0N RXDB0N TXSA1P TXDA1P TXSA1N TXDA1N TXSB1P TXDB1P channel Tx1 TXSB1N TXDB1N LANE 1 RXSA1P RXDA1P RXSA1N RXDA1N RXSB1P RXDB1P RXSB1N RXDB1N channel Rx1 002aac139 Fig 1. Functional diagram CBTU0808_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 September 2007 2 of 17 CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer 6. Pinning information 6.1 Pinning ball A1 index area CBTU0808EE/G 1 2 3 4 5 6 7 8 9 A B C D E F G H J 002aac213 Transparent top view Fig 2. Pin configuration for TFBGA48 1 2 A CTRL0 TXSB0P B RXSA0P GND C 3 TXSB0N 4 5 6 TXSA0P GND TXDA0P TXSA0N VDD TXDA0N 7 TXDB0N 8 9 TXDB0P TEST1 GND RXDA0P RXSA0N RXDA0N D RXSB0P RXSB0N RXDB0N RXDB0P E GND VDD VDD GND F TXSA1P TXSA1N TXDA1N TXDA1P TXSB1N TXDB1N G H TXSB1P GND J TEST0 RXSA1P RXSA1N RXSB1N VDD RXDB1N RXSB1P GND RXDB1P RXDA1N GND TXDB1P RXDA1P CTRL1 002aac212 48-ball, 9 × 9 grid; top view. An empty cell indicates no ball is populated at that grid point. Fig 3. Ball mapping CBTU0808_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 September 2007 3 of 17 CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer 6.2 Pin description Table 2. Pin description Signal group Symbol Pin Type Description Test and control CTRL0 A1 CTRL1 J9 CMOS input Switch configuration control inputs. See Table 3 “Switch configuration truth table”. TEST0 J1 CMOS input Test input. Used for test purposes only. Should be left open-circuit during normal operation. An internal pull-down resistor will default this pin to a LOW state. TEST1 A9 output Test output. Used for test purposes only. Should be left open-circuit in normal application. TXSA0P, TXSA0N, TXSB0P, TXSB0N A4, B4, A2, B3 signal port Transmit ports A and B differential signal terminals for Lane 0, Source side. RXSA0P, RXSA0N, B1, C2, RXSB0P, RXSB0N D1, D2 signal port Receive ports A and B differential signal terminals for Lane 0, Source side. TXSA1P, TXSA1N, TXSB1P, TXSB1N F1, F2, H1, G2 signal port Transmit ports A and B differential signal terminals for Lane 1, Source side. RXSA1P, RXSA1N, J2, H3, RXSB1P, RXSB1N J4, H4 signal port Receive ports A and B differential signal terminals for Lane 1, Source side. TXDA0P, TXDA0N, TXDB0P, TXDB0N A6, B6, A8, B7 signal port Transmit ports A and B differential signal terminals for Lane 0, Destination side. RXDA0P, RXDA0N, B9, C8, RXDB0P, RXDB0N D9, D8 signal port Receive ports A and B differential signal terminals for Lane 0, Destination side. TXDA1P, TXDA1N, TXDB1P, TXDB1N F9, F8, H9, G8 signal port Transmit ports A and B differential signal terminals for Lane 1, Destination side. RXDA1P, RXDA1N, J8, H7, RXDB1P, RXDB1N J6, H6 signal port Receive ports A and B differential signal terminals for Lane 1, Destination side. VDD B5, E2, E8, H5 power power supply pins GND A5, B2, B8, E1, E9, H2, H8, J5 power ground pins Signal ports Power CBTU0808_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 September 2007 4 of 17 CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer 7. Functional description 7.1 Functional description 7.1.1 General information The CBTU0808 Dual lane PCI Express port multiplexer is designed to allow port switching of up to two PCI Express lanes (each including a Transmit and Receive channel) according to three switch configuration settings (described in Section 7.1.2.1). The basic switch element of the CBTU0808 is designed integrally with its package and chip interconnect to present an optimum characteristic on-impedance when used in a PCI Express signaling environment, and to provide high off-port isolation and low crosstalk. 7.1.2 Functional information The following paragraphs describe the control and configuration possibilities available in the CBTU0808. 7.1.2.1 Switch configuration The position of the port switches is controlled by CMOS input signals CTRL[1:0] and can be overridden by CMOS input TEST0 to disconnect (open) all ports between source and destination. For a given lane, the switch positions are always identical between transmit and receive channels. Lane 0 is controlled by CTRL0 and Lane 1 is controlled by CTRL1. The truth table for the switch position as a function of these inputs is shown in Table 3. Table 3. Switch configuration truth table Inputs Function CTRLn[1] TEST0 LOW LOW HIGH[2] LOW LOW HIGH > LOW Source ports[1] Destination ports A B An Ron high-Z Bn high-Z Ron An high-Z Ron Bn high-Z high-Z An high-Z high-Z Bn high-Z high-Z HIGH Test mode for internal use only [1] n is the Lane number (0 or 1). [2] CTRL1 or CTRL0 = HIGH. CBTU0808_2 Product data sheet Comment SA:DA/SB:DB (Dual Through mode) SA:DB (Single Cross mode) All ports open-circuit (Disconnect mode) do not use © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 September 2007 5 of 17 CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage Conditions Min Max Unit −0.5 +2.5 V VI input voltage −0.5 +2.5 V IIK input clamping current VI < 0 V or VI > VDD - −50 mA IOK output clamping current VO < 0 V or VO > VDD - ±50 mA IO output current continuous; 0 V < VO < VDD - ±50 mA IDDC continuous current through each VDD or GND pin - ±100 mA Tstg storage temperature −65 +150 °C Vesd electrostatic discharge voltage Human Body Model; 1.5 kΩ; 100 pF >8 - kV Machine Model; 0 Ω; 200 pF >450 - V [1] [1] The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD supply voltage VI input voltage HIGH-level input voltage VIH Conditions Min Typ Max Unit 1.7 - 1.9 V −0.25 - +1.75 V CTRL[1:0], TEST inputs [1] 0.65 × VDD - VDD V [1] - - 0.35 × VDD V 0 - 1.5 V - - 1.2 V 0 - +85 °C TXn and RXn ports VIL LOW-level input voltage CTRL[1:0], TEST[1:0] inputs VICR common mode input voltage range TXn and RXn ports VI(dif)(p-p) peak-to-peak differential input voltage TXn and RXn ports Tamb ambient temperature operating in free air [2] [1] The CTRL[1:0] inputs of the device must be held at valid levels (not floating) to ensure proper device operation. [2] VI(dif)(p-p) = 2 × |VTX_D+ − VTX_D−|. See Paragraph 4.3.3, Table 4-5 of Ref. 1. CBTU0808_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 September 2007 6 of 17 CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer 10. Static characteristics Table 6. Static characteristics Over recommended operating conditions, unless otherwise noted. Symbol Parameter Conditions [1] supply current IDD Min Typ Max Unit - - 1 mA Digital inputs CTRL[1:0] and TEST0 ILI input leakage current VI = VDD or GND - - ±5 µA Ci input capacitance VI = VDD or GND - - 5 pF VI = VDD or GND; TEST0 = HIGH (Disconnect mode) −100 - +100 µA 8 10 12 Ω - 0.5 0.75 Ω - 3.6 4.75 pF Signal ports TXSA0P … RXDB1N ILI input leakage current Ron(sw) switch on-state resistance ∆Ron(sw) switch on-state resistance variation over recommended VID (input voltage) range CS(ON) ON-state capacitance VI = 0.9 V switch; simulated value of the silicon switch only, excluding package parasitics [1] Static operating current. CBTU0808_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 September 2007 7 of 17 CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer 11. Dynamic characteristics Table 7. Dynamic characteristics Over recommended operating conditions, unless otherwise noted. Characterization bandwidth: 10 MHz < foper < 6 GHz. Symbol Parameter Conditions Min Typ Max Unit tPD propagation delay Figure 5 - 60 - ps tstartup start-up time supply voltage valid to switch specified operating characteristics - - 100 µs trcfg reconfiguration time CTRL[1:0], TEST0 setting change to switch specified operating characteristics - - 100 µs tsk(o) output skew time difference in propagation delay between any two ‘ON’ paths within a channel; Figure 6 - - 40 ps tsk(edge) edge skew time difference of rising edge propagation delay to falling edge propagation delay; Figure 7 - - 40 ps tsk(dif) differential skew time difference in propagation delay between two members of a differential pair; Figure 8 - - 5 ps s12 reverse transmission coefficient f = 50 MHz −0.8 - - dB f = 625 MHz −2 - - dB f ≤ 1.25 GHz −3.3 - - dB f = 50 MHz −0.8 - - dB f = 625 MHz −2 - - dB f ≤ 1.25 GHz −3.3 - - dB f = 50 MHz - - −20 dB f = 625 MHz - - −8 dB f ≤ 1.25 GHz - - −6.0 dB f = 50 MHz - - −20 dB f = 625 MHz - - −8 dB f ≤ 1.25 GHz - - −6.0 dB f = 50 MHz - - −35 dB f = 625 MHz - - −35 dB f = 1.25 GHz - - −35 dB f = 50 MHz - - −35 dB f = 625 MHz - - −35 dB f = 1.25 GHz - - −35 dB s21 s11 s22 s12 s21 forward transmission coefficient input reflection coefficient output reflection coefficient reverse transmission coefficient forward transmission coefficient Differential mode ON insertion loss; ON-state Differential mode ON insertion loss; ON-state Differential mode ON return loss; ON-state Differential mode ON return loss; ON-state Differential mode port-to-port crosstalk; ON/OFF-state Differential mode port-to-port crosstalk; ON/OFF-state CBTU0808_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 September 2007 8 of 17 CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer Table 7. Dynamic characteristics …continued Over recommended operating conditions, unless otherwise noted. Characterization bandwidth: 10 MHz < foper < 6 GHz. Symbol Parameter Conditions s12 Differential mode off-port feedthrough; OFF-state s21 reverse transmission coefficient forward transmission coefficient f = 50 MHz Min Typ Max Unit - - −35 dB f = 625 MHz - - −35 dB f = 1.25 GHz - - −35 dB - - −35 dB Differential mode off-port feedthrough; OFF-state f = 50 MHz f = 625 MHz - - −35 dB f = 1.25 GHz - - −35 dB 002aac278 0 s11, s21, s12, s22 (dB) −6 (1) (2) −12 −18 −24 0 1.25 2.50 3.75 5.00 f (GHz) (1) insertion loss (2) return loss Fig 4. S parameters 1.8 V input 0.9 V 0.9 V VOH output 0V tPLH VOL tsk(o) tPHL VOH VOH output Vref Vref output VOL 002aac274 Fig 5. Propagation delay CBTU0808_2 Product data sheet VOL 002aac275 Fig 6. Output skew © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 September 2007 9 of 17 CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer 1.8 V input 0.9 V 1.8 V input 0.9 V 0.9 V 0.9 V 0V tPLH tPHL 0V tsk(dif) tsk(dif) VOH output 0.9 V 0.9 V 1.8 V input 0.9 V 0.9 V VOL 002aac277 0V 002aac276 tsk(edge) = |tsk(edge) rising − tsk(edge) falling| Fig 7. Edge skew Fig 8. Differential skew 12. Test information TXSx, RXSx DUT TXDx, RXDx CL 6 pF 50 Ω 002aac273 CL represents board and jig and does not indicate additional capacitance. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; slew rate = 2.5 V/ns Fig 9. Test circuit CBTU0808_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 September 2007 10 of 17 CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer 13. Package outline TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 5 x 5 x 0.8 mm B D SOT918-1 A ball A1 index area E A2 A A1 detail X e1 ∅v ∅w b e M M C C A B C y1 C y J H G F E e2 e D C B A ball A1 index area 1 2 3 4 5 6 7 8 9 X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D E e e1 e2 v w y y1 mm 1.15 0.25 0.15 0.90 0.75 0.35 0.25 5.1 4.9 5.1 4.9 0.5 4 4 0.15 0.05 0.08 0.1 REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT918-1 --- MO-195 --- EUROPEAN PROJECTION ISSUE DATE 05-09-21 05-10-13 Fig 10. Package outline SOT918-1 (TFBGA48) CBTU0808_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 September 2007 11 of 17 CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer 14. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities CBTU0808_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 September 2007 12 of 17 CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 11) than a PbSn process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 8 and 9 Table 8. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 9. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (°C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 11. CBTU0808_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 September 2007 13 of 17 CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 11. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor PCI Peripheral Component Interconnect PCIe PCI Express DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model PRR Pulse Repetition Rate 16. References [1] PCI Express Base Specification, Rev 1.1 — Revision 1.1, March 2005. CBTU0808_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 September 2007 14 of 17 CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer 17. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes CBTU0808_2 20070906 Product data sheet - CBTU0808_1 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • • Legal texts have been adapted to the new company name where appropriate. Section 2 “Features”, 10th bullet item: changed “2 kV HBM” to “8 kV HBM” Table 4 “Limiting values”: changed symbol “ICCC” to “IDDC” Table 4 “Limiting values”, Vesd, electrostatic discharge voltage: – changed minimum Human Body Model from “>2 kV” to “>8 kV” – changed minimum Machine Model from “>200 V” to “>450 V” CBTU0808_1 20060602 Product data sheet CBTU0808_2 Product data sheet - - © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 September 2007 15 of 17 CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 18.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] CBTU0808_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 6 September 2007 16 of 17 CBTU0808 NXP Semiconductors Dual lane PCI Express port multiplexer 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.1.1 7.1.2 7.1.2.1 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Functional description. . . . . . . . . . . . . . . . . . . . 5 General information . . . . . . . . . . . . . . . . . . . . . 5 Functional information . . . . . . . . . . . . . . . . . . . 5 Switch configuration . . . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Test information . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Introduction to soldering . . . . . . . . . . . . . . . . . 12 Wave and reflow soldering . . . . . . . . . . . . . . . 12 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 12 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 14 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 6 September 2007 Document identifier: CBTU0808_2