ISL90462 ® Single Volatile 32-tap XDCP Data Sheet October 7, 2005 Digitally Controlled Potentiometer (XDCP™) FN8230.3 Features • Volatile Solid-State Potentiometer The Intersil ISL90462 is a digitally controlled potentiometer (XDCP). Configured as a variable resistor, the device consists of a resistor array, wiper switches, a control section, and volatile memory. The wiper position is controlled by a 2pin Up /Down interface. The potentiometer is implemented by a resistor array composed of 31 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS and U/D inputs. The device can be used in a wide variety of applications including: • 2-pin UP/DN Interface • DCP Terminal Voltage, 2.7V to 5.5V • Tempco 35ppm/°C Typical • 32 Wiper Tap Points • Low Power CMOS - Active current, 25µA max. - Supply current 0.3µA • Available RTOTAL Values = 10kΩ, 50kΩ, 100kΩ • Temperature Range -40°C to +85°C • LCD contrast control • Packages - 6 Ld SC-70, SOT-23 • Parameter and bias adjustments • Pb-Free Plus Anneal Available (RoHS Compliant) • Industrial and Automotive Control Pinout • Transducer adjustment of pressure, temperature, position, chemical, and optical sensors ISL90462 (SOT23, SC70) TOP VIEW • Laser Diode driver biasing • Gain control and offset adjustment VDD RH GND RW U/D CS Ordering Information PART NUMBER PART MARKING ISL90462WIE627-TK AJS RTOTAL (K) TEMP RANGE (°C) 10 -40 to +85 6 Ld SC-70 P6.049 -40 to +85 6 Ld SC-70 (Pb-free) P6.049 ISL90462WIE627Z-TK (See Note) DEK ISL90462WIH627-TK PACKAGE (Tape and Reel) PKG. DWG. # AKB -40 to +85 6 Ld SOT-23 P6.064 ISL90462WIH627Z-TK (See Note) DEL -40 to +85 6 Ld SOT-23 (Pb-free) P6.064 -40 to +85 6 Ld SC-70 P6.049 ISL90462UIE627-TK AJU 50 ISL90462UIE627Z-TK (See Note) DEI -40 to +85 6 Ld SC-70 (Pb-free) P6.049 ISL90462UIH627-TK AKD -40 to +85 6 Ld SOT-23 P6.064 ISL90462UIH627Z-TK (See Note) DEJ ISL90462TIE627-TK AJT ISL90462TIE627Z-TK (See Note) DEG 100 -40 to +85 6 Ld SOT-23 (Pb-free) P6.064 -40 to +85 6 Ld SC-70 P6.049 -40 to +85 6 Ld SC-70 (Pb-free) P6.049 ISL90462TIH627-TK AKC -40 to +85 6 Ld SOT-23 P6.064 ISL90462TIH627Z-TK See Note) DEH -40 to +85 6 Ld SOT-23 (Pb-free) P6.064 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL90462 Block Diagram Pin Descriptions VCC RH UP/DOWN (U/D) CONTROL AND MEMORY DEVICE SELECT RW 6-PIN SYMBOL DESCRIPTION 1 VDD Supply voltage 2 GND Ground/Low terminal 3 U/D Up - Down 4 CS Chip select 5 RW Wiper terminal 6 RH High terminal (CS) GND (GROUND) GENERAL 2 FN8230.3 October 7, 2005 ISL90462 Absolute Maximum Ratings Recommended Operating Conditions Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage on CS, U/D and VCC With Respect to GND. . . . -1V to +7V Lead Temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . . . 300°C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1mW Temperature Range (Industrial) . . . . . . . . . . . . . . . . . . -40°C to 85°C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Potentiometer Specifications SYMBOL Over recommended operating conditions unless otherwise stated. PARAMETER RTOT End to end resistance VR MIN TYP (Note 4) MAX UNIT W version 8 10 12 kΩ U version 40 50 60 kΩ T version 80 100 120 kΩ VCC V TEST CONDITIONS RH, RL terminal voltages Noise 0 Ref: 1kHz RW Wiper Resistance IW Wiper Current Resolution dBV 600 Ω 1 Absolute linearity (Note 1) RH(n)(actual) - RH(n)(expected) Relative linearity (Note 2) RH(n+1) - [RH(n) + MI] RTOTAL temperature coefficient CH/CL/CW -120 Potentiometer capacitances See Equivalent Circuit 0.6 mA 32 Taps ±1 MI (Note 3) ±0.5 MI (Note 3) ±35 ppm/°C 10/10/25 pF NOTES: 1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (RH(n)(actual)-RH(n)(expected)) = ±1 Ml Maximum. n = 1 .. 29 only 2. Relative linearity is a measure of the error in step size between taps = RH(n+1)-[RH(n) + Ml] = ±0.5 Ml, n = 1 .. 29 only. 3. 1 Ml = Minimum Increment = RTOT/31. 4. Typical values are for TA = 25°C and nominal supply voltage. Equivalent Circuit RTOTAL RL RH CW CH CL RW 3 FN8230.3 October 7, 2005 ISL90462 DC Electrical Specifications SYMBOL Over recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS ICC VCC active current (Increment) CS = 0V, U/D = fclock = 1MHz and VCC = 3V ISB Standby supply current CS = VCC, U/D = GND or VCC = 3V ILI CS input leakage current VIN = GND to VCC VIH CS, U/D input HIGH voltage VIL CS, U/D input LOW voltage CIN CS, U/D input capacitance Timing Specifications TYP (NOTE 4) MIN 0.3 MAX UNIT 25 µA 1 µA ±1 µA VCC x 0.7 V VCC x 0.3 VCC = 3V, VIN = GND, TA = 25°C, f = 1MHz V 10 pF Over recommended operating conditions unless otherwise specified SYMBOL PARAMETER MIN TYP (Note 4) MAX UNIT tCU U/D to CS setup 25 ns tCI CS to U/D setup 50 ns tIC CS to U/D hold 25 ns tlL U/D LOW period 300 ns tlH U/D HIGH period 300 ns fTOGGLE Up/Down toggle Rate 1 MHz tSETTLE Output settling time 1 µs CS tCU tIC tIL U/D tCI tIH tSETTLE RW FIGURE 1. SERIAL INTERFACE TIMING DIAGRAM, INCREMENT 4 FN8230.3 October 7, 2005 ISL90462 CS tCU tIC tIH U/D tCI tIL tSETTLE RW FIGURE 2. SERIAL INTERFACE TIMING DIAGRAM DECREMENT Pin Descriptions Principles of Operation RH and RW The ISL90462 contains a digital potentiometer with one terminal tied to the ground pin (GND) of the device. The RH pin is the other potentiometer terminal, and the RW pin is the wiper terminal. The position of the wiper is controlled by the CS- and U/D- inputs, with a movement "up" connecting the wiper closer to the RH pin, and movement "down" connection the wiper closer to the GND pin. Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incremented or decremented. Chip Select (CS) The device is selected when the CS input is LOW. The current counter value is stored in volatile memory when CS is returned HIGH. When CS is high, the device is placed in low power standby mode. There are two sections of the ISL90462: the input control, counter and decode section; and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. The resistor array is comprised of 31 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the connection at that point to the wiper. The RH and RW terminals are uncommitted, and can for a variable voltage divider if RH is connected to a voltage source. The direction of the wiper movement is defined when the device is selected. If during CS transition from High to Low the U/D input is LOW, the wiper will move down on each rising edge of U/D toggling. Similarly, the wiper will move up on each rising edge of U/D toggling if, during CS transition from High to Low, the U/D input is High. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. If the wiper is moved several positions, multiple taps are connected to the wiper for tSETTLE (U/D to RW change). The 2-terminal resistance value for the device can temporarily change by a significant amount if the wiper is moved several positions. 5 FN8230.3 October 7, 2005 ISL90462 Small Outline Transistor Plastic Packages (SOT23-6) 0.20 (0.008) M P6.064 VIEW C C 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE CL INCHES e b SYMBOL 6 5 4 CL CL E1 E 1 2 3 e1 C D CL A A2 SEATING PLANE A1 -C- WITH b PLATING b1 c c1 MILLIMETERS MAX MIN MAX NOTES A 0.036 0.057 0.90 1.45 - A1 0.000 0.0059 0.00 0.15 - A2 0.036 0.051 0.90 1.30 - b 0.012 0.020 0.30 0.50 - b1 0.012 0.018 0.30 0.45 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.008 0.08 0.20 6 D 0.111 0.118 2.80 3.00 3 E 0.103 0.118 2.60 E1 0.060 0.068 1.50 3.00 - 1.75 3 e 0.0374 Ref 0.95 Ref - e1 0.0748 Ref 1.90 Ref - L 0.10 (0.004) C MIN 0.014 0.022 0.35 0.55 L1 0.024 Ref. 0.60 Ref. L2 0.010 Ref. 0.25 Ref. N 6 6 4 5 R 0.004 - 0.10 - R1 0.004 0.010 0.10 0.25 α 0o 8o 0o 8o Rev. 3 9/03 BASE METAL NOTES: 1. Dimensioning and tolerance per ASME Y14.5M-1994. 4X θ1 2. Package conforms to EIAJ SC-74 and JEDEC MO178AB. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. R 5. “N” is the number of terminal positions. GAUGE PLANE SEATING PLANE L C L1 α L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only 4X θ1 VIEW C 6 FN8230.3 October 7, 2005 ISL90462 Small Outline Transistor Plastic Packages (SC70-6) 0.20 (0.008) M P6.049 VIEW C C 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE CL INCHES e b SYMBOL 6 5 4 CL CL E1 E 1 2 3 e1 C D CL A A2 SEATING PLANE A1 -C- WITH b PLATING b1 c c1 MILLIMETERS MAX MIN MAX NOTES A 0.031 0.043 0.80 1.10 - A1 0.000 0.004 0.00 0.10 - A2 0.031 0.039 0.00 1.00 - b 0.006 0.012 0.15 0.30 - b1 0.006 0.010 0.15 0.25 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.009 0.08 0.20 6 D 0.073 0.085 1.85 2.15 3 E 0.071 0.094 1.80 2.40 - E1 0.045 0.053 1.15 1.35 3 e 0.0256 Ref 0.65 Ref - e1 0.0512 Ref 1.30 Ref - L 0.10 (0.004) C MIN 0.010 0.018 0.26 0.46 L1 0.017 Ref. 0.420 Ref. L2 0.006 BSC 0.15 BSC N 6 6 4 5 R 0.004 - 0.10 - R1 0.004 0.010 0.15 0.25 α 0o 8o 0o 8o Rev. 2 9/03 NOTES: BASE METAL 1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC70 and JEDEC MO203AB. 4X θ1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. 5. “N” is the number of terminal positions. R GAUGE PLANE SEATING PLANE L C L1 α L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only 4X θ1 VIEW C All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 7 FN8230.3 October 7, 2005