EMLSI EM720FV8CW-12L 64k x16 bit super low power and low voltage full cmos static ram Datasheet

merging Memory & Logic Solutions Inc.
EM611FV16U Series
Low Power, 64Kx16 SRAM
Document Title
64K x16 bit Super Low Power and Low Voltage Full CMOS Static RAM
Revision History
Revision No.
History
Draft Date
0.0
Initial Draft
May 9 , 2003
0.1
2’nd Draft
Add Pb-free part number
Remark
February 13 , 2004
Emerging Memory & Logic Solutions Inc.
IT Venture Tower Eastside 11F, 78, Karac-Dong, Songpa-Ku, Seoul, Rep.of Korea Zip Code : 138-160
Tel : +82-2-2142-1759~1766 Fax : +82-2-2142-1769 / Homepage : www.emlsi.com
The attached datasheets are provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your
questions about device. If you have any questions, please contact the EMLSI office.
1
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
FEATURES
GENERAL DESCRIPTION
•
•
•
•
•
•
The EM611FV16U families are fabricated by EMLSI’s
advanced full CMOS process technology. The families
support industrial temperature range and Chip Scale
Package for user flexibility of system design. The families also supports low data retention voltage for battery
back-up operation with low data retention current.
Process Technology : 0.18µm Full CMOS
Organization : 64K x 16 bit
Power Supply Voltage : 2.7V ~ 3.6V
Low Data Retention Voltage : 1.5V(Min.)
Three state output and TTL Compatible
Package Type : 44-TSOP2
PRODUCT FAMILY
Power Dissipation
Product
Family
Operating
Temperature
Vcc Range
Speed
Standby
(I SB1 , Typ.)
EM611FV16U
Industrial (-40 ~ 85oC)
2.7V~3.6V
551) /70ns
0.5 µA2 )
PKG Type
Operating
(I CC1.Max.)
3 mA
44 TSOP2
1. The parameter is measured with 30pF test load.
2. Typical values are measured at Vcc=3.3V, T A =25 oC and not 100% tested.
FUNCTIONAL BLOCK DIAGRAM
Pre-charge Circuit
A4
1
44
A5
A3
2
43
A6
A2
3
42
A7
A1
4
41
OE
A0
CS
I/O1
5
6
40
39
7
38
UB
LB
I/O16
I/O2
I/O3
8
9
A0
A1
A2
37
36
I/O15
I/O14
I/O4
VCC
VSS
10
11
35
34
33
I/O13
VSS
VCC
A3
A4
A5
A6
A7
32
31
I/O12
I/O11
A8
A9
I/O5
I/O6
I/O7
12
44 - TSOP2
13
14
15
30
I/O10
16
17
29
28
I/O9
NC
18
27
A8
A14
19
26
A9
A13
20
25
A10
A12
NC
21
22
24
23
A11
NC
I/O8
WE
A15
VCC
Row S elect
PIN DESCRIPTION
I/O1 ~ I/O8
1024 x 1024
Data
Cont
Data
Cont
I/O9 ~ I/O16
VSS
Memory Array
I/O Circuit
Column Select
A10 A11
WE
OE
UB
Name
Function
Name
CS
Chip select input
Vcc
Power Supply
OE
Output Enable input
Vss
Ground
WE
Write Enable input
UB
Upper Byte (I/O 9~16)
Address Inputs
LB
Lower Byte (I/O 1~8 )
NC
No Connection
A 0 ~A15
I/O1 ~I/O16 Data Inputs/outputs
LB
CS
Function
2
Control Logic
A12
A13
A14 A15
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
ABSOLUTE MAXIMUM RATINGS *
Parameter
Symbol
Voltage on Any Pin Relative to Vss
Ratings
Unit
VIN , VOUT
-0.2 to Vcc+0.3(Max. 4.0V)
V
VCC
-0.2 to 4.0V
V
Power Dissipation
PD
1.0
W
Operating Temperature
TA
-40 to 85
oC
Voltage on Vcc supply relative to Vss
* Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
FUNCTIONAL DESCRIPTION
CS
OE
WE
LB
UB
I/O 1-8
I/O9-16
Mode
Power
H
X
X
X
X
High-Z
High-Z
Deselected
Stand by
L
H
H
X
X
High-Z
High-Z
Output Disabled
Active
L
X
X
H
H
High-Z
High-Z
Output Disabled
Active
L
L
H
L
H
Data Out
High-Z
Lower Byte Read
Active
L
L
H
H
L
High-Z
Data Out
Upper Byte Read
Active
L
L
H
L
L
Data Out
Data Out
Word Read
Active
L
X
L
L
H
Data In
High-Z
Lower Byte Write
Active
L
X
L
H
L
High-Z
Data In
Upper Byte Write
Active
L
X
L
L
L
Data In
Data In
Word Write
Active
Note: X means don’t care. (Must be low or high state)
3
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
RECOMMENDED DC OPERATING CONDITIONS 1)
Parameter
1.
2.
3.
4.
Symbol
Min
Typ
Max
Unit
Supply voltage
VCC
2.7
3.3
3.6
V
Ground
VSS
0
0
0
V
Input high voltage
VIH
2.2
-
VCC + 0.22)
V
Input low voltage
VIL
-0.2 3)
-
0.6
V
TA= -40 to 85oC, otherwise specified
Overshoot: V CC +2.0 V in case of pulse width < 20ns
Undershoot: -2.0 V in case of pulse width < 20ns
Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE 1) (f =1MHz, TA=25oC)
Item
Symbol
Test Condition
Min
Max
Unit
Input capacitance
C IN
VIN=0V
-
8
pF
Input/Ouput capacitance
CIO
VIO =0V
-
10
pF
1. Capacitance is sampled, not 100% tested
DC AND OPERATING CHARACTERISTICS
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Input leakage current
ILI
VIN =VS S to VCC
-1
-
1
µA
Output leakage current
I LO
CS=VIH or OE=VIH or WE=VIL, VIO=VSS to V CC
-1
-
1
µA
Operating power supply
ICC
IIO=0mA, CS=VIL, VIN =VIH or VIL
-
-
3
mA
I CC1
Cycle time=1µs, 100% duty, I IO=0mA,
CS<0.2V, VIN <0.2V or VIN>VCC -0.2V
-
-
3
mA
I CC2
Cycle time = Min, I IO=0mA, 100% duty,
CS=VIL , VIN=VIL or V IH
55ns
-
-
26
70ns
-
-
20
Output low voltage
VOL
IOL = 2.1mA
-
-
0.4
V
Output high voltage
VOH
IOH = -1.0mA
2.4
-
-
V
Standby Current (TTL)
I SB
CS=VIH , Other inputs=VIH or VIL
-
-
0.3
mA
Standby Current (CMOS)
ISB1
(Typ. condition : VCC =3.3V @ 25o C)
-
0.51 )
5
µA
Average operating current
mA
CS>VCC -0.2V Other inputs=0~VCC
o
(Max. condition : VCC =3.6V @ 85 C)
NOTES
1. Typical values are measured at Vcc=3.3V, T A= 25o C and not 100% tested.
4
LL
LF
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
VTM 3)
AC OPERATING CONDITIONS
Test Conditions (Test Load and Test Input/Output Reference)
R12)
Input Pulse Level : 0.4 to 2.2V
Input Rise and Fall Time : 5ns
Input and Output reference Voltage : 1.5V
Output Load (See right) : CL = 100pF+ 1 TTL
R22)
CL1)
CL 1) = 30pF + 1 TTL
1. Including scope and Jig capacitance
2. R1 =3070Ω,
R 2 =3150Ω
3. VTM=2.8V
READ CYCLE (V cc =2.7 to 3.6V, Gnd = 0V, T A = -40oC to +85oC)
Parameter
55ns
Symbol
70ns
Min
Max
Min
Max
Unit
Read cycle time
tRC
55
-
70
-
ns
Address access time
tAA
-
55
-
70
ns
Chip select to output
tco
-
55
-
70
ns
Output enable to valid output
tO E
-
25
-
35
ns
UB, LB acess time
tBA
35
ns
Chip select to low-Z output
tLZ
10
-
10
-
ns
UB, LB enable to low-Z output
tBLZ
5
-
5
-
ns
Output enable to low-Z output
tOLZ
5
-
5
-
ns
Chip disable to high-Z output
tHZ
0
20
0
25
ns
UB, LB disable to high-Z output
tBHZ
0
20
0
25
ns
Output disable to high-Z output
tOHZ
0
20
0
25
ns
Output hold from address change
tOH
10
-
10
-
ns
30
WRITE CYCLE (Vcc =2.7 to 3.6V, Gnd = 0V, TA = -40oC to +85oC)
Parameter
55ns
Symbol
70ns
Unit
Min
Max
Min
Max
Write cycle time
tWC
55
-
70
-
ns
Chip select to end of write
tCW
45
-
60
-
ns
Address setup time
tAs
0
-
0
-
ns
Address valid to end of write
tAW
45
-
60
-
ns
UB, LB valid to end of write
tBW
45
-
60
-
ns
Write pulse width
tWP
40
-
50
-
ns
Write recovery time
tWR
0
-
0
-
ns
Write to ouput high-Z
tWHZ
0
25
0
30
ns
Data to write time overlap
tDW
25
Data hold from write time
tDH
0
-
0
-
ns
End write to output low-Z
tOW
5
-
5
-
ns
5
30
ns
merging Memory & Logic Solutions Inc.
EM611FV16U Series
Low Power, 64Kx16 SRAM
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1).
(Address Controlled, CS=OE=V IL, WE=V IH, UB or/and LB= VIL)
tRC
Address
tAA
tOH
Data Out
Previous Data Valid
Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)
tRC
Address
tAA
tOH
tCO
CS
tHZ
tB A
UB ,LB
tBHZ
tO E
OE
tOHZ
tOLZ
Data Out
High-Z
Data Valid
tBLZ
tLZ
NOTES (READ CYCLE)
1. t HZ and tOHZ are defined as the outputs achieve the open circuit conditions and are not referanced to output voltage levels.
2. At any given temperature and voltage condition, t HZ(Max.) is less than t LZ(Min.) both for a given device and from device to device
interconnection.
6
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE CONTROLLED)
tWC
Address
tCW (2)
tWR (4)
CS
tAW
tBW
UB ,LB
tWP (1)
WE
tAS(3)
Data in
tDH
tDW
High-Z
High-Z
Data Valid
tWHZ
Data out
tOW
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS CONTROLLED)
tWC
Address
tAS(3)
tCW (2)
tWR (4)
CS
tAW
tBW
UB,LB
tWP (1)
WE
tDW
Data in
Data out
Data Valid
High-Z
High-Z
7
tDH
merging Memory & Logic Solutions Inc.
EM611FV16U Series
Low Power, 64Kx16 SRAM
TIMING WAVEFORM OF WRITE CYCLE(3) (UB, LB CONTROLLED)
tWC
Address
tCW(2)
tW R(4)
CS
tA W
tB W
UB ,LB
tW P(1)
tA S(3)
WE
tDW
Data in
Data out
tDH
Data Valid
High-Z
High-Z
NOTES (WRITE CYCLE)
1. A write occurs during the overlap(tWP ) of low CS and low WE. A write begins when CS goes low and WE
goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double
byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is
measured from the beginning of write to the end of write.
2. t CW is measured from the CS going low to end of write.
3. t A S is measured from the address valid to the beginning of write.
4. t WR is measured from the end or write to the address change. tWR applied in case a write ends as CS
or WE going high.
8
EM611FV16U Series
merging Memory & Logic Solutions Inc.
Low Power, 64Kx16 SRAM
DATA RETENTION CHARACTERISTICS
Parameter
Symbol
VCC for Data Retention
VDR
Data Retention Current
I DR
Chip Deselect to Data Retention Time
Operation Recovery Time
tSDR
Test Condition
ISB1 Test Condition
(Chip Disabled)
1)
VCC =1.5V, ISB1 Test Condition
(Chip Disabled) 1)
Min
Typ2)
Max
Unit
1.5
-
3.6
V
-
0.25
-
µA
0
-
-
t RC
-
-
See data retention wave form
tRDR
ns
NOTES
1. See the IS B 1 measurement condition of datasheet page 4.
2.Typical values are measured at TA= 25o C and not 100% tested.
DATA RETENTION WAVE FORM
tSDR
Data Retention Mode
Vcc
2.7V
2.2V
VDR
CS > Vcc-0.2V
CS
GND
9
tRDR
merging Memory & Logic Solutions Inc.
EM611FV16U Series
Low Power, 64Kx16 SRAM
Unit: millimeters
PACKAGE DIMENSION
10
merging Memory & Logic Solutions Inc.
EM611FV16U Series
Low Power, 64Kx16 SRAM
MEMORY FUNCTION GUIDE
EM X XX X X X XX X X - XX XX
1. EMLSI Memory
11. Power
2. Device Type
10. Speed
3. Density
4. Option
9. Packages
5. Technology
8. Version
6. Operating Voltage
7. Orgainzation
1. Memory Component
8. Version
Blank ----------------- Mother Die
A ----------------------- First revision
B ----------------------- Second revision
C ----------------------- Third revision
D ----------------------- Fourth revision
E ----------------------- Fifth revision
F ----------------------- Sixth revision
2. Device Type
6 ------------------------ Low Power SRAM
7 ------------------------ STRAM
3. Density
1 ------------------------- 1M
2 ------------------------- 2M
4 ------------------------- 4M
8 ------------------------- 8M
16 ----------------------- 16M
32 ----------------------- 32M
64 ----------------------- 64M
9. Package
Blank ---------------------- FPBGA
S ---------------------------- 32 sTSOP1
T ---------------------------- 32 TSOP1
U ---------------------------- 44 TSOP2
W ---------------------------- Wafer
4. Option
0 ----------------------- Dual CS
1 ----------------------- Single CS
10. Speed
45 ---------------------- 45ns
55 ---------------------- 55ns
70 ---------------------- 70ns
85 ---------------------- 85ns
10 --------------------- 100ns
12 --------------------- 120ns
5. Technology
Blank ------------------ CMOS
F ------------------------ Full CMOS
6. Operating Voltage
Blank ------------------ 5.0V
V ------------------------- 2.7V~3.6V
U ------------------------- 3.0V
S ------------------------- 2.5V
R ------------------------- 2.0V
P ------------------------- 1.8V
11. Power
LL ---------------------- Low Low Power
LF ---------------------- Low Low Power(Pb-Free)
L ---------------------- Low Power
S ---------------------- Standard Power
7. Orginzation
8 ---------------------- x8 bit
16 ---------------------- x16 bit
32 ---------------------- x32 bit
11
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