TI1 DLPA1000YFFT Power management and led driver ic Datasheet

Product
Folder
Order
Now
Support &
Community
Tools &
Software
Technical
Documents
DLPA1000
SLVSDP7 – FEBRUARY 2017
DLPA1000 Power Management and LED Driver IC
1 Features
•
1
•
•
•
•
•
•
•
•
High-Efficiency RGB LED Driver With Buck-Boost
DC-to-DC Converter and Integrated MOSFETS
Six Low-Impedance (<100 mΩ) MOSFET
Switches for Channel Selection
Independent, 10-Bit Current Control per Channel
DMD Regulators
– Requires Only a Single Inductor
– VOFS: 8.5 V
– VBIAS: 16 V
– VRST: –10 V
Reset Generation and Power Supply Sequencing
RGB LED Strobe Decoder Supports:
– Common-Anode RGBs
– Cathode-Cathode-Anode RGBs
33-MHz Serial Peripheral Interface (SPI)
Multiplexer for Measuring Analog Signals
– Battery Voltage
– LED Voltage, LED Current
– Light Sensor (for White Point Correction)
– External Temperature Sensor
Monitoring and Protection Circuits
– Hot Die Warning and Thermal Shutdown
– Low-Battery and Undervoltage Lockout
– Overcurrent and Undervoltage Protection
49-Ball 0.4-mm Pitch, DSBGA Package
•
2 Applications
DLP® Pico™ Projector
•
3 Description
DLPA1000 is a dedicated PMIC / RGB LED driver for
the DLP2000 Digital Micromirror Devices (DMD)
when used with a DLPC2607 digital controller. For
reliable operation of these chipsets, it is mandatory to
use the DLPA1000.
Device Information(1)
PART NUMBER
DLPA1000
PACKAGE
DSBGA (49)
BODY SIZE (NOM)
2.40 mm × 2.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
PROJ_ON
Main System
Processor
(MPU)
DLPC2607
Pico Processor
RESETZ
VBIAS
INTZ
VOFS
SPI (4)
VRST
LED_SEL0
LED_SEL1
VLED
PWM_IN
DLPA1000
CMP_OUT
SW4
SW5
SW6
DPP
Power Supplies
DLP2000
DMD
PWR_EN
RGB LED
Assembly
VINA
Light
Sensor
SENS2
SENS1
Single Cell Li-Ion
Temp.
Sensor
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
7
7.4 Device Functional Modes........................................ 19
7.5 Programming........................................................... 20
7.6 Register Maps ......................................................... 21
1
1
1
2
3
5
8
Application and Implementation ........................ 35
8.1 Application Information............................................ 35
8.2 Typical Application .................................................. 35
9 Power Supply Recommendations...................... 39
10 Layout................................................................... 40
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Timing Requirements ................................................ 9
Typical Characteristics ............................................ 10
10.1 Layout Guidelines ................................................. 40
10.2 Layout Example .................................................... 41
11 Device and Documentation Support ................. 42
11.1
11.2
11.3
11.4
11.5
Detailed Description ............................................ 11
7.1 Overview ................................................................ 11
7.2 Functional Block Diagram ....................................... 11
7.3 Feature Description................................................. 12
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
42
42
42
42
42
12 Mechanical, Packaging, and Orderable
Information ........................................................... 43
4 Revision History
2
DATE
REVISION
NOTES
February 2017
*
Initial release.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
5 Pin Configuration and Functions
YFF
49-PIN DSBGA
Bottom View
1
2
3
4
5
6
7
G
SW1
SW2
SW3
VINA
SW4
SW5
SW6
F
V6V
VLED
LED_SEL0
TEST
RLIM_K
RLIM
RLIM
E
VLED
VLED
LED_SEL1
SENS1
SENS2
PROJ_ON
V2V5
D
L2
L2
PWR_EN
CMP_OUT
PWM_IN
DGND
AGND
C
PGNDL
PGNDL
SPI_CLK
SPI_CSZ
SPI_DIN
SPI_DOUT
VOFS
B
L1
L1
RESETZ
INTZ
VSPI
REF_VRST
VBIAS
A
VINL
VINL
AGND1
VINR
SWN
PGNDR
SWP
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
VINL
A1
POWER
Power supply input for VLED BUCK-BOOST power stage. Connect to system power.
VINL
A2
POWER
Power supply input for VLED BUCK-BOOST power stage. Connect to system power.
AGND1
A3
GND
VINR
A4
POWER
SWN
A5
IN (A)
Connection for the DMD SMPS-inductor (high-side switch).
PGNDR
A6
GND
Power ground for DMD SMPS. Connect to ground plane.
SWP
A7
IN(A)
Connection for the DMD SMPS-inductor (low-side switch).
L1
B1
IN (A)
Connection for VLED BUCK-BOOST inductor.
L1
B2
IN(A)
Connection for VLED BUCK-BOOST inductor.
RESETZ
B3
OUT(D)
Reset output to the DLP system (active low). Pin is held low to reset DLP system.
INTZ
B4
OUT(D)
Interrupt output signal (open drain). Connect to pull-up resistor or short to ground.
VSPI
B5
POWER
Power Supply input for SPI interface. Connect to system I/O voltage.
REF_VRST
B6
IN(A)
Analog ground. Connect to ground plane.
Power supply input for DMD switch mode power supply. Connect to system power.
Reference pin for the VRST regulator. Connect to VRST rail through 100-kΩ resistor.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
3
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
VBIAS
B7
OUT(A)
PGNDL
C1
GND
Power ground for VLED BUCK-BOOST. Connect to ground plane.
PGNDL
C2
GND
Power ground for VLED BUCK-BOOST. Connect to ground plane.
SPI_CLK
C3
IN(D)
Clock input for SPI interface.
SPI_CSZ
C4
IN(D)
SPI chip select (active low).
SPI_DIN
C5
IN(D)
SPI data input.
SPI_DOUT
C6
OUT(D)
SPI data output.
VOFS
C7
OUT(A)
VOFS output rail. Connect to ceramic capacitor.
L2
D1
IN(A)
Connection for VLED BUCK-BOOST inductor.
L2
D2
IN(A)
Connection for VLED BUCK-BOOST inductor.
PWR_EN
D3
OUT(D)
Enable pin for the external power supplies (active high).
CMP_OUT
D4
OUT(A)
Analog-comparator output.
PWM_IN
D5
IN(D)
Reference voltage input for analog comparator.
DGND
D6
GND
Digital ground. Connect to ground plane.
AGND
D7
GND
Analog ground. Connect to ground plane.
VLED
E1
OUT (A)
VLED BUCK-BOOST converter output pin.
VLED
E2
OUT(A)
VLED BUCK-BOOST converter output pin.
LED_SEL1
E3
IN(D)
Digital input to the RGB STROBE DECODER.
SENS1
E4
IN(A)
Input signal from light sensor.
SENS2
E5
IN(A)
Input signal from temperature sensor.
PROJ_ON
E6
IN(D)
Input signal to enable/disable the IC and DLP projector.
V2V5
E7
OUT (D)
Internal supply filter pin for digital logic. Typical 2.45 V.
V6V
F1
OUT(D)
Internal supply filter pin for gate driver circuitry. Typical 6 V.
VLED
F2
OUT(A)
VLED BUCK-BOOST converter output pin.
LED_SEL0
F3
IN(D)
Digital input to the RGB STROBE DECODER.
TEST
F4
IN(D)
Test pin for digital, must be tied to the output capacitor of V2V5.
RLIM_K
F5
IN(A)
Kelvin sense connection for LED current sense resistor. For best accuracy, route signal with a
dedicated trace separated from F6/F7 and connect directly at sense resistor.
RLIM
F6
OUT(A)
Connection to LED current sense resistor. Connect to a 100-mΩ resistor.
RLIM
F7
OUT(A)
Connection to LED current sense resistor. Connect to pin F6.
SW1
G1
OUT(A)
High-side MOSFET switch for LED anode. Connect to RGB LED assembly.
If output is not used, short to VLED.
SW2
G2
OUT(A)
High-side MOSFET switch for LED anode. Connect to RGB LED assembly.
If output is not used, short to VLED.
SW3
G3
OUT(A)
High-side MOSFET switch for LED anode. Connect to RGB LED assembly.
If output is not used, short to VLED.
VINA
G4
POWER
Power supply input for sensitive analog circuitry.
SW4
G5
OUT(A)
Low-side MOSFET switch for LED cathode. Connect to RGB LED assembly.
SW5
G6
OUT(A)
Low-side MOSFET switch for LED cathode. Connect to RGB LED assembly.
SW6
G7
OUT(A)
Low-side MOSFET switch for LED cathode. Connect to RGB LED assembly.
4
VBIAS output rail. Connect to ceramic capacitor.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
Input voltage
VINL, VINA, VINR
Ground pins to system ground
Voltage
MIN
MAX
UNIT
–0.3
7
V
V
–0.3
0.3
SWN
–18
7
SWP, VBIAS
–0.3
20
VOFS
–0.3
10
V6V, VLED, L1, L2, SW1, SW2, SW3, SW4, SW5, SW6,
INTZ, PROJ_ON
–0.3
7
All pins unless noted otherwise
–0.3
RESETZ, PWR_EN, CMP_OUT
Source current
3.6
V
1
SPI_DOUT
mA
5.5
RESETZ, PWR_EN, CMP_OUT
Sink current
V
1
SPI_DOUT, INTZ
mA
5.5
Peak output current
Internally limited
mA
Continuous total power dissipation
Internally limited
W
TA
Operating ambient temperature
–30
85
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Input voltage at VINL, VINA, VINR
MIN
NOM
MAX
Full functional and parametric performance
2.7
3.6
6
Extended operation, limited parametric
performance
2.3
3.6
6
1.8
UNIT
V
Voltage at VSPI
1.7
3.6
V
TA
Operating ambient temperature
–10
85
°C
TJ
Operating junction temperature
–10
125
°C
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
5
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
6.4 Thermal Information
DLPA1000
THERMAL METRIC (1)
YFF (DSBGA)
UNIT
49 PINS
RθJA
Junction-to-ambient thermal resistance
49
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
0.1
°C/W
RθJB
Junction-to-board thermal resistance
6.9
°C/W
ψJT
Junction-to-top characterization parameter
1.1
°C/W
ψJB
Junction-to-board characterization parameter
6.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
VIN = 3.6 V, TA = –10°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.7
3.6
6
2.3
3.6
6
UNIT
INPUT VOLTAGE
Input voltage range
VIN
Extended input voltage range
VLOW_BAT
VUVLO
VSTARTUP
(1)
VINA, VINR, VINL
V
Low battery warning threshold
VINA falling
3
Hysteresis
VINA rising
100
Undervoltage lockout threshold
VINA falling
2.3
V
Hysteresis
VINA rising
100
mV
Startup voltage
VBIAS, VOFS, VRST loaded with 2 mA
2.5
V
mV
V
INPUT CURRENT
IQ
ACTIVE2 mode
12
mA
ISTD
STANDBY mode
360
µA
ISLEEP
SLEEP mode
10
µA
INTERNAL SUPPLIES
VV6V
Internal supply, analog
6.25
V
CLDO_V6V
Filter capacitor for V6V LDO
100
nF
VV2V5
Internal supply, logic
2.5
V
CLDO_V2V5
Filter capacitor for V2V5 LDO
2.2
µF
DMD REGULATOR
RDS(ON)
VFW
MOSFET on resistance
Forward voltage drop
Switch E (from VINR to SWN)
1000
Switch F (from SWP to PGND)
320
Switch G (from SWP to VBIAS) (2)
VINR = 5 V, VSWP = 2 V, IF = 100 mA
1.3
Switch H (from SWP to VOFS)
VINR = 5 V, VSWP = 2 V, IF = 100 mA
1.3
mΩ
V
RDIS
Discharge resistor (SWP to GND)
Active when all rails are disabled
2
kΩ
tPG
Power-good timeout
Not tested in production
6
ms
ILIMIT
Switch current limit
200 (3)
mA
L
Inductor value
10
µH
(1)
(2)
(3)
6
Full functional but limited parametric performance.
Including rectifying diode.
Contact factory for 100-mA and 300-mA options.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
Electrical Characteristics (continued)
VIN = 3.6 V, TA = –10°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOFS REGULATOR
Output voltage
8.5
IOUT = 2 mA
DC load regulation
VIN = 3.6 V, IOUT= 0 mA to 4 mA
–19
V/A
DC line regulation
VINA, VINL, VINR 2.7 V to 6 V,
IOUT = 2 mA
35
mV/V
VRIPPLE
Output ripple
VIN = 3.6 V, IOUT = 4 mA, COUT = 220 nF
240
mV
IOUT
Output current
PG
Power-good threshold
(fraction of nominal output voltage)
VOFS rising
85%
VOFS falling
62%
RDIS
Output discharge resistor
Active when rail is disabled
C
Output capacitor
Recommended value
VOFS
–2%
V
DC output voltage accuracy
2%
0
110
3
mA
2
kΩ
220
nF
16
V
VBIAS REGULATOR
Output voltage
DC output voltage accuracy
IOUT = 2 mA
DC load regulation
VIN = 3.6 V, IOUT = 0 mA to 4 mA
DC line regulation
VINA, VINL, VINR 2.7 V to 6 V,
IOUT = 2 mA
VRIPPLE
Output ripple
VIN = 3.6 V, IOUT = 4 mA, COUT = 220 nF
IOUT
Output current
PG
Power-good threshold
(fraction of nominal output voltage)
VOFS rising
85%
VOFS falling
62%
RDIS
Output discharge resistor
Active when rail is disabled
C
Output capacitor
Recommended value
VBIAS
–2%
2%
–14
V/A
18
mV/V
240
0
110
mV
4
mA
2
kΩ
220
nF
VRST REGULATOR
Output voltage
–10
IOUT = 2 mA
DC load regulation
VIN = 3.6 V, IOUT = 0 mA to 4 mA
13
V/A
DC line regulation
VINA, VINL, VINR 2.7 V to 6 V,
IOUT = 2 mA
–21
mV/V
VRIPPLE
Output ripple
VIN = 3.6 V, IOUT = 4 mA, COUT = 220 nF
240
mV
VREF_VRST
Reference voltage
IOUT
Output current
PG
Power-good threshold
C
Output capacitor
VRST
–2%
V
DC output voltage accuracy
2%
500
0
Recommended value
110
mV
4
mA
–9.1
V
220
nF
VLED BUCK-BOOST
VLED
Output voltage range
1.2
5.9
Default output voltage
SW4/5/6 in OPEN position
3.5
VOVP
Output overvoltage protection
Clamps buck-boost output
5.9
VLED_OVP
Fault detection threshold
Triggers VLED_OVP interrupt
5.4
ISW
Switch current limit
RDS(ON)
MOSFET on resistance
fSW
Switching frequency
COUT
Output capacitance
1.65
2.2
Switch A (from VINL to L1)
100
Switch B (from L1 to GND)
100
Switch C (from L2 to GND)
100
Switch D (from L2 to VLED)
V
V
2.5
2 × 10
Submit Documentation Feedback
Product Folder Links: DLPA1000
A
mΩ
100
2.25
Copyright © 2017, Texas Instruments Incorporated
V
MHz
µF
7
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
Electrical Characteristics (continued)
VIN = 3.6 V, TA = –10°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
SW1, SW2, SW3
50
100
SW4, SW5, SW6
40
100
UNIT
RGB STROBE CONTROLLER SWITCHES
RDS(ON)
Drain-source on resistance
ILEAK
Off-state leakage current
VDS = 5 V
mΩ
1
µA
4.8
V
LED CURRENT CONTROL
Vf
LED forward voltage
Maximum LED drive current
ILED
DC current accuracy, SW4, 5, 6
Transient LED current limit range
Current rise time (4)
trise
ILED = 1 A
VIN = 3.1 V, VLED = 4.4 V
700
VIN = 4 V, VLED = 4.4 V
mA
1000
SWx_IDAC[9:0] = 0x100h
RLIM = 100 mΩ, 0.1%, TA = 25°C
258
272
ILIM[2:0] = 000
260
ILIM[2:0] = 111
1250
ILED from 5% to 95%, ILED = 300 mA, transient
current limit disabled
286
mA
mA
50
µs
MEASUREMENT SYSTEM (AFE)
G
Amplifier gain (PGA)
AFE_GAIN[1:0] = 01
1
AFE_GAIN[1:0] = 10
9.5
AFE_GAIN[1:0] = 11
VOFS
Input referred offset voltage (4)
tsettle
Settling time (4)
fsample
Sampling rate (4)
PGA, AFE_CAL_DIS = 1
Comparator
V/V
18
–1
1
–1.5
1.5
To 1% of final value
15
To 0.1% of final value
52
mV
µs
19
kHz
LOGIC LEVELS AND TIMING CHARACTERISTICS
VOL
Output low-level
VOH
Output high-level
IO = 0.5 mA, sink current
(RESETZ, PWR_EN, CMP_OUT)
0
0.3
IO = 5 mA, sink current
(SPI_DOUT, INTZ)
0
0.3
IO = 0.5 mA, source current
(RESETZ, PWR_EN, CMP_OUT)
1.3
2.5
IO = 5 mA, sink current
(SPI_DOUT)
1.3
2.5
VIL
Input low-level
TEST, PROJ_ON, LED_SEL0, LED_SEL1,
SPI_CSZ, SPI_CLK, SPI_DIN
VIH
Input high-level
TEST, PROJ_ON, LED_SEL0, LED_SEL1,
SPI_CSZ, SPI_CLK, SPI_DIN
I(bias)
Input bias current
VIO = 3.3 V
Any input pin
tdeglitch
Deglitch time (4)
(4)
8
(PROJ_ON, TEST) pins
(LED_SEL0, LED_SEL1) pins
V
V
0.4
1.2
V
V
0.5
µA
1
ms
300
ns
Not tested in production.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
Electrical Characteristics (continued)
VIN = 3.6 V, TA = –10°C to 85°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INTERNAL OSCILLATOR
fOSC
Oscillator frequency
9
Frequency accuracy
TA = –40°C to 85°C
MHz
–10%
10%
THERMAL SHUTDOWN
Thermal warning (HOT threshold)
TWARN
120
Hysteresis
TSHTDWN
°C
10
Thermal shutdown (TSD threshold)
150
Hysteresis
°C
15
6.6 Timing Requirements
VBAT = 3.6 V ±5%, TA = 25°C, CL = 10 pF (unless otherwise noted)
PARAMETER
MIN
TYP
UNIT
33.34
MHz
fCLK
Serial clock frequency
tCLKL
Pulse width low, SPI_CLK, 50% level
10
tCLKH
Pulse width high, SPI_CLK, 50% level
10
tt
Transition time, 20% to 80% level, all signals
0.2
tCSCR
SPI_CSZ falling to SPI_CLK rising, 50% level
tCFCS
SPI_CLK falling to SPI_CSZ rising, 50% level
tCDS
SPI_DIN data setup time, 50% level
tCDH
SPI_DIN data hold time, 50% level
tiS
SPI_DOUT data setup time (1), 50% level
tiH
SPI_DOUT data hold time (1), 50% level
0
ns
tCFDO
SPI_CLK falling to SPI_DOUT data valid, 50% level
tCSZ
SPI_CSZ rising to SPI_DOUT HiZ
(1)
0
MAX
ns
ns
4
ns
8
ns
1
ns
7
ns
6
ns
10
ns
13
ns
6
ns
The DPPxxxx processors send and receive data on the falling edge of the clock.
SPI_CSZ
(SS)
tCSCR
tCLKL
tCLKH
tCFCS
SPI_CLK
(SCLK)
tCDS
tCDH
SPI_DIN
(MOSI)
tCFDO
SPI_DOUT
(MISO)
tiS
HiZ
tiH
tCSZ
HiZ
Figure 1. SPI Timing Diagram
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
9
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
6.7 Typical Characteristics
The maximum output current of the buck-boost is a function of input voltage (VIN), and output voltage (VLED). The
relationship between VIN, VLED, and MAX ILED is shown in Figure 2. Please note that VLED is the output of the buck-boost
regulator which includes the voltage drop across the sense resistor (100 mΩ), internal strobe control switch (100-mΩ max),
and the forward voltage of the LED. For example, to drive 1-A of current through a LED with Vf = 4.2 V, the minimum input
voltage needs to be ≥ 3.7 V (VLED = 4.2 V + 1 A × 100 mΩ + 1 A × 100 mΩ = 4.4 V). For an input voltage of 3.1 V and a drive
current of 700 mA, the max VLED voltage cannot exceed 4.4 V.
1100
1000
VLED=3.6V
MAX ILED[mA]
900
800
VLED=4.0V
700
600
VLED=4.4V
500
400
VLED=4.8V
300
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VIN [V]
Measured on a typical unit. Note that VLED is the output of the buck-boost regulator and includes the voltage drop across the sense resistor,
internal strobe control switch, and the forward voltage of the LED.
Figure 2. Maximum LED Output Current as a Function of Input Voltage (VIN) and BB Output Voltage (VLED)
10
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
7 Detailed Description
7.1 Overview
DLPA1000 is a power management IC optimized for TI DLP® Pico™ Projector systems and meant for use in
either embedded or accessory mobile phone applications. For embedded applications, the projector is built into
the mobile phone and operates from the mobile phone’s single cell battery. In accessory applications, the
projector resides in its own enclosure and has its own battery or external power supply and operates as a standalone device.
DLPA1000 contains a complete LED driver and can supply up to 1 A per LED. Integrated high-current switches
are included for sequentially selecting a red, green, or blue LED. The DLPA1000 also contains three regulated
DC supplies for the DMD: VBIAS, VRST and VOFS.
The DLPA1000 contains a serial periphery interface (SPI) used for setting the configuration. Using SPI, currents
can be set independently for each LED with 10-bit resolution. Other features included are the generation of the
system reset, power sequencing, input signals for sequentially selecting the active LED, IC self-protection, and
an analog multiplexer and comparator to support A/D conversion of system parameters.
7.2 Functional Block Diagram
VINA
From system power
Reference
System
V2V5
LDO_V2V5
VLED
2.2 F
1 F
VREF
UVLO
VLED_OVP
V6V
LDO_V6V
VINL
VINL
LOW_BAT
VREF
AGND
AGND1
AFE_GAIN [1:0]
CMP_OUT
To host
MUX
VINA/3
VLED/3
SW4
SW5
SW6
RLIM_K
VLED
Buck-Boost
SENS1
SENS2
From light sensor
From temperature sensor
10 F
VRST (±10 V)
220 nF
100k
SWN
REF_VRST
SWP
H
G
VBIAS (16 V)
VOFS (8.5 V)
PGNDR
VBIAS
VOFS
PGNDL
PGNDL
C
L2
L2
VLED
VLED
VLED
From system power
1 F
2.2 F
10 F
10 F
E
10 F
220 nF
B
D
VINR
From system power
L1
L1
AFE_SEL[2:0]
AFE
PWM_IN
From host
A
100 nF
DMD
Reset
Regulators
SW1
SW2
SW3
SW4
SW5
SW6
RGB
Strobe
Decoder
F
RLIM
RLIM
RLIM_K
RGB LED
Assembly
100 m
220 nF
TEST
PROJ_ON
LED_SEL0
LED_SEL1
LDO_V2V5
From host
From host
From host
From host
From host
From host
From host
To host
V2V5
RESETZ
To system
V2V5
PWR_EN
To system
0.1 F
VSPI
SPI_CSZ
SPI_CLK
SPI_DIN
SPI_DOUT
Digital
Core
VIO
INTZ
SPI
To DPP (optional)
DGND
Copyright © 2017, Texas Instruments Incorporated
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
11
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
7.3 Feature Description
7.3.1 DMD Regulators
DLPA1000 contains three switch-mode power supplies that power the DMD. These rails are VOFS, VBIAS, and
VRST. 100 ms after pulling the PROJ_ON pin high, VOFS is powered up, followed by VBIAS and VRST with an
additional 10-ms delay. Only after all three rails are enabled can the LED driver and STROBE DECODER circuit
be enabled. If any one of the rails encounters a fault such as an output short, all three rails are disabled
simultaneously. The detailed power-up and power-down diagram is shown in Figure 3.
5 ms (min.)
System Power
5 ms (min.)
2.5 V
2.3 V
PROJ_ON
3.5 ms fixed delay
PWR_EN
129 ms
100 ms
RESETZ
PROJ_ON interrupt bit
INTZ pin
HiZ
VOFS
HiZ
12 ms
PRECHARGE
10 ms
VBIAS
25 ms
PRECHARGE
VRST
VLED
OFF
ACTIVE1
ACTIVE2
ACTIVE1
OFF
Power-up or down is initiated by pulling the PROJ_ON pin high or low, respectively. Upon pulling PROJ_ON high, the
device enters ACTIVE2 mode immediately because DMD_EN and VLED_EN bits default to 1.
Figure 3. Power-Up and Power-Down Timing of the DMD REGULATOR and VLED Supplies
7.3.2 RGB Strobe Decoder
DLPA1000 contains RGB color-sequential circuitry that is composed of six NMOS switches, the LED driver, the
strobe decoder and the LED current control. The NMOS switches are connected to the terminals of the external
LED package and turn the currents through the LEDs on and off. The strobe decoder controls the gates of the
NMOS switches according to the LED_SEL[1:0] input signals and the MAP bit of the SYSTEM register. The MAP
bit selects one of two package configurations. A ‘1’ indicates a cathode-cathode-anode package and a ‘0’
indicates the common anode package. The two package connections are shown in Figure 4 and the
corresponding switch map in Table 1 and Table 2.
12
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
Feature Description (continued)
The LED_SEL[1:0] signals typically receive a rotating code switching from RED to GREEN to BLUE and then
back to RED. When the LED_SEL[1:0] input signals select a specific color, the NMOSFETs are controlled based
on the color selected, and a 10-bit current control DAC for this color is selected that provides a color correction
current to the RGB LEDs feedback control network.
VLED
SW3
SW2
VLED
SW1
SW3
SW2
SW1
SW1
SW1
SW2
SW2
SW3
SW3
SW4
R
G
SW4
B
SW5
SW5
SW6
SW6
G
B
R
SW4
SW5
SW6
SW4
SW5
RLIM
SW6
RLIM
RLIM_K
RLIM_K
100m
100m
Figure 4. LEFT: Switch Connection for a Common-Anode LED Assembly
RIGHT: Switch Connection for a Cathode-Cathode-Anode LED Assembly
Table 1. Switch Positions for Common Anode RGB LEDs (MAP = 0)
MAP = 0 (Common Anode, Default)
LED_SEL[1:0]
SW6
SW5
SW4
SW3
SW2
SW1
IDAC input
0x00h
open
open
open
closed
closed
closed
N/A
0x01h
open
open
closed
closed
closed
closed
SW4_IDAC[9:0]
0x02h
open
closed
open
closed
closed
closed
SW5_IDAC[9:0]
0x03h
closed
open
open
closed
closed
closed
SW6_IDAC[9:0]
Table 2. Switch Positions for Cathode-Cathode-Anode RGB LEDs (MAP = 1)
MAP = 1 (Cathode-Cathode-Anode LED Arrangement)
LED_SEL[1:0]
SW6
SW5
SW4
SW3
SW2
SW1
IDAC input
0x00h
open
open
open
open
open
open
N/A
0x01h
closed
open
open
open
open
closed
SW4_IDAC[9:0]
0x02h
open
closed
closed
closed
open
open
SW5_IDAC[9:0]
0x03h
open
closed
closed
open
closed
open
SW6_IDAC[9:0]
The switching of the six NMOS switches is controlled such that switches are returned to the OPEN position first
before the CLOSED connections are made (Break Before Make). The dead time between opening and closing
switches is controlled through the BBM register. Switches that already are in the CLOSED position and are to
remain in the CLOSED state according to the SWCNTRL register, are not opened during the BBM delay time.
7.3.3 LED Current Control
DLPA1000 provides time-sequential circuitry to drive three LEDs with independent current control. A system
based on a common anode LED configuration is shown in Figure 6 and consists of a buck-boost converter which
provides the voltage to drive the LEDs, three switches connected to the cathodes of the LEDs, a 100-mΩ resistor
used to sense the LED current, and a current DAC to control the LED current.
The STROBE DECODER controls the switch positions as described in the section above. With all switches in the
OPEN position, the buck-boost output assumes an output voltage of 3.5 V.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
13
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
For a common-anode RGB LED configuration (MAP = 0, default), the BUCK-BOOST output voltage (VLED)
assumes a value such that the voltage drop across the sense resistor equals (SW4_IDAC[9:0] × 100 mΩ) when
SW4 is closed. The exact value of VLED depends on the current setting and the voltage drop across the LED but
is limited to 6.5 V. When the STROBE decoder switches from SW4 to SW5, the Buck-Boost assumes a new
output voltage such that the sense voltage equals (SW5_IDAC[9:0] × 100 mΩ), and finally, when SW6 is
selected, V(RLIM_K) is regulated to (SW6_IDAC[9:0] × 100 mΩ).
Similarly, the regulation current setting switches from SW4_IDAC[9:0] to SW5_IDAC[9:0] to SW6_IDAC[9:0]
depending on the LED_SEL[1:0] setting with a MAP setting of 1 (cathode-cathode-anode configuration). See
Table 2 for details.
7.3.3.1 LED Current Accuracy
LED drive current is controlled by a current DAC (digital to analog converter) and can be set independently for
switch SW4, SW5, and SW6. The DAC is trimmed to achieve a LED drive current of 272 mA at code 0x100h with
an accuracy of ±14 mA. The first order gain-error of the DAC can be neglected, therefore the LED driver current
accuracy of ±14 mA can be assumed over the full current range. For example, at full-scale (SWx_IDAC[9:0] =
0x3FFh) the LED current is regulated to 1030 mA ±14 mA or ±1.4%. At the lowest setting (0x001h) the LED
current is regulated to 20 mA ±14 mA and the resulting relative error is large; however this is not a typical
operating point for a projector application. A typical drive current for projection LEDs is 300 mA and the resulting
regulation error is < 5%.
7.3.3.2 Transient Current Limiting
Typically the forward voltages of the GREEN and BLUE diodes are close to each other (~3 V to 4 V) but Vf of the
RED diode is significantly lower (1.8 V to 2.5 V). This can lead to a current spike in the RED diode when the
strobe controller switches from GREEN or BLUE to RED because VLED is regulated to a higher voltage than
required to drive the RED diode. DLPA1000 provides transient current limiting for each switch to limit the current
in the LEDs during the transition. The transient current limit value is controlled through the ILIM[2:0] bits in the
IREG register. The same register also contains three bits to select which switch employs the transient current
limiting feature. In a typical application it is required only for the RED diode and the ILIM[2:0] value should be set
approximately 10% higher than the DC regulation current. The effect that the transient current limit has on the
LED current is shown in Figure 5.
1200
900
1500
Current overshoot due
to Buck-Boost output
voltage change.
600
300
0
RED LED CURRENT [mA]
RED LED CURRENT [mA]
1500
1200
900
Transient current
limit active
600
300
0
TIME
TIME
LEFT: RED LED current without transient current limit. The current overshoots because the buck-boost voltage starts
at the (higher) level of the GREEN or BLUE LED.
RIGHT: LED current with transient current limit.
Figure 5. RED LED Current With and Without Transient Current Limit
14
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
FB
VLED
BUCK-BOOST
VLED
SW4LIM_EN
SW4
0
ILIM[2:0]
VDAC
E/A
1
SW5LIM_EN
SW5
0
E/A
1
SW6LIM_EN
SW6
0
LED_SEL[1:0]
MAP
STROBE
DECODER
RLIM
E/A
1
SW4_IDAC[9:0]
SW5_IDAC[9:0]
RLIM_K
IDAC
200 W
SW6_IDAC[9:0]
100 mW
Copyright © 2017, Texas Instruments Incorporated
Figure 6. Block Diagram of the LED Driver Circuitry
7.3.4 Measurement System
The measurement system is composed of a 8:1 analog multiplexer (MUX), a programmable-gain amplifier and a
comparator. It works together with the DPP processor to provide:
• White-point correction (WPC) by independently adjusting the R/G/B LED currents, after measuring the
brightness of each color from an external light sensor.
• A measurement of the battery voltage.
• A measurement of the LED forward voltage.
• A measurement of the exact LED current.
• A measurement of temperature as derived by measuring the voltage across an external thermistor.
A block diagram of the measurement system is shown in Figure 7.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
15
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
VINA VLED
AFE_GAIN [1:0]
CMP_OUT
To host
2R
2R
1R
1R
AFE
PWM_IN
From host
AFE_SEL[2:0]
MUX
SW4
SW5
SW6
RLIM_K
SENS1
From light sensor
SENS2
From temperature sensor
Copyright © 2017, Texas Instruments Incorporated
Figure 7. Block Diagram of the Measurement System
Table 3. Recommended Configuration of the AFE for Different Input Selections
AFE_SEL[2:0]
SELECTED INPUT
RECOMMENDED GAIN SETTING
AFE-GAIN[1:0]
RECOMMENDED SETTING OF
AFE_CAL_DIS BIT
0x00h
SENS2
0x01h (1x)
Setting has no effect on measurement
0x01h
VLED
0x01h (1x)
Setting has no effect on measurement
0x02h
VINA
0x01h (1x)
Setting has no effect on measurement
0x03h
SENS1
0x01h (1x)
Setting has no effect on measurement
0x04h
RLIM_K
0x03h (18x)
Set to 1 if sense voltage is > 100 mV,
otherwise set to 0 (default).
0x05h
SW4
0x02h (9.5x)
Set to 1 if sense voltage is > 200 mV,
otherwise set to 0 (default).
0x06h
SW5
0x02h (9.5x)
Set to 1 if sense voltage is > 200 mV,
otherwise set to 0 (default).
0x07h
SW6
0x02h (9.5x)
Set to 1 if sense voltage is > 200 mV,
otherwise set to 0 (default).
7.3.5 Protection Circuits
DLPA1000 has several protection circuits to protect the IC as well as the system from damage due to excessive
power consumption, die temperature, or over-voltages. These circuits are described below.
7.3.5.1 Thermal Warning (HOT) and Thermal Shutdown (TSD)
DLPA1000 continuously monitors the junction temperature and issues a HOT interrupt if temperature exceeds
the HOT threshold. If the temperature continues to increase above the thermal shutdown threshold, all rails are
disabled and the TSD bit in the INT register is set. Once the temperature drops by 15°C, the output rails are
powered up in sequence and normal operation resumes (DMD_EN bit is not reset by TSD fault).
Thermal shutdown
threshold
Thermal warning
threshold
hysteresis
hysteresis
Temperature
HOT
(internal signal)
TSD
(internal signal)
Available time for controlled
shutdown of System
Figure 8. Definition of the Thermal Shutdown and Hot-Die Temperature Warning
16
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
7.3.5.2 Low Battery Warning (BAT_LOW) and Undervoltage Lockout (UVLO)
If the battery voltage drops below the BAT_LOW threshold (typically 3 V) the BAT_LOW interrupt is issued but
normal operation continues. Once the battery drops below the undervoltage threshold (typically 2.3 V) the UVLO
interrupt is issued, all rails are powered down in sequence, the DMD_EN bit is reset, and the part enters
STANDBY mode. The power rails cannot be re-enabled before the input voltage recovers to > 2.4 V. To reenable the rails, the PROJ_ON pin must be toggled.
VINA
hysteresis
BAT_LOW threshold
hysteresis
UVLO threshold
ACTIVE
BAT LOW
(internal signal)
INACTIVE
200 ms
deglitch
UVLO
(internal signal)
ACTIVE
INACTIVE
200 ms
deglitch
Figure 9. Undervoltage Lockout is Asserted When the Input Supply Drops Below the UVLO Threshold
7.3.5.3 DMD Regulator Fault (DMD_FLT)
The DMD regulator is continuously monitored to check if the output rails are in regulation and if the inductor
current increases as expected during a switching cycle. If either one of the output rails drops out of regulation
(e.g. due to a shorted output) or the inductor current does not increase as expected during a switching cycle (due
to a disconnected inductor), the DMD_FLT interrupt bit is set in the INT register, the DMD_EN bit is reset, and
the DMD regulator is shut down. Resetting the DMD_EN bit also causes the LED driver to power down. To
restart the system, the PROJ_ON pin must be toggled.
7.3.5.4 V6V Power-Good (V6V_PGF) Fault
The VLED buck-boost requires the V6V rail for proper operation. The rail is continuously monitored and should
the output drop below the power-good threshold, the V6V_PGF bit is set. The buck-boost is disabled and
attempts to restart automatically.
7.3.5.5 VLED Over-Voltage (VLED_OVP) Fault
If the buck-boost output voltage rises above 6.5 V, the VLED_OVP interrupt is set but the buck-boost regulator is
not turned off. A typical condition to cause this fault is an open LED.
7.3.6 Interrupt Pin (INTZ)
The interrupt pin is used to signal events and fault conditions to the host processor. Whenever a fault or event
occurs in the IC, the corresponding interrupt bit is set in the INT register, and the open-drain output is pulled low.
The INTZ pin is released (returns to HiZ state) and fault bits are cleared when the INT register is read by the
host. However, if a failure persists, the corresponding INT bit remains set and the INTZ pin is pulled low again
after a maximum of 32 µs.
Interrupt events include fault conditions such as power-good faults, over-voltage, over-temperature shut-down,
and under-voltage lock-out.
The MASK register is used to mask events from generating interrupts, i.e. from pulling the INTZ pin low. The
MASK settings affect the INTZ pin only and have no impact on protection and monitor circuits themselves. When
an interrupt is masked, the event causing the interrupt still sets the corresponding bit in the INT register.
However, it does not pull the INTZ pin low.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
17
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
Note that persisting fault conditions such as thermal shutdown can cause the INTZ pin to be pulled low for an
extended period of time which can keep the host in a loop trying to resolve the interrupt. If this behavior is not
desired, set the corresponding mask bit after receiving the interrupt and keep polling the INT register to see
when the fault condition has disappeared. After the fault is resolved, unmask the interrupt bit again.
7.3.7 Serial Peripheral Interface (SPI)
DLPA1000 provides a 4-wire SPI port that supports high-speed serial data transfers up to 33.3 MHz. Register
and data buffer write and read operations are supported. The SPI_CSZ input serves as the active low chip select
for the SPI port. The SPI_CSZ input must be forced low in order to write or read registers and data buffers.
When SPI_CSZ is forced high, the data at the SPI_DIN input is ignored, and the SPI_DOUT output is forced to a
high-impedance state. The SPI_DIN input serves as the serial data input for the port; the SPI_DOUT output
serves as the serial data output. The SPI_CLK input serves as the serial data clock for both the input and output
data. Data is latched at the SPI_DIN input on the rising edge of SPI_CLK, while data is clocked out of the
SPI_DOUT output on the falling edge of SPI_CLK. Figure 10 illustrates the SPI port protocol. Byte 0 is referred to
as the command byte, where the most significant bit is the write/not read bit. For the W/nR bit, a 1 indicates a
write operation, while a 0 indicates a read operation. The remaining seven bits of the command byte are the
register address targeted by the write or read operation. The SPI port supports write and read operations for
multiple sequential register addresses through the implementation of an auto-increment mode. As shown in
Figure 10, the auto-increment mode is invoked by simply holding the SPI_CSZ input low for multiple data bytes.
The register address is automatically incremented after each data byte transferred, starting with the address
specified by the command byte. After reaching address 0x7Fh the address pointer jumps back to 0x00h.
Set SPI_CSZ=1 here to write/read one register location
Hold SPI_CSZ=0 to enable auto-increment mode
SPI_CSZ
Header
SPI_DIN
Byte0
Register Data (write)
Byte1
Byte2
Byte3
ByteN
Register Data (read)
SPI_DOUT
Data for A[6:0]
Data for A[6:0]+1
Data for A[6:0]+(N-2)
SPI_CLK
Byte 0
SPI_DIN
W/nR
Byte 1
A6 A5 A4 A3 A2 A1 A0 N7 N6 N5 N4 N3 N2 N1 N0
W/nR
Set high for write, low for read
Register Address
SPI_CLK
Figure 10. SPI Protocol
18
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
7.4 Device Functional Modes
Table 4. Modes of Operation
MODE
DESCRIPTION
OFF
This is the lowest-power mode of operation. All power functions are turned off, registers are reset to their default values and
the IC does not respond to SPI commands. RESETZ and PWR_EN pins are pulled low. The IC will enter OFF mode
whenever the PROJ_ON pin is pulled low.
RESET
Logic core and registers are reset to default values, the IC does not respond to SPI commands, RESETZ and PWR_EN pins
are pulled low, but the analog reference system is kept alive. The device enters RESET state when the input voltage drops
below the UVLO threshold.
STANDBY
All power functions are turned off but the IC does respond to the SPI interface. The device enters STANDBY mode when
PROJ_ON pins is high, but DMD_EN bit is set to 0. Also, device enters STANDBY mode when a fault on the DMD regulator
occurs or the temperature increases above thermal shutdown threshold (TSD). (1)
ACTIVE1
The DMD supplies are powered up but LED power (VLED) and the STROBE DECODER are disabled. PROJ_ON pin must
be high, DMD_EN bit must be set to 1, and VLED_EN bit set to 0.
ACTIVE2
DMD supplies, LED power and STROBE DECODER are enabled. PROJ_ON pin must be high and DMD_EN and VLED_EN
bits must both be set to 1.
(1)
DMD_EN power-up default is 1. Once the bit is set to 0, the PROJ_ON pin must be toggled to recover the bit to 1.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
19
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
POWER DOWN
Valid power source connected
VRST = OFF &
VBIAS = OFF &
VOFS = OFF &
VLED = OFF &
STROBE DECODER disabled &
SPI interface disabled
PWR_EN is low
RESETZ is low
All registers reset to default values
PROJ_ON = low
ANY STATE
OFF
PROJ_ON = high
VRST = OFF &
VBIAS = OFF &
VOFS = OFF &
VLED = OFF &
STROBE DECODER disabled &
SPI interface disabled
PWR_EN is low
RESETZ is low
All registers reset to default values
PROJ_ON = high &
not UVLO
RESET
STANDBY
DMD_EN = 0(1) ||
FAULT
VRST = OFF &
VBIAS = OFF &
VOFS = OFF &
VLED = OFF &
STROBE DECODER disabled &
SPI interface enabled
PWR_EN is high
RESETZ is high
DMD_EN = 1(1) &
No FAULT
UVLO
VRST = ON &
VBIAS = ON &
VOFS = ON &
VLED = OFF &
STROBE DECODER disabled &
SPI interface enabled
PWR_EN is high
RESETZ is high
ACTIVE1
VLED_EN = 0
VLED_EN = 1
VRST = ON &
VBIAS = ON &
VOFS = ON &
VLED = ON &
STROBE DECODER enabled
SPI interface enabled
PWR_EN is high
RESETZ is high
ACTIVE2
NOTES:
|| = OR, & = AND, (­) = rising edge, (¯) = falling edge
FAULT = Undervoltage on VRST, VBIAS, VOFS, or DMD regulator current-limit fault (DMD_FLT) ||
Thermal Shut Down (TSD)
DMD_PG and UVLO faults reset the DMD_EN bit and keep the part in STANDBY mode
.
TSD does not reset DMD_EN bit, so part resumes normal operation after the part has cooled off
.
(1) : DMD_EN bit power-up default is 1. The bit can be reset by writing to the ENABLE register but to set
the bit back to1 requires toggling of PROJ_ON
Figure 11. State Diagram
7.5 Programming
7.5.1 Password Protected Registers
Register address 0x11h through 0x27h can be read-accessed the same way as any other register but are
protected against accidental write operations through the PASSWORD register (address 0x10h). To write to a
protected register, first:
• Write data 0xBAh to register address 0x10h, then
• Write data 0xBEh to register address 0x10h.
20
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
Programming (continued)
Both writes must be consecutive, i.e. there must be no other read or write operation in between sending the two
bytes. Once the password has been successfully written, register 0x11h through 0x27h are unlocked and can be
write accessed using the regular SPI protocol. They remain unlocked until any byte other than 0xBAh is written to
the PASSWORD register or the part is power cycled.
To check if the registers are unlocked, read back the PASSWORD register. If the data returned is 0x00h, the
registers are locked. If the PASSWORD register returns 0x01h, the registers are unlocked.
7.6 Register Maps
Table 5. Register Address Map
Address
Acronym
Register Name
Section
0x00h
CHIPID
Chip revision register
Go
0x01h
ENABLE
Enable register
Go
0x02h
IREG
Transient-current limit settings
Go
0x03h
SW4MSB
Regulation current MSBs, SW4
Go
0x04h
SW4LSB
Regulation current LSBs, SW4
Go
0x05h
SW5MSB
Regulation current MSBs, SW5
Go
0x06h
SW5LSB
Regulation current LSBs, SW5
Go
0x07h
SW6MSB
Regulation current MSBs, SW6
Go
0x08h
SW6LSB
Regulation current LSBs, SW6
Go
0x09h
RESERVED
Reserved
0x0Ah
AFE
AFE (MUX) control
Go
0x0Bh
BBM
Break before make timing
Go
0x0Ch
INT
Interrupt register
Go
0x0Dh
INT MASK
Interrupt mask register
Go
0x10h
PASSWORD
Password register
Go
0x11h
SYSTEM
System configuration register
Go
0x20h
BYTE0
User EEPROM, Byte0
Go
0x21h
BYTE1
User EEPROM, Byte1
Go
0x22h
BYTE2
User EEPROM, Byte2
Go
0x23h
BYTE3
User EEPROM, Byte3
Go
0x24h
BYTE4
User EEPROM, Byte4
Go
0x25h
BYTE5
User EEPROM, Byte5
Go
0x26h
BYTE6
User EEPROM, Byte6
Go
0x27h
BYTE7
User EEPROM, Byte7
Go
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
21
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
7.6.1 Chip ID (CHIPID) Register (address = 0x00h) [reset = A6h]
Figure 12. CHIPID Register
7
6
5
4
3
2
1
0
1
DMD_EN
R/W-1h
0
VLED_EN
R/W-1h
CHIPID[7:0]
R-A6h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6. CHIPID Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
CHIPID
R
A6h
1010 0000b = DLPA1000 (Rev 1p0)
1010 0010b = DLPA1000 (Rev 1p1)
1010 0110b = DLPA1000 (Rev 1p2)
7.6.2 Enable (ENABLE) Register (address = 0x01h) [reset = 3h]
Figure 13. ENABLE Register
7
6
5
4
3
2
RESERVED
R-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7. ENABLE Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
0h
N/A
1h
DMD Regulator enable/status bit
0b = disabled (OFF)
1b = enabled (ON)
NOTE: Power-up default is 1. Once set to 0, the PROJ_ON pin
must be toggled to set the bit back to 1. If bit is set to 0, VLED
buck-boost will automatically be disabled.
1h
VLED Buck-Boost enable bit
0b = disabled (OFF)
1b = enabled (ON)
NOTE: Bit does not reflect current status of VLED buck-boost.
NOTE: If VLED is disabled, RGB Strobe Decoder will automatically
be disabled
1
0
22
DMD_EN
VLED_EN
R/W
R/W
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
7.6.3 Switch Transient Current Limit (IREG) Register (address = 0x02h) [reset = 28h]
Figure 14. IREG Register
7
6
5
4
ILIM[2:0]
R/W-5h
RESERVED
R-0h
3
2
SW6LIM_EN
R/W-0h
1
SW5LIM_EN
R/W-0h
0
SW4LIM_EN
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 8. IREG Register Field Descriptions
Bit
Field
Type
Reset
Description
7-6
RESERVED
R
0h
N/A
ILIM[2:0]
R/W
5h
Transient current-limit
000b = 260 mA
001b = 300 mA
010b = 345 mA
011b = 385 mA
100b = 440 mA
101b = 660 mA
110b = 880 mA
111b = 1250 mA
NOTE: Transient current limit should always be set higher than
regulation current
2
SW6LIM_EN
R/W
0h
Transient current-limit enable for SW6
0b = transient current-limit is disabled
1b = transient current-limit is enabled
1
SW5LIM_EN
R/W
0h
Transient current-limit enable for SW5
0b = transient current-limit is disabled
1b = transient current-limit is enabled
0
SW4LIM_EN
R/W
0h
Transient current-limit enable for SW4
0b = transient current-limit is disabled
1b = transient current-limit is enabled
5-3
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
23
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
7.6.4 SW4 LED DC Regulation Current, MSB (SW4MSB) Register (address = 0x03h) [reset = 0h]
Figure 15. SW4MSB Register
7
6
5
4
3
2
1
RESERVED
R-0h
0
SW4_IDAC[9:8]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9. SW4MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
0h
N/A
1-0
SW4_IDAC[9:8]
R/W
0h
Switch4 DC regulation, most significant byte (MSB)
7.6.5 SW4 LED DC Regulation Current, LSB (SW4LSB) Register (address = 0x04h) [reset = 0h]
Figure 16. SW4LSB Register
7
6
5
4
3
2
1
0
SW4_IDAC[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 10. SW4LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
SW4_IDAC[7:0]
R/W
0h
Switch4 DC current limit, least significant byte (MSB)
SW4_IDAC[9:0]
LED
CURRENT (1)
SW4_IDAC[9:0]
LED
CURRENT (1)
SW4_IDAC[9:0]
LED
CURRENT (1)
SW4_IDAC[9:0]
LED
CURRENT (1)
0x000h
0 mA
0x100h
272 mA
0x200h
525 mA
0x300h
777.99 mA
0x001h
19.99 mA
0x101h
272.99 mA
0x201h
525.98 mA
0x301h
778.98 mA
0x002h
20.98 mA
0x102h
273.98 mA
0x202h
526.97 mA
0x302h
779.97 mA
...
...
...
...
...
...
...
...
0x0FEh
270.02 mA
0x1FEh
523.602 mA
0x2FEh
776.02 mA
0x3FEh
1029.01 mA
0x0FFh
271.01 mA
0x1FFh
524.01 mA
0x2FFh
777 mA
0x3FFh
1030 mA
(1)
24
Values shown are for a typical unit at TA = 25°C. Typical step size is 988 µA.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
7.6.6 SW5 LED DC Regulation Current, MSB (SW5MSB) Register (address = 0x05h) [reset = 0h]
Figure 17. SW5MSB Register
7
6
5
4
3
2
1
RESERVED
R-0h
0
SW5_IDAC[9:8]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 11. SW5MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
0h
N/A
1-0
SW5_IDAC[9:8]
R/W
0h
Switch5 DC regulation, most significant byte (MSB)
7.6.7 SW5 LED DC Regulation Current, LSB (SW5LSB) Register (address = 0x06h) [reset = 0h]
Figure 18. SW5LSB Register
7
6
5
4
3
2
1
0
SW5_IDAC[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 12. SW5LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
SW5_IDAC[7:0]
R/W
0h
Switch5 DC current limit, least significant byte (LSB)
SW5_IDAC[9:0]
LED
CURRENT (1)
SW5_IDAC[9:0]
LED
CURRENT (1)
SW5_IDAC[9:0]
LED
CURRENT (1)
SW5_IDAC[9:0]
LED
CURRENT (1)
0x000h
0 mA
0x100h
272 mA
0x200h
525 mA
0x300h
777.99 mA
0x001h
19.99 mA
0x101h
272.99 mA
0x201h
525.98 mA
0x301h
778.98 mA
0x002h
20.98 mA
0x102h
273.98 mA
0x202h
526.97 mA
0x302h
779.97 mA
...
...
...
...
...
...
...
...
0x0FEh
270.02 mA
0x1FEh
523.602 mA
0x2FEh
776.02 mA
0x3FEh
1029.01 mA
0x0FFh
271.01 mA
0x1FFh
524.01 mA
0x2FFh
777 mA
0x3FFh
1030 mA
(1)
Values shown are for a typical unit at TA = 25°C. Typical step size is 988 µA.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
25
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
7.6.8 SW6 LED DC Regulation Current, MSB (SW6MSB) Register (address = 0x07h) [reset = 0h]
Figure 19. SW6MSB Register
7
6
5
4
3
2
1
RESERVED
R-0h
0
SW6_IDAC[9:8]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 13. SW6MSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R
0h
N/A
1-0
SW6_IDAC[9:8]
R/W
0h
Switch6 DC regulation, most significant byte (MSB)
7.6.9 SW6 LED DC Regulation Current, LSB (SW6LSB) Register (address = 0x08h) [reset = 0h]
Figure 20. SW6LSB Register
7
6
5
4
3
2
1
0
SW6_IDAC[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. SW6LSB Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
SW6_IDAC[7:0]
R/W
0h
Switch6 DC current limit, least significant byte (LSB)
SW6_IDAC[9:0]
LED
CURRENT (1)
SW6_IDAC[9:0]
LED
CURRENT (1)
SW6_IDAC[9:0]
LED
CURRENT (1)
SW6_IDAC[9:0]
LED
CURRENT (1)
0x000h
0 mA
0x100h
272 mA
0x200h
525 mA
0x300h
777.99 mA
0x001h
19.99 mA
0x101h
272.99 mA
0x201h
525.98 mA
0x301h
778.98 mA
0x002h
20.98 mA
0x102h
273.98 mA
0x202h
526.97 mA
0x302h
779.97 mA
...
...
...
...
...
...
...
...
0x0FEh
270.02 mA
0x1FEh
523.602 mA
0x2FEh
776.02 mA
0x3FEh
1029.01 mA
0x0FFh
271.01 mA
0x1FFh
524.01 mA
0x2FFh
777 mA
0x3FFh
1030 mA
(1)
26
Values shown are for a typical unit at TA = 25°C. Typical step size is 988 µA.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
7.6.10 Analog Front End Control (AFE) Register (address = 0x0Ah) [reset = 0h]
Figure 21. AFE Register
7
RESERVED
R-0h
6
AFE_EN
R-0h
5
AFE_CAL_DIS
R/W-0h
4
3
2
1
AFE_SEL[2:0]
R/W-0h
AFE_GAIN[1:0]
R/W-0h
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. AFE Register Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
0h
N/A
6
AFE_EN
R
0h
Enable bit for AFE
0b = AFE is disabled
1b = AFE is enabled
NOTE: Comparator output is in HiZ state when disabled.
0h
Calibration disable bit. Set this bit high to disable the factory
calibration setting. May result in lower offset error if sensed input
voltage level is significantly greater than 40 mV (see Table 3).
0b = Factory calibration setting is enabled
1b = Factory calibration setting is disabled
0h
Gain setting of the programmable gain amplifier
00b = amplifier is off
01b = 1x
10b = 9.5x
11b = 18x
0h
AFE Multiplexer control
000b = SENS2
001b = VLED
010b = VINA
011b = SENS1
100b = RLIM_K
101b = SW4
110b = SW5
111b = SW6
5
AFE_CAL_DIS
4-3
R/W
AFE_GAIN
2-0
R/W
AFE_SEL[2:0]
R/W
7.6.11 Strobe Decode - Break Before Make Timing Control (BBM) Register (address = 0x0Bh) [reset =
0h]
Figure 22. BBM Register
7
6
5
4
3
2
1
0
BBM[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 16. BBM Register Field Descriptions
Bit
Field
Type
Reset
Description
Break before make timing. Time between opening one set of switches and closing
the next set. (1)
7-0
(1)
BBM[7:0]
R/W
0h
0x00 = 222 ns
0x01 = 333 ns
0x02 = 444 ns
...
0x3E = 7104 ns
0x3F = 7215 ns
0x40 = 7326 ns
0x41 = 7437 ns
0x42 = 7548 ns
...
0x7E = 14208 ns
0x7F = 14319 ns
0x80 = 14430 ns
0x81 = 14451 ns
0x82 = 14652 ns
...
0xBE = 21312 ns
0xBF = 21423 ns
0xC0 = 21534 s
0xC1 = 21645 ns
0xC2 = 21756 ns
...
0xFE = 28416 ns
0xFF = 28527 ns
It takes 333 ns to 444 ns to turn off the switches from the time a change occurs on LED_SEL[1:0].
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
27
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
7.6.12 Interrupt (INT) Register (address = 0x0Ch) [reset = X]
Figure 23. INT Register
7
VLED_OVP
R-X
6
V6V_PGF
R-X
5
PROJ_ON
R-X
4
DMD_FLT
R-X
3
UVLO
R-X
2
BAT_LOW
R-X
1
TSD
R-X
0
HOT
R-X
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; X = undefined
Table 17. INT Register Field Descriptions
Bit
Type
Reset
Description
7
VLED_OVP
R
X
VLED BUCK_BOOST over-voltage fault interrupt (normal
operation resumes)
0b = No fault
1b = BUCK-BOOST output is above OVP threshold
6
V6V_PGF
R
X
V6V power-good fault interrupt. (normal operation resumes)
0b = No fault
1b = V6V is not in regulation
5
PROJ_ON
R
X
PROJ_ON interrupt (part enters OFF mode)
0b = PROJ_ON pin is pulled high, normal mode
1b = PROJ_ON pin is pulled low. Alerts the DPP that DMD
regulator is about to shut down.
X
DMD REGULATOR FAULT (part enters STANDBY mode and
DMD_EN bit is cleared)
0b = No fault
1b = The inductor current is not increasing at the correct rate.
Likely to be caused by an open inductor or one of the regulator
outputs has dropped below the power-good threshold. Likely to be
caused by a short.
NOTE: DMD_FLT resets DMD_EN bit to 0.
4
28
Field
DMD_FLT
R
3
UVLO
R
X
Undervoltage lockout threshold (sensed at VINA pin) (part enters
RESET state)
0b = Battery voltage is above the UVLO threshold
1b = Battery voltage has dropped below the UVLO threshold
NOTE: UVLO resets DMD_EN bit to 0. 25ms after UVLO interrupt
part enters RESET state with SPI disabled.
2
BAT_LOW
R
X
Low-Battery warning (sensed at VINA pin) (normal operation
resumes)
0b = Battery voltage is above the low-battery threshold
1b = Battery voltage has dropped below the low-battery threshold
1
TSD
R
X
Thermal Shutdown interrupt (part enters STANDBY mode,
DMD_EN bit is not cleared)
0b = Die temperature is below the thermal shut-down threshold
1b = Die temperature is above thermal shut-down threshold or has
not cooled down enough to recover from TSD
0
HOT
R
X
Thermal warning interrupt (normal operation resumes)
0b = Die temperature is normal operating range
1b = Die temperature is above the HOT threshold or has not
cooled down enough to recover from HOT
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
7.6.13 Interrupt Mask (MASK) Register (address = 0x0Dh) [reset = 0h]
Figure 24. MASK Register
7
VLED_OVPM
R/W-0h
6
V6V_PGM
R/W-0h
5
PROJ_ONM
R/W-0h
4
DMD_FLTM
R/W-0h
3
UVLOM
R/W-0h
2
BAT_LOWM
R/W-0h
1
TSDM
R/W-0h
0
HOTM
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 18. MASK Register Field Descriptions
Bit
7
6
5
4
Field
VLED_OVPM
V6V_PGM
PROJ_ONM
DMD_FLTM
Type
R/W
R/W
R/W
R/W
Reset
Description
0h
VLED BUCK_BOOST over-voltage fault interrupt mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
0h
VLED BUCK_BOOST power-good fault interrupt mask
0b = no fault
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
0h
PROJ_ON interrupt mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
0h
DMD REGULATOR fault mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
3
UVLOM
R/W
0h
Undervoltage lockout threshold (sensed at VINA pin) mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
2
BAT_LOWM
R/W
0h
Low-Battery warning (sensed at VINA pin) mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
1
TSDM
R/W
0h
Thermal Shutdown interrupt mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
0
HOTM
R/W
0h
Thermal warning interrupt mask
0b = interrupt is not masked.
1b = Interrupt is masked. INTZ pin is not pulled low when interrupt
bit is set.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
29
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
7.6.14 Password (PASSWORD) Register (address = 0x10h) [reset = 0h]
Figure 25. PASSWORD Register
7
6
5
4
3
PASSWORD[7:0]
R/W-0h
2
1
0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 19. PASSWORD Register Field Descriptions
Bit
Field
7-0
(1)
Type
PASSWORD[7:0]
R/W
Reset
Description (1)
0h
To write-access protected registers write 0xBAh followed by
0xBEh to the register. Both writes need to be consecutive.
To lock protected registers, write 0x00h.
Reading the PASSWORD register returns 0x00h if the protected
registers are locked for write access and 0x01h if they are
unlocked.
Protected registers can be read-accessed without writing to the PASSWORD register.
7.6.15 System Configuration (SYSTEM) Register (address = 0x11h) [reset = 0h]
Figure 26. SYSTEM Register
7
6
5
RESERVED
R-0h
4
3
2
EEPROG
R/W-0h
1
RESERVED
R/W-0h
0
MAP
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 20. SYSTEM Register Field Descriptions
30
Bit
Field
Type
Reset
Description
7-3
RESERVED
R
0h
N/A
2
EEPROG
R/W
0h
EEPROM programming bit. When set high, BYTE0 through BYTE7
settings are committed to EEPROM and become new power-up
default values.
To program the EEPROM, set this bit high and back low after 50
ms. Power must not be interrupted during EEPROM programming
to prevent loss of data.
1
RESERVED
R/W
0h
This bit should always be set to 0.
0
MAP
R/W
0h
Switch map selector bit:
0b = Common anode configuration
1b = Cathode-cathode-anode configuration
NOTE: See switch control section for details.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
7.6.16 EEPROM User Register, Byte0 (BYTE0) (address = 0x20h) [reset = 0h]
Figure 27. BYTE0 Register
7
6
5
4
3
2
1
0
BYTE0[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 21. BYTE0 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BYTE0[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7.6.17 EEPROM User Register, Byte1 (BYTE1) (address = 0x21h) [reset = 0h]
Figure 28. BYTE1 Register
7
6
5
4
3
2
1
0
BYTE1[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 22. BYTE1 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BYTE1[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
31
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
7.6.18 EEPROM User Register, Byte2 (BYTE2) (address = 0x22h) [reset = 0h]
Figure 29. BYTE2 Register
7
6
5
4
3
2
1
0
BYTE2[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 23. BYTE2 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BYTE2[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7.6.19 EEPROM User Register, Byte3 (BYTE3) (address = 0x23h) [reset = 0h]
Figure 30. BYTE3 Register
7
6
5
4
3
2
1
0
BYTE3[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 24. BYTE3 Register Field Descriptions
32
Bit
Field
Type
Reset
Description
7-0
BYTE3[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
7.6.20 EEPROM User Register, Byte4 (BYTE4) (address = 0x24h) [reset = 0h]
Figure 31. BYTE4 Register
7
6
5
4
3
2
1
0
BYTE4[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 25. BYTE4 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BYTE4[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7.6.21 EEPROM User Register, Byte5 (BYTE5) (address = 0x25h) [reset = 0h]
Figure 32. BYTE5 Register
7
6
5
4
3
2
1
0
BYTE5[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 26. BYTE5 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BYTE5[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
33
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
7.6.22 EEPROM User Register, Byte6 (BYTE6) (address = 0x26h) [reset = 0h]
Figure 33. BYTE6 Register
7
6
5
4
3
2
1
0
BYTE6[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 27. BYTE6 Register Field Descriptions
Bit
Field
Type
Reset
Description
7-0
BYTE6[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
7.6.23 EEPROM User Register, Byte7 (BYTE7) (address = 0x27h) [reset = 0h]
Figure 34. BYTE7 Register
7
6
5
4
3
2
1
0
BYTE7[7:0]
R/W-0h
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 28. BYTE7 Register Field Descriptions
34
Bit
Field
Type
Reset
Description
7-0
BYTE7[7:0]
R/W
0h
User programmable EEPROM. See Table 20 for detail on how to
program EEPROM.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
A DLPC2607 controller can be used with a DLP2000 DMD to provide a compact, reliable, high-efficiency display
solution for many different video display applications. DMDs are spatial light modulators which reflect incoming
light from an illumination source to one of two directions with the primary direction being into collection optics
within a projection lens. The projection lens sends the light to the destination needed for the application. Each
application is derived primarily from the optical architecture of the system and the format of the pixel data being
input into the DLPC2607.
In display applications using the DLP2000 DMD, the DLPA1000 provides necessary analog functions including
analog power supplies and an RGB LED driver to provide a robust and efficient display solution. Display
applications of interest include pico-projectors embedded in display devices like smart phones, tablets, cameras,
and camcorders. Other applications include wearable (near-eye) displays, battery-powered mobile accessory,
interactive display, low latency gaming displays, and digital signage.
8.2 Typical Application
BAT
Projector Module Electronics
±
+
A common application when using DLPA1000 with DLP2000 DMD and DLPC2607 controller is creating a picoprojector embedded in a handheld product. For example, a pico-projector may be embedded in a smart phone, a
tablet, a camera, or camcorder. The DLPC2607 in the pico-projector embedded module typically receives images
from a host processor within the product as shown in Figure 35. DLPA1000 provides power supply sequencing
and controls the LED currents as required by the application.
L5
2.3 V ± 5.5 V
DC
Supplies
On/Off
Connector
PWR_EN
MIC
SYSPWR
PROJ_ON
LCD
Panel
VDD
L6
RESETZ
FLASH,
SDRAM,
etc.
L2
Flash
INIT_DONE
CLRL
4
GPIO4
Parallel or
BT.656
28
24/16/8
SPI(4)
DLPC2607
DLPA1000
Analog
ASIC
RED
GREEN
BLUE
LED_SEL(2)
BIAS, RST, OFS
3
PWM_IN
RGB
Illumination
Optics
CMP_OUT
DATA
Keypad
L1
INTZ
PROJ_ON
Host
Processor
1.8 V
1V
VLED
PARKZ
RF
I/F
Dual
Reg.
I2C
Thermistor
1.8 V
1V
DDR
VIO
VCORE
CTRL
DATA
nHD/WVGA
WVGA
DDR DMD
GPIO5
DDR
Mobile SDRAM
Copyright © 2017, Texas Instruments Incorporated
Figure 35. Typical Standalone Projector System Block Diagram
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
35
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
Typical Application (continued)
8.2.1 Design Requirements
A pico-projector is created by using a DLP chipset comprised of a DMD such as the DLP2000, a controller such
as the DLPC2607, and a PMIC/LED driver such as the DLPA1000. The DLPA1000 provides the needed analog
functions for the projector, the DLPC2607 does the digital image processing, and the DMD is the display device
for producing the projected image. In addition to the three critical DLP components, other chips may be needed
for the full system design, such as the battery (SYSPWR), a regulated 1.8-V supply for the controller VIO, and a
regulated 1-V supply for the controller VCORE.
The DLPA1000 provides power to the illumination source for the DMD, typically from red, green, and blue LEDs.
These are often contained in three separate packages, but sometimes more than one color of LED die may be in
the same package to reduce the overall size of the pico-projector. The entire pico-projector can be turned on and
off by using a single signal called PROJ_ON. When PROJ_ON is high, the projector turns on and begins
displaying images. When PROJ_ON is set low, the projector turns off and draws just microamps of current on
SYSPWR. When PROJ_ON is set low, the 1.8-V and 1-V supplies can remain active to be used by other nonprojector sections of the product.
8.2.2 Detailed Design Procedure
The DLPA1000 contains a buck-boost regulator for the LEDs, boost regulators for the DMD rails, and internal
LDOs for logic state control and operation. Each regulator requires a few external components to operate,
referenced by their designators in Figure 36 and Figure 38, and all capacitors should maintain the recommended
values at expected operating temperatures and bias voltages.
36
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
Typical Application (continued)
From system power
VINA
TEST
AGND
V2V5
R1
100 k
C2
1 F
C1
2.2 F
AGND1
R2
1k
V6V
From host
C3
100 nF
PWM_IN
C4
1 F
From system power
VINL
To host
VINL
CMP_OUT
From light sensor
SENS1
From temperature sensor
SENS2
C6
1 F
L1
L1
From system power
PGNDL
VINR
C7
10 F
L2
2.2 H
PGNDL
L2
D6
VRST (±10 V)
L2
SWN
REF_VRST
C8
220 nF
VLED
R27
100 k
SWP
VLED
L1
10 H
DLPA1000
VLED
C9
10 F
C10
10 F
PGNDR
SW1
SW2
VBIAS (16 V)
VBIAS
SW3
C11
220 nF
SW4
SW5
VOFS (8.5 V)
VOFS
SW6
C12
220 nF
RLIM
RLIM
RGB LED
Assembly
R34
100 m
VIO
RLIM_K
From host
PROJ_ON
From host
LED_SEL0
From host
LED_SEL1
From host
VSPI
INTZ
R3
100 k
RESETZ
C5
0.1 F
From host
SPI_CSZ
From host
SPI_CLK
From host
SPI_DIN
To host
PWR_EN
SPI_DOUT
DGND
Copyright © 2017, Texas Instruments Incorporated
Figure 36. Schematic
8.2.2.1 VLED Buck-Boost
The VLED buck-boost provides the necessary voltages for the LED array capable of supporting both common
anode and cathode-cathode-anode RGB LEDs. Configurations for both packages are detailed in the RGB Strobe
Decoder section. Alternatively, a design could utilize an optical engine from an OEM that specializes in designing
optics for DLP projectors, which typically integrate the LEDs and DMD into a single module. Current sensing
through the LEDs is accomplished with a high-precision (0.1%) 100-mΩ sense resistor (R34) connecting RLIM to
GND, with a separate trace providing a Kelvin connection to RLIM_K directly from the pad of the sense resistor.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
37
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
Typical Application (continued)
The VLED buck-boost utilizes a single 2.2-µH inductor (L2) to generate the voltages for the LED array, bridging
the pins labeled L1 to the pins labeled L2. The buck-boost also requires a 1-µF input bypass capacitor (C6)
connecting VINL to GND, and two 10-µF output filter capacitors (C9 and C10) connecting VLED to GND. Ensure
the inductor can handle the expected operating currents and refer to Calculating Inductor Peak Current to
calculate the expected peak current for a design that can saturate the inductor's core.
8.2.2.1.1 Calculating Inductor Peak Current
To properly configure the DLPA1000 device, a 2.2-µH inductor (L2) must be connected between pins L1 and L2.
The peak current for the inductor in steady state operation can be calculated.
Equation 1 shows how to calculate the peak current I1 in step down mode operation and Equation 2 shows how
to calculate the peak current I2 in boost mode operation. VIN1 is the maximum input voltage VIN2 is the
minimum input voltage, f is the switching frequency (2.25 MHz) and L the inductor value (2.2 µH).
V
(V - V )
I
I1 = OUT + OUT IN 1 OUT
0.8
2 ´ VIN 1 ´ f ´ L
(1)
I2 =
VOUT ´ I OUT VIN 2 (VOUT - VIN 2 )
+
0.8 ´ VIN 2
2 ´ VOUT ´ f ´ L
(2)
The critical current value for selecting the right inductor is the higher value of I1 and I2. It also needs to be taken
into account that load transients and error conditions may cause higher inductor currents. This also needs to be
taken into account when selecting an appropriate inductor. Internally the switching current is limited to 2.2 A.
8.2.2.2 DMD Supplies
The PMIC also utilizes a single inductor (L1) to generate the low-current –10-V, 16-V, and 8.5-V supplies.
Connect the inductor from SWP to SWN, and use a Schottky diode (D6) to generate the –10 V by connecting the
cathode of the diode to the SWN side of the inductor and the anode of the diode to the load (VRST). Place a
220-nF filter cap (C8) from VRST to GND and bridge VRST to the feedback pin (REF_VRST) using a 100-kΩ
resistor (R27). Bypass VINR to GND using a 10-µF capacitor (C7), and ensure VBIAS and VOFS each have
dedicated 220-nF output filter capacitors (C11 and C12).
8.2.2.3 LDOs and Digital Logic
Ensure V2V5 has a 2.2-µF output capacitor (C1), and that V6V has a 100-nF output capacitor (C3). It is critical
that V2V5 externally connects to the TEST pin (R1), otherwise the PMIC will be unable to operate. UVLO for this
device is typically 2.3 V.
8.2.3 Application Curve
Figure 37. Power-Up Sequence: PROJ_ON Asserted
38
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
9 Power Supply Recommendations
The DLPA1000 is designed to operate from a 2.3-V to 6-V input voltage supply or battery. To avoid insufficient
supply current due to line drop, ringing due to trace inductance at the VIN terminal, or supply peak current
limitations, additional bulk capacitance may be required. Electrolytic or tantalum type capacitors can dampen
ringing often caused by ceramic input capacitors. The amount of bulk capacitance required should be evaluated
such that the input voltage can remain in specification long enough for a proper fast shutdown to occur for the
VOFS, VRST, and VBIAS supplies. The shutdown begins when the input voltage drops below the programmable
UVLO threshold such as when the external power supply or battery supply is suddenly removed from the system.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
39
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
10 Layout
10.1 Layout Guidelines
As for all switching power supplies, the layout is an important step in the design, especially at high peak currents
and high switching frequencies. If the layout is not carefully done, the regulators could show stability problems as
well as EMI problems. Therefore, use wide and short traces for the main current path and for the power ground
tracks. Input capacitors, output capacitors, and inductors should be placed as close as possible to the IC.
40
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
10.2 Layout Example
Place L2 (VLED)
as close to the IC
as possible. Route
on top level and
avoid vias. Max
current is 2 A.
C6 and C7
should be placed
close to the IC
(supply caps).
Keep traces
separated and
star-connect to
system power.
Place L1 as
close to the IC as
possible. Max
trace current is
200 mA.
Keep trace from
R27 to pin [B6]
shielded from
[A5]-L1 trace as
much as possible
to avoid noise
coupling.
Place C11, and
C12, (VBIAS,
VOFS) close to
the IC. Average
current is <5 mA.
Place C9 and
C10 (VLED) as
close to the IC as
possible. Use
wide metal (1 A
current) and
avoid vias.
Place C3 (V6V)
close to IC and
route on top metal.
This is low-current
trace.
Place D6 close to
L1 and C8 close
to D6.
Place C1, as
close to the IC as
possible. This is
an internal
reference pin and
needs to be
shielded from
noise.
Keep trace [F5]
R34 separated from
trace [F6, F7] - R34
and connect them
directly at R34. R34
is the LED sense
resistor.
Place C2 (supply
cap) as close to
the IC as possible.
Star-connect to
system power.
Figure 38. Layout
Table 29. Layout Components
LABEL
DESCRIPTION
C1
V2V5 output filter cap
C2
VINA input cap
C3
V6V output filter cap
C6
VINL input cap
C7
VINR input cap
C8
VRST output filter cap
C9
VLED output filter cap
C10
VLED output filter cap
C11
VBIAS output filter cap
C12
VOFS output filter cap
D6
VRST rectifying diode
L1
DMD supply inductor
L2
VLED buck-boost inductor
R27
100k VRST feedback resistor
R34
100m RLIM sense resistor
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
41
DLPA1000
SLVSDP7 – FEBRUARY 2017
www.ti.com
11 Device and Documentation Support
11.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
Pico, E2E are trademarks of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
42
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
DLPA1000
www.ti.com
SLVSDP7 – FEBRUARY 2017
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Product Folder Links: DLPA1000
43
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jun-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DLPA1000YFFR
PREVIEW
DSBGA
YFF
49
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-10 to 85
100
DLPA1000YFFT
PREVIEW
DSBGA
YFF
49
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-10 to 85
100
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Jun-2017
Addendum-Page 2
D: Max = 3.184 mm, Min =3.124 mm
E: Max = 2.988 mm, Min =2.928 mm
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated