Sharp LRS1341 Stacked chip 16m flash memory and 2m sram Datasheet

LRS1341/LRS1342
Stacked Chip
16M Flash Memory and 2M SRAM
Data Sheet
FEATURES
– Thirty-one 32K-word main blocks
– Top/Bottom boot location versions
– Extended cycling capability
– 100,000 block erase cycles
– Enhanced automated suspend options
– Word write suspend to read
– Block erase suspend to word write
– Block erase suspend to read
• Flash Memory and SRAM
• Stacked Die Chip Scale Package
• 72-ball CSP (FBGA072-P-0811) plastic package
• Power supply: 2.7 V to 3.6 V
• Operating temperature: -25°C to +85°C
• Flash Memory
– Access time (MAX.): 100 ns
– Operating current (MAX.):
The current for F-VCC pin
– Read: 25 mA (tCYCLE = 200 ns)
– Word write: 17 mA
– Block erase: 17 mA
– Deep power down current (the current for
F-VCC pin): 10 µA (MAX. F-CE ≥ F-VCC - 0.2 V,
F-RP ≤-0.2 V, F-VPP ≤0.2 V)
– Optimized array blocking architecture
– Two 4K-word boot blocks
– Six 4K-word parameter blocks
• SRAM
– Access time (MAX.): 85 ns
– Operating current (MAX.):
– 45 mA
– 8 mA (tRC, tWC = 1 µs)
– Standby current: 45 µA (MAX.)
– Data retention current: 35 µA (MAX.)
DESCRIPTION
The LRS1341/LRS1342 is a combination memory
organized as 1,048,576 × 16-bit flash memory and
131,072 × 16-bit static RAM in one package.
PIN CONFIGURATION
72-BALL FBGA
TOP VIEW
INDEX
1
2
3
4
5
6
7
8
9
10
11
12
NC
NC
NC
A11
A15
A14
A13
A12
GND
NC
NC
NC
B
A16
A8
A10
A9
DQ15 S-WE DQ14
DQ7
C
F-WE
F-RY/
BY
T1
T3
DQ13
DQ5
D
GND
F-RP
T2
T4
DQ12 S-CE2 S-VCC F-VCC
E
F-WP
F-VPP F-A19 DQ11
F
S-LB S-UB S-OE
NC
G
F-A18
F-A17
A7
NC
A5
A4
NC
NC
A
H
NC
NC
T5
DQ6
DQ4
DQ10 DQ2
DQ3
DQ9
DQ8
DQ0
DQ1
A6
A3
A2
A1
S-CE1
A0
F-CE
GND F-OE
NC
NOTE: Two NC pins at the corner are connected.
LRS1342-1
Figure 1. LRS1341/LRS1342 Pin Configuration
Data Sheet
1
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
F-VCC
F-VPP
F-A17 to
F-A19
F-RY/BY
A0 to A16
GND
F-CE
F-OE
16M (x16) BIT
FLASH MEMORY
F-WE
F-RP
F-WP
DQ0 to
DQ15
S-CE1
S-CE2
S-OE
2M (x16) BIT
SRAM
S-WE
S-LB
S-UB
S-VCC
LRS1342-2
Figure 2. LRS1341/LRS1342 Block Diagram
2
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
Table 1. Pin Descriptions
PIN
A0 to A16
TYPE
Address Inputs (Common)
Input
Address Inputs (Flash)
Input
Chip Enable Input (Flash)
Input
Chip Enable Inputs (SRAM)
Input
F-WE
Write Enable Input (Flash)
Input
S-WE
Write Enable Input (SRAM)
Input
F-OE
Output Enable Input (Flash)
Input
S-OE
Output Enable Input (SRAM)
Input
S-LB
SRAM Byte Enable Input (DQ0 to DQ7)
Input
S-UB
SRAM Byte Enable Input (DQ8 to DQ15)
Input
F-RP
Reset/Power Down (Flash)
Block erase and Word Write: VIH or VHH
Read: VIH or VHH
Reset/Power Down: VIL
Input
F-WP
Write Protect (Flash)
Two Boot Blocks Locked: VIL (with F-RP = VHH
Erase of Write can operate to all blocks)
Input
F-RY/BY
Ready/Busy (Flash)
During an Erase or Write operation: VOL
Block Erase and Word Write Suspend: HIGH-Z
Deep Power Down: VOH
Output
F-A17 to F-A19
F-CE
S-CE1, S-CE2
DQ0 to DQ15
Data Input/Outputs (Common)
Input/Output
F-VCC
Power Supply (Flash)
Power
S-VCC
Power Supply (SRAM)
Power
F-VPP
Write, Erase Power Supply (Flash)
Block Erase and Word Write: F-VPP = VPPLK
All Blocks Locked: F-VPP < VPPLK
Power
GND
Ground (Common)
Power
NC
T1 to T5
Data Sheet
DESCRIPTION
No Connection
—
Test Pins (Should be Open)
—
3
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
Table 2. Truth Table1
FLASH
SRAM
F-CE
F-RP
F-OE
F-WE
S-CE1
S-CE2
S-OE
S-WE
DQ8 DQ15
Standby
L
H
L
H
Standby
L
H
H
H
Write
Standby
L
H
H
L
X
X
Read
H
H
X
X
L
H
L
H
Output
Disable
H
H
X
X
L
H
H
H
X
X
HIGH-Z
H
H
X
X
L
H
X
X
H
H
HIGH-Z
Write
H
H
X
X
L
H
L
L
Read
X
L
X
X
L
H
L
H
Reset/Power Down
Output
Disable
X
L
X
X
L
H
H
H
X
X
HIGH-Z
X
L
X
X
L
H
X
X
H
H
HIGH-Z
Write
X
L
X
X
L
H
Standby
Standby
H
H
X
X
Reset/Power Down
Standby
X
L
X
X
See Note 4
NOTES:
1. L = VIL, H = VIH, X = H or L. Refer to DC Characteristics.
2. Refer to the ‘Flash Memory Command Definition’ section for valid
DIN during a write operation.
3. F-WP set to VIL or VIH.
4. SRAM standby mode. See Table 2a.
X
X
DQ0 DQ-7
Output Disable
Standby
X
S-UB
Read
See Note 4
X
S-LB
L
L
X
X
X
X
See Note 4
2, 3
3
DIN
2, 3, 5, 6
See Note 7
See Note 7
See Note 4
HIGH-Z
3
HIGH-Z
3
5. Command writes involving block erase or word write are reliably
executed when F-VPP = VPPH and F-VCC = 2.7 V to 3.6 V. Block
erase or word write with VIH < RP < VHH produce spurious results
and should not be attempted.
6. Never hold F-OE LOW and F-WE LOW at the same time.
7. S-LB, S-UB control mode. See Table 2b.
Table 2b.
PINS
S-CE1
S-CE2
S-LB
S-UB
H
X
X
X
Standby
(SRAM)
DOUT
HIGH-Z
See Note 7
Table 2a.
MODE
NOTES
X
L
X
X
X
X
H
H
MODE
(SRAM)
Read/Write
PINS
S-LB
S-UB
DQ0 - DQ7
DQ8 - DQ15
L
L
DOUT/DIN
DOUT/DIN
L
H
DOUT/DIN
HIGH-Z
H
L
HIGH-Z
DOUT/DIN
Table 3. Command Definition for Flash Memory1
COMMAND
Read Array/Reset
FIRST BUS CYCLE
BUS CYCLES
REQUIRED
OPERATION
1
Write
2
ADDRESS
3
SECOND BUS CYCLE
DATA
XA
FFH
3
OPERATION2
ADDRESS3
DATA3
NOTES
Read Identifier Codes
≥2
Write
XA
90H
Read
IA
ID
Read Status Register
2
Write
XA
70H
Read
XA
SRD
Clear Status Register
1
Write
XA
50H
Block Erase
2
Write
BA
20H
Write
BA
D0H
5
Word Write
2
Write
WA
40H or 10H
Write
WA
WD
5
Block Erase and Word
Write Suspend
1
Write
XA
B0H
5
Block Erase and Word
Write Resume
1
Write
XA
D0H
5
NOTES:
1. Commands other than those shown in table are reserved by
SHARP for future device implementations and should not be used.
2. BUS operations are defined in Table 2.
3. XA = Any valid address within the device;
IA = Identifier code address;
BA = Address within the block being erased;
4
4
WA = Address of memory location to be written;
SRD = Data read from status register, see Table 6;
WD = Data to be written at location WA. Data is latched on the
rising edge of F-WE or F-CE (whichever goes high first);
ID = Data read from identifier codes.
4. See Table 4 for Identifier Codes.
5. See Table 5 for Write Protection Alternatives.
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
Table 4. Identifier Codes
CODES
ADDRESS
(A0 - A18)
LRS1341 DATA
(DQ0 - DQ7)
LRS1342 DATA
(DQ0 - DQ7)
Manufacture Code
00000H
B0H
B0H
Device Code
00001H
48H
49H
Table 5. Write Protection Alternatives
OPERATION
Block Erase or
Word Write
F-VPP
F-RP
F-WP
VIL
X
X
All blocks locked
VIL
X
All blocks locked
VHH
X
All blocks unlocked
VIH
VIL
Two boot blocks locked
VIH
VIH
All blocks unlocked
> VPPLK
EFFECT
Table 6. Status Register Definition
WSMS
ESS
ES
WWS
VPPS
WWSS
DPS
R
7
6
5
4
3
2
1
0
SR.7 = Write State Machine Status (WSMS)
1 = Ready
0 = Busy
SR.6 = Erase Suspend Status (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = Erase Status (ES)
1 = Error in Block Erasure
0 = Successful Block Erase
SR.4 = Word Write Status (WWS)
1 = Error in Word Write
0 = Successful Word Write
NOTES:
1. Check RY/BY or SR.7 to determine block erase or word write
completion. SR.6 - SR.0 are invalid while SR.7 = 0.
2. If both SR.5 and SR.4 are ‘1’s after a block erase attempt, an
improper command sequence was entered.
3. SR.3 does not provide a continuous indication of F-VPP level. The
WSM interrogates and indicates the F-VPP level only after Block
Erase or Word Write command sequences. SR.3 is not guaranteed
to report accurate feedback only when F-VPP ≠ VPPH1, VPPH2.
4. The WSM interrogates the F-WP and F-RP only after Block Erase
or Word Write command sequences. It informs the system,
depending on the attempted operation, if the F-WP is not VIH or
F-RP is not VHH.
5. SR.0 is reserved for future use and should be masked out when
polling the status register.
SR.3 = VPP Status (VPPS)
1 = F-VPP LOW Detect, Operation Abort
0 = F-VPP Okay
SR.2 = Word Write Suspend Status (WWSS)
1 = Word Write Suspended
0 = Word Write in Progress/Completed
SR.1 = Device Protect Status (DPS)
1 = F-WP and/or F-RP Lock Detected,
Operation Abort
0 = Unlock
SR.0 = Reserved for future enhancements (R)
Data Sheet
5
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
MEMORY MAPS
[A0 - A19]
FFFFF
F8000
F7FFF
F0000
EFFFF
E8000
E7FFF
E0000
DFFFF
D8000
D7FFF
D0000
CFFFF
C8000
C7FFF
C0000
BFFFF
B8000
B7FFF
B0000
AFFFF
A8000
A7FFF
A0000
9FFFF
98000
97FFF
90000
8FFFF
88000
87FFF
80000
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
07000
06FFF
06000
05FFF
05000
04FFF
04000
03FFF
03000
02FFF
02000
01FFF
01000
00FFF
00000
32K-WORD MAIN BLOCK
30
32K-WORD MAIN BLOCK
29
32K-WORD MAIN BLOCK
28
32K-WORD MAIN BLOCK
27
32K-WORD MAIN BLOCK
26
32K-WORD MAIN BLOCK
25
32K-WORD MAIN BLOCK
24
32K-WORD MAIN BLOCK
23
32K-WORD MAIN BLOCK
22
32K-WORD MAIN BLOCK
21
32K-WORD MAIN BLOCK
20
32K-WORD MAIN BLOCK
19
32K-WORD MAIN BLOCK
18
32K-WORD MAIN BLOCK
17
32K-WORD MAIN BLOCK
16
32K-WORD MAIN BLOCK
15
32K-WORD MAIN BLOCK
14
32K-WORD MAIN BLOCK
13
32K-WORD MAIN BLOCK
12
32K-WORD MAIN BLOCK
11
32K-WORD MAIN BLOCK
10
32K-WORD MAIN BLOCK
9
32K-WORD MAIN BLOCK
8
32K-WORD MAIN BLOCK
7
32K-WORD MAIN BLOCK
6
32K-WORD MAIN BLOCK
5
32K-WORD MAIN BLOCK
4
32K-WORD MAIN BLOCK
3
32K-WORD MAIN BLOCK
2
32K-WORD MAIN BLOCK
1
32K-WORD MAIN BLOCK
0
4K-WORD PARAMETER BOOT BLOCK 5
4K-WORD PARAMETER BOOT BLOCK 4
4K-WORD PARAMETER BOOT BLOCK 3
4K-WORD PARAMETER BOOT BLOCK 2
4K-WORD PARAMETER BOOT BLOCK 1
4K-WORD PARAMETER BOOT BLOCK 0
4K-WORD BOOT BLOCK
1
4K-WORD BOOT BLOCK
0
F8000
F7FFF
F0000
EFFFF
E8000
E7FFF
E0000
DFFFF
D8000
D7FFF
D0000
CFFFF
C8000
C7FFF
C0000
BFFFF
B8000
B7FFF
B0000
AFFFF
A8000
A7FFF
A0000
9FFFF
98000
97FFF
90000
8FFFF
88000
87FFF
80000
7FFFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
LRS1342-3
Figure 3. Bottom Boot for Flash Memory
TOP BOOT
4K-WORD BOOT BLOCK
0
4K-WORD BOOT BLOCK
1
4K-WORD PARAMETER BOOT BLOCK
0
4K-WORD PARAMETER BOOT BLOCK
1
4K-WORD PARAMETER BOOT BLOCK
2
4K-WORD PARAMETER BOOT BLOCK
4K-WORD PARAMETER BOOT BLOCK
4K-WORD PARAMETER BOOT BLOCK
3
4
5
32K-WORD MAIN BLOCK
0
32K-WORD MAIN BLOCK
1
32K-WORD MAIN BLOCK
2
32K-WORD MAIN BLOCK
3
32K-WORD MAIN BLOCK
4
32K-WORD MAIN BLOCK
5
32K-WORD MAIN BLOCK
6
32K-WORD MAIN BLOCK
7
32K-WORD MAIN BLOCK
8
32K-WORD MAIN BLOCK
9
32K-WORD MAIN BLOCK
10
32K-WORD MAIN BLOCK
11
58000
57FFF
50000
4FFFF
32K-WORD MAIN BLOCK
12
32K-WORD MAIN BLOCK
13
48000
47FFF
40000
3FFFF
32K-WORD MAIN BLOCK
14
32K-WORD MAIN BLOCK
15
32K-WORD MAIN BLOCK
16
32K-WORD MAIN BLOCK
17
32K-WORD MAIN BLOCK
18
32K-WORD MAIN BLOCK
19
32K-WORD MAIN BLOCK
20
32K-WORD MAIN BLOCK
21
32K-WORD MAIN BLOCK
22
32K-WORD MAIN BLOCK
23
32K-WORD MAIN BLOCK
24
32K-WORD MAIN BLOCK
25
32K-WORD MAIN BLOCK
26
32K-WORD MAIN BLOCK
27
32K-WORD MAIN BLOCK
28
32K-WORD MAIN BLOCK
29
32K-WORD MAIN BLOCK
30
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
07000
06FFF
06000
05FFF
05000
04FFF
04000
03FFF
03000
02FFF
02000
01FFF
01000
00FFF
00000
BOTTOM BOOT
6
[A0 - A19]
FFFFF
LRS1342-13
Figure 4. Top Boot for Flash Memory
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATINGS
UNIT
NOTES
Supply voltage
VCC
-0.2 to +3.9
V
1, 2
Input voltage
VIN
-0.2 to VCC +0.3
V
1, 3, 4
Operating temperature
TOPR
-25 to +85
°C
Storage temperature
TSTG
-55 to +125
°C
F-VPP voltage
F-VPP
-0.2 to +14.0
V
1, 4, 5
F-RP voltage
F-RP
-0.5 to +14.0
V
1, 4, 5
NOTES:
1. The maximum applicable voltage on any pins with respect to GND.
2. Except F-VPP.
3. Except F-RP.
4. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
5. +14.0 V overshoot is allowed when the pulse width is less than 20 ns.
RECOMMENDED DC OPERATING CONDITIONS
TA = -25°C to +85°C
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
VCC
2.7
3.0
3.6
V
VIH
2.2
VCC + 0.2
V
1
VIL
-0.2
0.6
V
2
VHH
11.4
12.6
V
3
Input voltage
NOTES
NOTES:
1. VCC is the lower one of S-VCC and F-VCC.
2. -2.0 V undershoot is allowed when the pulse width is less than 20 ns.
3. This voltage is applicable to F-RP pin only.
PIN CAPACITANCE
TA = 25°C, f = 1 MHz
PARAMETER
SYMBOL
CONDITION
Input capacitance*
CIN
I/O capacitance*
CI/O
MIN.
TYP.
MAX.
UNIT
VIN = 0 V
20
pF
VI/O = 0 V
22
pF
NOTE: *Sampled by not 100% tested.
Data Sheet
7
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
DC CHARACTERISTICS
TA = -25°C to + 85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
CONDITION
MIN.
TYP.1
MAX.
UNIT
Input leakage current
ILI
VIN = VCC or GND
-1.5
+1.5
µA
Output leakage current
ILO
VOUT = VCC or GND
-1.5
+1.5
µA
Standby Current
Deep Power-Down Current
F-VCC
F-VPP
Read Current
ICCS
ICCD
ICCR
Word Write Current
ICCW
Block Erase Current
ICCE
F-CE = F-RP = F-VCC ± 0.2 V
F-WP = F-VCC ± 0.2 V
or F-GND ± 0.2 V
25
50
µA
F-CE = F-RP = VIH, F-WP = VIH or VIL
0.2
2
mA
5
10
µA
CMOS input, F-CE = F-GND,
f = 5 MHz, IOUT = 0 mA
25
mA
3, 4
TTL input, F-CE = F-GND,
f = 5 MHz, IOUT = 0 mA
30
mA
3, 4
F-RP = F-GND ± 0.2 V,
IOUT (F-RY/BY) = 0 mA
F-VPP = 2.7 V to 3.6 V
17
mA
F-VPP = 11.4 V to 12.6 V
12
mA
F-VPP = 2.7 V to 3.6 V
17
mA
F-VPP = 11.4 V to 12.6 V
12
mA
F-CE = VIH
6
mA
Word Write Block Erase
Suspend Current
ICCWS
ICCES
Standby or Read Current
IPPS
IPPR
F-VPP = F-VCC
±2
±15
µA
F-VPP > F-VCC
10
200
µA
Deep Power-Down Current
IPPD
F-RP = F-GND ± 0.2 V
0.1
5
µA
Word Write Current
IPPW
F-VPP = 2.7 V to 3.6 V
12
Block Erase Current
IPPE
Word Write or Block Erase
Suspend Current
Standby Current
S-VCC
IPPWS
IPPES
F-VPP = 11.4 V to 12.6 V
F-VPP = 2.7 V to 3.6 V
8
F-VPP = 11.4 V to 12.6 V
F-VPP = VPPH
10
40
mA
30
mA
25
mA
20
mA
200
µA
ISB
S-CE1, S-CE2 ≥ S-VCC - 0.2 V
or S-CE2 ≤0.2 V
45
µA
ISB1
S-CE1 = VIH or S-CE2 = VIL
3
mA
ICC1
S-CE1 = VIL, S-CE2 = VIH, VIN = VIL or
VIH, tCYCLE = MIN., II/O = 0 mA
45
mA
ICC2
S-CE1 = 0.2 V, S-CE2 = S-VCC - 0.2 V,
VIN = S-VCC - 0.2 V, or 0.2 V
tCYCLE = 1 µs, II/O = 0 mA
8
mA
V
Operation Current
NOTES
2
Input LOW Voltage
VIL
-0.2
0.6
Input HIGH Voltage
VIH
2.2
VCC + 0.2
V
Output LOW Voltage
VOL
IOL = 0.5 mA
0.4
V
2
IOH = -0.5 mA
V
2
1.5
V
5
2.7
3.6
V
VPPH2
11.4
12.6
V
VLKO
1.5
12.6
V
Output HIGH Voltage (CMOS)
VOH1
F-VPP Lockout during Normal Operations
VPPLK
F-VPP Word Write or Block Erase
Operations
VPPH1
F-VCC Lockout Voltage
F-RP Unlock Voltage
VHH
Unavailable F-WP
NOTES:
1. Reference values at VCC = 3.0 V and TA = +25°C.
2. Includes F-RY/BY.
3. Automatic Power Savings (APS) for Flash Memory reduces typical ICCR to 3 mA at 2.7 VCC in static operation.
4. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs
are either VIL or VIH.
8
2.2
11.4
V
6
5. Block erases and word writes are inhibited when F-VPP ≤VPPLK and
not guaranteed in the range between VPPLK (MAX.) and VPPH
(MIN.), and above VPPH (MAX.).
6. F-RP connection to a VHH supply is allowed for a maximum cumulative period of 80 hours.
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
FLASH MEMORY AC CHARACTERISTICS
AC Test Conditions
PARAMETER
Input pulse level
CONDITION
0 V to 2.7 V
Input rise and fall time
10 ns
Input and Output timing reference level
1.35 V
Output load
1TTL + CL (30 pF)
Read Cycle
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
MIN.
Read Cycle Time
tAVAV
100
Address to Output Delay
tAVQV
100
ns
F-CE to Output Delay*
tELQV
100
ns
F-RP HIGH to Output Delay
tPHQV
10
µs
F-OE to Output Delay*
tGLQV
45
ns
F-CE to Output in LOW-Z
tELQX
F-CE HIGH to Output in HIGH-Z
tEHQZ
F-OE to Output in LOW Z
tGLQX
F-OE HIGH to Output in HIGH-Z
tGHQZ
Output Hold from Address, F-CE or F-OE change,
whichever occurs first
tOH
MAX.
UNIT
ns
0
ns
45
0
ns
ns
20
0
ns
ns
NOTE: *F-OE may be delayed up to tELQV - tGLQV after the falling edge of F-CE without impact on tELQV.
Data Sheet
9
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
Write Cycle (F-WE Controlled)1
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
MIN.
Write Cycle Time
tAVAV
100
ns
F-RP HIGH Recovery to F-WE going to LOW
tPHWL
10
µs
F-CE Setup to F-WE going LOW
tELWL
0
ns
F-WE Pulse Width
tWLWH
50
ns
F-RP VHH Setup to F-WE going HIGH
tPHHWH
100
ns
F-WP VIH Setup to F-WE going HIGH
tSHWH
100
ns
F-VPP Setup to F-WE going HIGH
tVPWH
100
ns
tAVWH
50
ns
Data Setup to F-WE going HIGH
tDVWH
50
ns
Data Hold from F-WE HIGH
tWHDX
0
ns
Address Hold from F-WE HIGH
tWHAX
0
ns
F-CE Hold from F-WE HIGH
tWHEH
0
ns
F-WE Pulse Width HIGH
tWHWL
30
ns
F-WE HIGH to F-RY/BY going LOW
tWHRL
Write Recovery before Read
tWHGL
0
ns
F-VPP Hold from Valid SRD, F-RY/BY HIGH-Z
tQVVL
0
ns
F-RP VHH Hold from Valid SRD, F-RY/BY HIGH-Z
tQVPH
0
ns
F-WP VIH Hold from Valid SRD, F-RY/BY HIGH
tQVSL
0
ns
Address Setup to F-WE going HIGH
2
2
MAX.
100
UNIT
ns
NOTES:
1. Read timing characteristics during block erase and word write operations are the same as
during read-only operations. Refer to AC Characteristics for Read Cycle.
2. Refer to the ‘Flash Memory Command Definition’ section for valid AIN and DIN for block erase or word write.
10
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
Write Cycle (F-CE Controlled)1
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Write Cycle Time
tAVAV
100
ns
F-RP HIGH Recovery to F-CE going to LOW
tPHEL
10
µs
F-WE Setup to F-CE going LOW
tWLEL
0
ns
F-CE Pulse Width
tELEH
70
ns
F-RP VHH Setup to F-CE going HIGH
tPHEH
100
ns
F-WP VIH Setup to F-CE going HIGH
tSHEH
100
ns
F-VPP Setup to F-CE going HIGH
tVPEH
100
ns
Address Setup to F-CE going HIGH2
tAVEH
50
ns
Data Setup to F-CE going HIGH2
tDVEH
50
ns
Data Hold from F-CE HIGH
tEHDX
0
ns
Address Hold from F-CE HIGH
tEHAX
0
ns
F-WE Hold from F-CE HIGH
tEHWH
0
ns
F-CE Pulse Width HIGH
tEHEL
25
ns
F-CE HIGH to F-RY/BY going LOW
tEHRL
100
ns
Write Recovery before Read
tEHGL
0
ns
F-VPP Hold from Valid SRD, F-RY/BY HIGH-Z
tQVVL
0
ns
F-RP VHH Hold from Valid SRD, F-RY/BY HIGH-Z
tQVPH
0
ns
F-WP VIH Hold from Valid SRD, F-RY/BY HIGH
tQVSL
0
ns
NOTES:
1. Read timing characteristics during block erase and word write operations are the same as
during read-only operations. Refer to AC Characteristics for Read Cycle.
2. Refer to the ‘Flash Memory Command Definition’ section for valid AIN and DIN for block erase or word write.
Block Erase and Word Write Performance
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
SYMBOL
tWHQV1
tEHQV1
PARAMETER
VPP = 2.7 V to 3.6 V
MIN.
1
TYP.
MAX.
VPP = 11.4 V to 12.6 V
MIN.
TYP.1
MAX.
UNIT
NOTES
Word Write Time 32K-word Block
55
15
µs
2
Word Write Time 4K-word Block
60
30
µs
2
Block Write Time 32K-word Block
1.8
0.6
s
2
Block Write Time 4K-word Block
0.3
0.2
s
2
Block Erase Time 32K-word Block
1.2
0.7
s
2
Block Erase Time 4K-word Bock
0.5
0.5
s
2
tWHRZ1
tEHRZ1
Word Write Suspend Latency Time to Read
7.5
8.6
6.5
7.5
µs
tWHRZ2
tEHRZ2
Erase Suspend Latency Time to Read
19.3
23.6
11.8
15
µs
tWHQV2
tEHQV2
NOTES:
1. Reference values at TA = +25°C and VCC = 3.0 V, VPP = 3.0 V.
2. Excludes system-level overhead.
Data Sheet
11
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
FLASH MEMORY AC CHARACTERISTICS TIMING DIAGRAMS
Standby
Device
Address Selection
Data Valid
Address Stable
ADDRESS
tAVAV
F-CE
tEHQZ
F-OE
tGHQZ
tGLQV
F-WE
tELQV
tGLQX
tOH
tELQX
DQ
HIGH Z
HIGH Z
Valid Output
tAVQV
F-VCC
tPHQV
F-RP
LRS1342-4
Figure 5. Read Cycle Timing Diagram
12
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
1
ADDRESS
LRS1341/LRS1342
2
3
AIN
AIN
tAVAV
4
tAVWH
5
6
tWHAX
tWHWL
F-WE
tWLWH
tDVWH
tWHGL
F-OE
F-CE
tELWL
tWHEH
tWHDX
HIGH-Z
DQ
Data
Valid
SRD
tWHQV1, 2, 3, 4
DIN
DIN
DIN
tPHWL
tEHRL
F-RY/BY
tSHWH
tQVSL
tPHHWH
tQVPH
F-WP
VHH
VIH
F-RP
VIL
tVPWH
tQVVL
VPPH
F-VPP
VPPLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or word write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
LRS1342-5
Figure 6. Write Cycle Timing Diagram (F-WE Controlled)
Data Sheet
13
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
1
ADDRESS
2
3
AIN
AIN
tAVAV
4
5
6
tAVEH
tEHAX
F-WE
tWLEL
tEHWH
tEHGL
F-OE
tEHEL
tEHQV1, 2, 3, 4
F-CE
tELEH
tDVEH
tEHDX
DQ
HIGH-Z
Data
Valid
SRD
DIN
DIN
DIN
tPHWL
tEHRL
F-RY/BY
tSHEH
tQVSL
tPHHEH
tQVPH
F-WP
VHH
F-RP
VIH
VIL
tVPEH
tQVVL
VPPH
F-VPP
VPPLK
VIL
NOTES:
1. VCC power-up and standby.
2. Write block erase or word write setup.
3. Write block erase confirm or valid address and data.
4. Automated erase or program delay.
5. Read status register data.
6. Write Read Array command.
LRS1342-6
Figure 7. Write Cycle Timing Diagram (F-CE Controlled)
14
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
RESET OPERATIONS
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
MIN.
F-RP Pulse LOW Time (if F-RP is tied to VCC, this
specification is not applicable).
tPLPH
100
F-RP LOW to Reset during Block Erase or Word Write
tPLRZ
F-VCC 2.7 V to F-RP HIGH
tVPH
MAX.
UNIT
NOTES
ns
23.6
100
µs
1, 2
ns
3
NOTES:
1. If F-RP is asserted while a block erase or word write operation is not executing,
the reset will complete with 100 ns.
2. A reset time tPHQV is required from the later of F-RY/BY going HIGH-Z, or F-RP going HIGH until outputs are valid.
3. When the device power-up, holding F-RP LOW minimum 100 ns is required after VCC has been
in predefined range and also has been stable there.
HIGH Z
F-RY/BY (R)
VOL
F-RP (P)
VIH
VIL
tPLPH
A. Reset During Read Array Mode
HIGH Z
F-RY/BY (R)
VOL
tPLRZ
F-RP (P)
VIH
VIL
tPLPH
B. Reset During Block Erase or Word Write
2.7 V
F-VCC
VIL
tVPH
F-RP (P)
VIH
VIL
C. F-RP Rising Timing
LRS1342-7
Figure 8. AC Waveform for Reset Operation
Data Sheet
15
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
SRAM AC ELECTRICAL CHARACTERISTICS
AC Test Conditions
PARAMETER
CONDITION
Input Pulse Level
0.4 V to 2.7 V
Input Rise and Fall Time
5 ns
Input and Output Timing Reference Level
1.5 V
1TTL + CL (30 pF)
Output Load*
NOTE: *Including scope and jig capacitance.
Read Cycle
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
MIN.
tRC
85
Read Cycle Time
UNIT
ns
tAA
85
ns
S-CE1
tACE1
85
ns
S-CE2
Address Access Time
Chip Enable Access Time
MAX.
tACE2
85
ns
Byte Enable Access Time
tBE
85
ns
Output Enable to Output Valid
tOE
45
ns
Output hold from address change
S-CE1
S-CE1, S-CE2 LOW to Output Active*
tOH
10
ns
tLZ1
10
ns
tLZ2
10
ns
S-OE LOW to Output Active*
tOLZ
10
ns
S-UB or S-LB LOW to Output in HIGH Impedance*
tBLZ
10
ns
S-CE1
tHZ1
0
25
ns
S-CE2
tHZ2
0
25
ns
S-OE HIGH to Output in HIGH Impedance*
tOHZ
0
25
ns
S-UB or S-LB HIGH to Output in HIGH Impedance*
tBHZ
0
25
ns
S-CE2
S-CE1, S-CE2 HIGH to Output in HIGH Impedance*
NOTE: *Active output to HIGH impedance and HIGH impedance to output active
tests specified for a ±200 mV transition from steady state levels into the test load.
Write Cycle
TA = -25°C to +85°C, VCC = 2.7 V to 3.6 V
PARAMETER
SYMBOL
MIN.
MAX.
Write Cycle Time
tWC
85
ns
Chip Enable to End of Write
tCW
75
ns
Address Valid to End of Write
tAW
75
ns
Byte Enable to End of Write
tBW
75
ns
Address Setup Time
tAS
0
ns
Write Pulse Width
tWP
65
ns
Write Recovery Time
tWR
0
ns
Input Data Setup Time
tDW
35
ns
Input Data Hold Time
tDH
0
ns
S-WE HIGH to Output Active*
tOW
5
ns
S-WE LOW to Output in HIGH Impedance*
tWZ
0
25
UNIT
ns
NOTE: *Active output to HIGH impedance and HIGH impedance to output active
tests specified for a ±200 mV transition from steady state levels into the test load.
16
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
SRAM AC CHARACTERISTICS TIMING DIAGRAMS
tRC
ADDRESS
tAA
tACE1, 2
S-CE1
tLZ
tHZ
S-CE2
tBE
tHZ
S-UB, S-LB
tBLZ
tBHZ
tOE
S-OE
tOLZ
DOUT
tOHZ
Data Valid
tOH
NOTE: S-WE is HIGH for Read Cycle.
LRS1342-8
Figure 9. Read Cycle Timing Diagram
Data Sheet
17
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
tWC
ADDRESS
tAW
tCW
(NOTE 2)
S-CE1
tWR
S-CE2
tBW
(NOTE 3)
S-UB, S-LB
tAS
tWP
(NOTE 4)
(NOTE 7)
tWR
(NOTE 5)
S-WE
tWZ
tOW
(NOTE 8)
DOUT
tDW
tDH
(NOTE 6)
Data Valid
DIN
NOTES:
1. A write occurs during the overlap of a LOW S-CE1, a HIGH S-CE2 and a LOW S-WE.
A write begins at the latest transition among S-CE1 going LOW, S-CE2 going HIGH
and S-WE going LOW. A write ends at the earliest transition among S-CE1 going HIGH,
S-CE2 going LOW and S-WE going HIGH. tWP is measured from the beginning of
write to the end of write.
2. tCW is measured from the later of S-CE1 going LOW or S-CE2 going HIGH to the end
of write.
3. tBW is measured from the time of going LOW S-UB or LOW S-LB to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change.
6. During this period, DQ pins are in the output state, therefore the input signals of
opposite phase to the outputs must not be applied.
7. If S-CE1 goes LOW or S-CE2 goes HIGH simultaneously with S-WE going LOW or
after S-WE going LOW, the outputs remain in HIGH impedance state.
8. If S-CE1 goes HIGH or S-CE2 goes LOW simultaneously with S-WE going HIGH or
S-WE going HIGH, the outputs remain in HIGH impedance state.
LRS1342-9
Figure 10. Write Cycle Timing Diagram (S-WE Controlled)
18
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
tWC
ADDRESS
tAW
tAS
tCW
(NOTE 4)
(NOTE 2)
tWR
S-CE1
tWR
(NOTE 5)
S-CE2
tBW
(NOTE 3)
S-UB, S-LB
tWP
(NOTE 7)
S-WE
DOUT
HIGH IMPEDANCE
tDW
tDH
(NOTE 6)
DIN
Data Valid
NOTES:
1. A write occurs during the overlap of a LOW S-CE1, a HIGH S-CE2 and a LOW S-WE.
A write begins at the latest transition among S-CE1 going LOW, S-CE2 going HIGH
and S-WE going LOW. A write ends at the earliest transition among S-CE1 going HIGH,
S-CE2 going LOW and S-WE going HIGH. tWP is measured from the beginning of
write to the end of write.
2. tCW is measured from the later of S-CE1 going LOW or S-CE2 going HIGH to the end
of write.
3. tBW is measured from the time of going LOW S-UB or LOW S-LB to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change.
6. During this period, DQ pins are in the output state, therefore the input signals of
opposite phase to the outputs must not be applied.
7. If S-CE1 goes LOW or S-CE2 goes HIGH simultaneously with S-WE going LOW or
after S-WE going LOW, the outputs remain in HIGH impedance state.
LRS1342-10
Figure 11. Write Cycle Timing Diagram (S-CE Controlled)
Data Sheet
19
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
tWC
ADDRESS
tAW
tCW
(NOTE 2)
S-CE1
tWR
S-CE2
tBW
(NOTE 3)
S-UB, S-LB
tAS
tWP
(NOTE 4)
(NOTE 7)
tWR
(NOTE 5)
S-WE
tWZ
tOW
(NOTE 8)
DOUT
tDW
tDH
(NOTE 6)
Data Valid
DIN
NOTES:
1. A write occurs during the overlap of a LOW S-CE1, a HIGH S-CE2 and a LOW S-WE.
A write begins at the latest transition among S-CE1 going LOW, S-CE2 going HIGH
and S-WE going LOW. A write ends at the earliest transition among S-CE1 going HIGH,
S-CE2 going LOW and S-WE going HIGH. tWP is measured from the beginning of
write to the end of write.
2. tCW is measured from the later of S-CE1 going LOW or S-CE2 going HIGH to the end
of write.
3. tBW is measured from the time of going LOW S-UB or LOW S-LB to the end of write.
4. tAS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change.
6. During this period, DQ pins are in the output state, therefore the input signals of
opposite phase to the outputs must not be applied.
7. If S-CE1 goes LOW or S-CE2 goes HIGH simultaneously with S-WE going LOW or
after S-WE going LOW, the outputs remain in HIGH impedance state.
8. If S-CE1 goes HIGH or S-CE2 goes LOW simultaneously with S-WE going HIGH or
S-WE going HIGH, the outputs remain in HIGH impedance state.
LRS1342-11
Figure 12. Write Cycle Timing (S-UB, S-LB Controlled)
20
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
SRAM DATA RETENTION CHARACTERISTICS
TA = -25°C to +85°C
CONDITIONS
MIN.
TYP.1
PARAMETER
SYMBOL
Data Retention Supply Voltage
VCCDR
S-CE2 ≤0.2 V or
S-CE1 ≥ VCCDR - 0.2 V
Data Retention Supply Current
ICCDR
VCCDR = 3V, S-CE2 ≤0.2 V or
S-CE1 ≥ VCCDR - 0.2 V
Chip Enable Setup Time
tCDR
0
ns
Chip Enable Hold Time
tR
5
ms
2.0
MAX.
UNIT
NOTES
3.6
V
2
35
µA
2
NOTES:
1. Reference value at TA = 25°C, S-VCC = 3.0 V.
2. S-CE1 ≥ VCC - 0.2 V, S-CE2 ≥ VCC - 0.2 V (S-CE1 controlled) or S-CE2 ≤0.2 V (S-CE2 controlled).
Data Retention Mode
S-VCC
2.7 V
tR
tCDR
2.2 V
VCCDR
S-CE1 ≥ VCCDR - 0.2 V
S-CE1
0V
NOTE: To control the data retention mode at S-CE1, fix the input level of S-CE2 between
VCCDR and VCCDR - 0.2 V, or 0 V and 0.2 V, and during the data retention mode.
LRS1342-12
Figure 13. Data Retention Timing Diagram (S-CE1 Controlled)
Data Retention Mode
S-VCC
2.7 V
tCDR
S-CE2
tR
VCCDR
0.6 V
S-CE2 ≤ 0.2 V
0V
LRS1342-13
Figure 14. Data Retention Timing Diagram (S-CE2 Controlled)
Data Sheet
21
LRS1341/LRS1342
GENERAL DESIGN GUIDELINES
Supply Power
Maximum difference (between F-VCC and S-VCC) of
the voltage is less than 0.3 V.
Stacked Chip (16M Flash & 2M SRAM)
Data Protection Through F-VPP
When the level of F-VPP is lower than F-VPPLK (lockout voltage), write operation on the flash memory is disabled. All blocks are locked and the data in the blocks
are completely write protected.
Power Supply and Chip Enable of Flash
Memory and SRAM
For the lockout voltage refer to the ‘DC Characteristics’ section.
S-CE1 should not be LOW and S-CE2 should not be
HIGH when F-CE is LOW simultaneously.
Data Protection During Voltage Transition
If the two memories are active together, they may
not operate normally because of interference noises or
data collision on DQ bus.
DATA PROTECTION THROUGH F-RP
When the F-RP is kept LOW during power up and
power down sequence, write operation on the flash
memory is disabled, write protecting all blocks.
Both F-VCC and S-VCC need to be applied by the
recommended supply voltage at the same time except
SRAM data retention mode.
Power Up Sequence
When turning on Flash memory power supply, keep
F-RP LOW. After F-VCC reaches over 2.7 V, keep F-RP
LOW for more than 100 ns.
Device Decoupling
The power supply needs to be designed carefully
because one of the SRAM and the Flash Memory is in
standby mode when the other is active. A careful
decoupling of power supplies is necessary between
SRAM and Flash Memory. Note peak current caused
by transition of control signals (F-CE, S-CE1, S-CE2).
FLASH MEMORY DATA PROTECTION
Noises having a level exceeding the limit specified in
the specification may be generated under specific
operating conditions on some systems.
Such noises, when induced onto F-WE signal or
power supply may be interpreted as false commands,
causing undesired memory updating.
To protect the data stored in the flash memory
against unwanted overwriting, systems operating with
the flash memory should have the following write protect designs, as appropriate:
Protecting Data in Specific Block
By setting a F-WP to LOW, only the boot block can
be protected against overwriting. Parameter and main
blocks cannot be locked. System program, etc., can be
locked by storing them in the boot block. When a high
voltage is applied to F-RP, overwrite operation is
enabled for all blocks.
For further information on setting/resetting of block
bit, and controlling of F-WP and F-RP, refer to the
‘Command Definitions’ section.
22
For details of F-RP control refer to the ‘Flash
Memory AC Electrical Characteristics’ section.
DESIGN CONSIDERATIONS
Power Supply Decoupling
To avoid a bad effect on the system by flash memory
power switching characteristics, each device should
have a 0.1 µF ceramic capacitor connected between its
VCC and GND and between its VPP and GND. LOW
inductance capacitors should be placed as close as
possible to package leads.
VPP Trace on Printed Circuit Boards
Updating the memory contents of flash memories
that reside in the target system requires that the printed
circuit board designer pay attention to the VPP Power
Supply trace. Use similar trace widths and layout considerations given to the VCC power bus.
The Inhibition of Overwrite Operation
Please do not execute reprogramming ‘0’ for the bit
which has already been programmed ‘0’. Overwrite
operation may generate unerasable bit. In case of
reprogramming ‘0’ to the data which has been programmed ‘1’.
• Program ‘0’ for the bit in which you want to change
data from ‘1’ to ‘0’.
• Program ‘1’ for the bit which has already been programmed ‘0’.
For
example,
changing
data
from
‘1011110110111101’ to ‘1010110110111100’ requires
‘1110111111111110’ programming.
Power Supply
Block erase, full chip erase, word write and lock-bit
configuration with an invalid VPP (see ‘DC Characteristics’) produce spurious results and should not be
attempted. Device operations at invalid VCC voltage
product spurious results and should be attempted.
Data Sheet
Stacked Chip (16M Flash & 2M SRAM)
LRS1341/LRS1342
OUTLINE DIMENSIONS
FBGA072-P-0811
B
A
INDEX
8.0 +0.2
-0
TOP VIEW
11.0 +0.2
-0
0.10
S
S
SIDE VIEW
0.40 TYP.
(See Detail)
0.10
S
DETAIL
1.1 TYP.
0.4 TYP.
0.8 TYP.
1.4 MAX.
C
0.35 ±0.05
1.2 TYP.
H
D
BOTTOM VIEW G
F
0.8 TYP.
E
0.4 TYP.
D
C
B
A
1
2
3
4 5
6
7
8 9 10 11 12
φ 0.45 ±0.05
NOTE: Dimensions are in mm.
Data Sheet
φ 0.30 M
S AB
φ 0.15 M
S CD
72FBGA
23
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
LIFE SUPPORT POLICY
SHARP components should not be used in medical devices with life support functions or in safety equipment (or similiar applications where
component failure would result in loss of life or physical harm) without the written approval of an officer of the SHARP Corporation.
LIMITED WARRANTY
SHARP warrants to its Customer that the Products will be free from defects in material and workmanship under normal use and service for a
period of one year from the date of invoice. Customer's exclusive remedy for breach of this warranty is that SHARP will either (i) repair or
replace, at its option, any Product which fails during the warranty period because of such defect (if Customer promptly reported the failure to
SHARP in writing) or, (ii) if SHARP is unable to repair or replace, refund the purchase price of the Product upon its return to SHARP. This
warranty does not apply to any Product which has been subjected to misuse, abnormal service or handling, or which has been altered or
modified in design or construction, or which has been serviced or repaired by anyone other than Sharp. The warranties set forth herein are in
lieu of, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE
WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY
EXCLUDED. In no event will Sharp be liable, or in any way responsible, for any incidental or consequential economic or property damage.
The above warranty is also extended to Customers of Sharp authorized distributors with the following exception: reports of failures of Products
during the warranty period and return of Products that were purchased from an authorized distributor must be made through the distributor.
In case Sharp is unable to repair or replace such Products, refunds will be issued to the distributor in the amount of distributor cost.
SHARP reserves the right to make changes in specifications at any time and without notice. SHARP does not assume any responsibility
for the use of any circuitry described; no circuit patent licenses are implied.
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of the Americas
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Facsimile: (360) 834-8903
http://www.sharpsma.com
SHARP Electronics (Europe) GmbH
Microelectronics Division
Sonninstraße 3
20097 Hamburg, Germany
Phone: (49) 40 2376-2286
Facsimile: (49) 40 2376-2232
http://www.sharpmed.com
SHARP Corporation
Integrated Circuits Group
2613-1 Ichinomoto-Cho
Tenri-City, Nara, 632, Japan
Phone: +81-743-65-1321
Facsimile: +81-743-65-1532
http://www.sharp.co.jp
©1999 by SHARP Corporation
Reference Code SMA99092