bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 I2C Controlled 3A Single Cell USB Charger With Narrow VDC 4.5-5.5V Adjustable Voltage at 1.5A Synchronous Boost Operation Check for Samples: bq24295 FEATURES 1 • • 2 • • • • • 90% High Efficiency Switch Mode 3A Charger 3.9V-6.2V Single Input USB-compliant Charger with 6.4V Over-Voltage Protection – USB Host or Charging Port D+/D- Detection Compatible to USB Battery Charger Spec (BC1.2) – Support Non-standard 2A/1A Adapters detection – Input voltage and current limit supports USB2.0 and USB 3.0 – Input Current Limit: 100mA, 150mA, 500mA, 900mA, 1A, 1.5A, 2A, and 3A Synchronous Boost Converter in Battery Boost Mode with – Adjustable Output [email protected] – 90% 5.1V Boost Mode Efficiency – Fast OTG Startup (22ms typ.) Narrow VDC (NVDC) Power Path Management – Instant System On with No Battery or Deeply Discharged Battery – Ideal Diode Operation in Battery Supplement Mode 1.5MHz Switching Frequency for Low Profile 1.2mm Inductor I2C port for optimal system performance and status reporting Autonomous Battery Charging with or without Host Management – Battery Charge Enable – Battery Charge Preconditioning – Charge Termination and Recharge • • • • • • • High Accuracy – ±0.5% Charge Voltage Regulation – ±7% Charge Current Regulation – ±7.5% Input Current Regulation – ±3% Output Voltage Regulation in Boost Mode High Integration – Power Path Management – Synchronous Switching MOSFETs – Integrated Current Sensing – Bootstrap Diode – Internal Loop Compensation Safety – Battery Temperature Sensing for Charging and Discharging in Boost Mode – Battery Charging Safety Timer – Thermal Regulation and Thermal Shutdown – Input and System Over-Voltage Protection – MOSFET Over-Current Protection Charge Status Outputs for LED or Host Processor Maximum power tracking capability by input voltage regulation 20µA Low Battery Leakage Current and Support Shipping Mode 4mm x 4mm QFN-24 Package APPLICATIONS • • • Power Bank for Smartphone, Tablet Portable Media Players Internet Devices 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION The bq24295 is a highly-integrated switch-mode battery charge management and system power path management devices for 1 cell Li-Ion and Li-polymer battery in a wide range of power bank, tablet and other portable device applications. Its low impedance power path optimizes switch-mode operation efficiency, reduces battery charging time and extends battery life during discharging phase. The I2C serial interface with charging and system settings makes the device a truly flexible solution. The device supports a 3.9V-6.2V USB input sources, including standard USB host port and USB charging port with 6.4V over-voltage protection. The bq24295 is compliant with USB 2.0 and USB 3.0 power specifications with input current and voltage regulation. To set the default input current limit, the bq24295 detects the input source through D+/D- detection following the USB battery charging spec 1.2. In addition, the bq24295 detects nonstandard 2A/1A adapters. The bq24295 supports battery boost operation by supplying adjustable voltage 4.555.5V (default 5.1V) on PMID pin with minimum current of 1.5A. The power path management regulates the system slightly above battery voltage but does not drop below 3.5V minimum system voltage (programmable). With this feature, the system maintains operation even when the battery is completely depleted or removed. When the input current limit or voltage limit is reached, the power path management automatically reduces the charge current to zero. As the system load continues to increase, the power path discharges the battery until the system power requirement is met. This supplement mode operation prevents overloading the input source. The devices initiate and complete a charging cycle without software control. It automatically detects the battery voltage and charges the battery in three phases: pre-conditioning, constant current and constant voltage. At the end of the charging cycle, the charger automatically terminates when the charge current is below a preset limit in the constant voltage phase. When the full battery falls below the recharge threshold, the charger will automatically start another charging cycle. The devices provide various safety features for battery charging and system operation, including negative thermistor monitoring, charging safety timer and over-voltage/over-current protections. The thermal regulation reduces charge current when the junction temperature exceeds 120°C (programmable). The STAT output reports the charging status and any fault conditions. The INT immediately notifies the host when a fault occurs. The bq24295 is available in a 24-pin, 4x4 mm2 thin QFN package. bq24295 Configuration Table bq24295 2 I2C Address 6BH Boost Mode Output Yes Adjustable [email protected] (max) USB Detection D+/D- Default Battery Voltage 4.208V Default Charge Current 1.024A Default Adapter Current Limit 3A Default Pre-charge Current / Max Pre-charge Current 256mA / 2.048A Default Termination Current 256mA Charging Temperature Profile Cold/Hot Status Output STAT, STAT During Fault Blinking @ 1Hz Default Safety Timer 12hr Default VINDPM 4.76V Default Pre-charge Timer 4hr Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 ORDERING INFORMATION PART NUMBER PART MARKING PACKAGE bq24295 bq24295 24-pin 4mmx4mm VQFN ORDERING NUMBER QUANTITY bq24295RGER 3000 bq24295RGET 250 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 3 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com APPLICATION DIAGRAM APPLICATION SCHEMATIC L1 2.2mH 5V USB SDP/DCP C2 1m F Phone Tablet SW VBUS BTST PMID REGN C1 20mF min SYS R6 10kW C3 47nF C6 10mF C7 10mF C4 4.7mF PGND OTG R1 317W (1.5A max) ILIM bq24295 USB SYS BAT R2 2.2kW +3.3V R4 10kW Host R5 10kW SDA SCL INT CE C5 10mF QON STAT R3 10kW SYS BATTERY D+ D– Optional REGN RT1 5.52kW TS Power Pad RT2 31.23kW RTH 10kW Charge Enable (0°C - 45°C) Figure 1. bq24295 with USB D+/D- Detection for Charging and Discharging in Boost Mode 4 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 FUNCTIONAL BLOCK DIAGRAM VBUS PMID RBFET (Q1) VVBUS_UVLOZ UVLO Q1 Gate Control VBATZ +VSLEEP SLEEP REGN REGN LDO EN_HIZ ACOV VACOV BTST FBO I(Q2) IOTG_HSZCP Q2_UCP_BOOST I(Q3) Q3_OCP_BOOST VINDPM IOTG_LSOCP IINDPM SW BAT IC TJ CONVERTER CONTROL BATOVP HSFET (Q2) REGN 104%xVBAT_REG BAT TREG LSFET (Q3) VBAT_REG ILSFET_UCP UCP Q2_OCP I(Q3) SYS VSYSMIN ICHG_REG I(Q2) PGND IHSFET_OCP EN_HIZ EN_CHARGE EN_BOOST REFRESH VBTST-SW VBTST_REFRESH SYS ICHG VBAT_REG ICHG_REG REF DAC BAD_SRC CONVERTER CONTROL TSHUT STATE MACHINE ILIM D+ D– USB Host Adapter Detection BAT_GD USB Adapter OTG RECHRG INT IBADSRC I2C Interface SCL SDA BATSHORT BATFET (Q4) IDC BAT IC TJ TSHUT BAT QON VBATGD VBAT_REG - VRECHG BAT ICHG TERMINATION CHARGE ITERM CONTROL SUSPEND STATE VBATLOWV MACHINE BATLOWV BAT STAT Q4 Gate Control bq24295 BATTERY THERMISTER SENSING TS VSHORT BAT CE Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 5 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com VBUS PMID REGN BTST SW SW PINOUTS 24 23 22 21 20 19 VBUS 1 18 PGND D+ 2 17 PGND D– 3 16 SYS bq24295 STAT 15 SYS 4 SCL 5 14 SDA 13 BAT 8 9 10 11 12 CE ILIM TS QON INT 7 OTG 6 BAT PIN FUNCTIONS PIN 6 TYPE DESCRIPTION NAME NO. VBUS 1,24 P D+ 2 I Analog Positive line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD) and primary detection in bc1.2. D– 3 I Analog Negative line of the USB data line pair. D+/D– based USB host/charging port detection. The detection includes data contact detection (DCD) and primary detection in bc1.2. STAT 4 O Open drain charge status output to indicate various charger operation. Connect to the pull up rail via 10kohm. LOW indicates charge in progress. HIGH indicates charge complete or charge disabled. When any fault condition occurs, STAT pin in the charge blinks at 1Hz. Charger Input Voltage. The internal n-channel reverse block MOSFET (RBFET) is connected between VBUS and PMID with VBUS on source. Place a 1µF ceramic capacitor from VBUS to PGND and place it as close as possible to IC. SCL 5 I I2C Interface clock. Connect SCL to the logic rail through a 10kΩ resistor. SDA 6 I/O I2C Interface data. Connect SDA to the logic rail through a 10kΩ resistor. INT 7 O Open-drain Interrupt Output. Connect the INT to a logic rail via 10kΩ resistor. The INT pin sends active low, 256us pulse to host to report charger device status and fault. OTG 8 I Digital OTG Enable pin. The boost mode is activated when the OTG pin is High, REG01[5], and no Input source is detected at VBUS. CE 9 I Active low Charge Enable pin. Battery charging is enabled when REG01[5:4]=01 and CE pin = Low. CE pin must be pulled high or low. ILIM 10 I ILIM pin sets the maximum input current limit by regulating the ILIM voltage at 1V. A resistor is connected from ILIM pin to ground to set the maximum limit as IINMAX = (1V/RILIM) × KILIM. The actual input current limit is the lower one set by ILIM and by I2C REG00[2:0]. The minimum input current programmed on ILIM pin is 500mA. TS 11 I Analog Temperature qualification voltage input #1. Connect a negative temperature coefficient thermistor. Program temperature window with a resistor divider from REGN to TS1 to GND. Charge suspends or Boost disable disable when TS pin is out of range. Recommend 103AT-2 thermistor. QON 12 I BATFET enable control in shipping mode. A logic low to high transition on this pin with minimum 2ms high level turns on BATFET to exit shipping mode. It has internal 1MΩ (typ.) pull down. For backward compatibility, when BATFET enable control function is not used, the pin can be no connect or tied to TS pin. (Please refer to Shipping Mode for detail description). BAT 13,14 P Battery connection point to the positive terminal of the battery pack. The internal BATFET is connected between BAT and SYS. Connect a 10uF closely to the BAT pin. SYS 15,16 I System connection point. The internal BATFET is connected between BAT and SYS. When the battery falls below the minimum system voltage, switch-mode converter keeps SYS above the minimum system voltage. PGND 17,18 P Power ground connection for high-current power converter node. Internally, PGND is connected to the source of the nchannel LSFET. On PCB layout, connect directly to ground connection of input and output capacitors of the charger. A single point connection is recommended between power PGND and the analog GND near the IC PGND pin. SW 19,20 O Switching node connecting to output inductor. Internally SW is connected to the source of the n-channel HSFET and the drain of the n-channel LSFET. Connect the 0.047µF bootstrap capacitor from SW to BTST. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 PIN FUNCTIONS (continued) PIN TYPE DESCRIPTION NAME NO. BTST 21 P PWM high side driver positive supply. Internally, the BTST is connected to the anode of the boost-strap diode. Connect the 0.047µF bootstrap capacitor from SW to BTST. REGN 22 P PWM low side driver positive supply output. Internally, REGN is connected to the cathode of the boost-strap diode. Connect a 4.7-μF (10V rating) ceramic capacitor from REGN to analog GND. The capacitor should be placed close to the IC. REGN also serves as bias rail of TS pin. PMID 23 P Battery Boost Mode Output Voltage. Connected to the drain of the reverse blocking MOSFET and the drain of HSFET. The minimum capactiance required on PMID to PGND is 20uF PowerPAD – P Exposed pad beneath the IC for heat dissipation. Always solder PowerPAD™ to the board, and have vias on the PowerPAD plane star-connecting to PGND and ground plane for high-current power converter. ABSOLUTE MAXIMUM RATINGS (1) VALUE VBUS (converter not switching) –2 V – 15 V (2) PMID (converter not switching) –0.3 V – 15 V (2) STAT –0.3 V – 12 V BTST –0.3 V – 12 V SW –2 V – 7 V 8V (Peak for 20ns duration) Voltage range (with respect to GND) Output sink current BAT, SYS (converter not switching) –0.3 V – 6 V SDA, SCL, INT, OTG, ILIM, REGN, TS, QON CE, D+, D–, –0.3 V – 7 V BTST TO SW –0.3 V – 7 V PGND to GND –0.3 V – 0.3 V INT, STAT 6mA Junction temperature –40°C to 150°C Storage temperature –65°C to 150°C (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. VBUS is specified up to 16V for a maximum of 24 hours under no load conditions. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT 3.9 6.2 (1) V Input current (VBUS) 3 A Output current (SYS) 3.5 A Battery voltage 4.4 V 3 A VIN Input voltage IIN ISYS VBAT IBAT TA (1) Fast charging current Discharging current with internal MOSFET Operating free-air temperature range –40 5.5 A 85 °C The inherent switching noise voltage spikes should not exceed the absolute maximum rating on either the BTST or SW pins. A tight layout minimizes switching noise. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 7 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com THERMAL INFORMATION RGE PACKAGE THERMAL METRIC (1) 24-PIN θJA Junction-to-ambient thermal resistance 32.2 θJCtop Junction-to-case (top) thermal resistance 29.8 θJB Junction-to-board thermal resistance 9.1 ψJT Junction-to-top characterization parameter 0.3 ψJB Junction-to-board characterization parameter 9.1 θJCbot Junction-to-case (bottom) thermal resistance 2.2 (1) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. space ELECTRICAL CHARACTERISTICS VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS QUIESCENT CURRENTS VVBUS < VUVLO, VBAT = 4.2 V, leakage between BAT and VBUS IBAT Battery discharge current (BAT, SW, SYS) IVBUS Input supply current (VBUS) IBOOST Battery Discharge Current in boost mode 5 µA High-Z Mode, or no VBUS, BATFET disabled (REG07[5] = 1), –40°C – 85°C 16 20 µA High-Z Mode, or no VBUS, BATFET enabled (REG07[5] = 0), –40°C – 85°C 32 55 µA VVBUS = 5 V, High-Z mode, No battery 15 30 µA VVBUS > VUVLO, VVBUS > VBAT, converter not switching 1.5 3 mA VVBUS > VUVLO, VVBUS > VBAT, converter switching, VBAT=3.2V, ISYS=0A 4 mA VVBUS > VUVLO, VVBUS > VBAT, converter switching, charge disable, VBAT=3.8V, ISYS=100µA 3.5 mA VBAT=4.2V, Boost mode, IPMID = 0A, converter switching 3.5 mA VBUS/BAT POWER UP VVBUS_OP VBUS operating range VVBUS_UVLOZ VBUS for active I2C, no battery VVBUS rising 3.6 VSLEEP Sleep mode falling threshold VVBUS falling, VVBUS-VBAT 35 VSLEEPZ Sleep mode rising threshold VVBUS rising, VVBUS-VBAT 170 VACOV VBUS over-voltage rising threshold VVBUS rising 6.2 VACOV_HYST VBUS Over-Voltage Falling Hysteresis VVBUS falling VBAT_UVLOZ Battery for active I2C, no VBUS VBAT rising VBAT_DPL Battery depletion threshold VBAT falling 2.4 VBAT_DPL_HY Battery depletion rising hysteresis VBAT rising 200 VVBUSMIN Bad adapter detection threshold VVBUS falling 3.8 V IBADSRC Bad adapter detection current source 30 mA tBADSRC Bad source detection duration 30 ms 8 3.9 Submit Documentation Feedback 6.2 V 80 120 mV 250 350 mV V 6.6 250 V mV 2.3 V 2.6 V mV Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS (continued) VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS 4.35 V POWER PATH MANAGEMENT VSYS_RANGE Typical system regulation voltage Isys = 0A, BATFET (Q4) off, VBAT up to 4.2 V, REG01[3:1]=101, VSYSMIN = 3.5 V 3.5 VSYS_MIN System voltage output REG01[3:1]=101, VSYSMIN = 3.5 V 3.5 RON(RBFET) Top reverse blocking MOSFET onresistance between VBUS and PMIID RON(HSFET) Internal top switching MOSFET onresistance between PMID and SW RON(LSFET) Internal bottom switching MOSFET onresistance between SW and PGND VFWD 3.65 V 28 41 mΩ TJ = –40°C – 85°C 39 51 TJ = -40°C – 125°C 39 58 TJ = –40°C – 85°C 61 82 TJ = -40°C – 125°C 61 90 BATFET forward voltage in supplement mode BAT discharge current 10mA 30 mV VSYS_BAT SYS/BAT Comparator VSYS falling 70 mV VBATGD Battery good comparator rising threshold VBAT rising 3.55 V VBATGD_HYST Battery good comparator falling threshold VBAT falling 100 mV mΩ mΩ BATTERY CHARGER VBAT_REG_ACC Charge voltage regulation accuracy VBAT = 4.112V and 4.208V VBAT = 3.8V, ICHG = 1024mA, TJ = 25°C IICHG_REG_ACC Fast charge current regulation accuracy –0.5 0.5 % -4 4 % VBAT = 3.8V, ICHG = 1024mA, TJ = -20°C – 125°C -7 7 % VBAT = 3.8V, ICHG = 2112mA, TJ = -20°C – 125°C –10 10 % 75 175 mA ICHG_20pct Charge current with 20% option on VBAT = 3.1V, ICHG = 104mA, REG02=03 and REG02[0]=1 VBATLOWV Battery LOWV falling threshold Fast charge to precharge, REG04[1] = 1 2.6 2.8 2.9 V VBATLOWV_HYST Battery LOWV rising threshold Precharge to fast charge, REG04[1] = 1 (Typical 200mV hysteresis) 2.8 3.0 3.1 V IPRECHG_ACC Precharge current regulation accuracy VBAT = 2.6V, ICHG = 256mA –20 ITYP_TERM_ACC Typical Termination current ITERM = 256mA, ICHG = 2048mA ITERM_ACC Termination current accuracy ITERM = 256mA, ICHG = 2048mA VSHORT Battery Short Voltage VBAT falling 2.0 V VSHORT_HYST Battery Short Voltage hysteresis VBAT rising 200 mV ISHORT Battery short current VBAT<2.2V 100 mA VRECHG Recharge threshold below VBAT_REG VBAT falling, REG04[0] = 0 100 mV tRECHG Recharge deglitch time VBAT falling, REG04[0]=0 20 TJ = 25°C 24 28 TJ = –40°C – 125°C 24 35 RON_BATFET SYS-BAT MOSFET on-resistance 20 265 –22.5 % mA 22.5 % ms mΩ INPUT VOLTAGE/CURRENT REGULATION VINDPM_REG_ACC Input voltage regulation accuracy -2 2 USB100 85 100 mA USB150 125 150 mA USB500 440 500 mA mA IUSB_DPM USB Input current regulation limit, VBUS = 5V, current pulled from SW USB900 750 900 IADPT_DPM Input current regulation accuracy IADP=1.5A, REG00[2:0]=101 1.3 1.5 IIN_START Input current limit during system start up VSYS<2.2V KILIM IIN = KILIM/RILIM IINDPM = 1.5A 100 395 435 % A mA 475 AxΩ D+/D- DETECTION VD+_SRC D+ voltage source ID+_SRC D+ connection check current source ID–_SINK D– current sink ID_LKG Leakage current into D+/D– VD+_LOW D+ Low comparator threshold 0.5 0.7 V 7 14 µA 150 µA D–, switch open 50 –1 100 1 µA D+, switch open –1 1 µA 0.8 V Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 9 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other noted. PARAMETER TEST CONDITIONS MIN MAX UNITS 250 TYP 400 mV 14.25 24.8 kΩ VD–_LOWdatref D– Low comparator threshold RD–_DWN D– Pulldown for connection check tSDP_DEFAULT Charging timer with 100mA USB host in default mode Vadpt1_lo D+ Low Comparator Threshold for Nonstandard adapter Divider-1 As Percentage of REGN, 0°C – 85°C (1) 46.5 48 49.5 % Vadpt1_hi D+ Low Comparator Threshold for Nonstandard adapter Divider-1 As Percentage of REGN, 0°C – 85°C (1) 58.5 60 61.5 % Vadpt2_lo D+ Low Comparator Threshold for Nonstandard adapter Divider-2 As Percentage of REGN, 0°C – 85°C (1) 15.5 17 18.5 % Vadpt2_hi D+ Low Comparator Threshold for Nonstandard adapter Divider-2 As Percentage of REGN, 0°C – 85°C (1) 28.5 30 31.5 % Vadpt3_lo D- Low Comparator Threshold for Nonstandard adapter Divider-3 As Percentage of REGN, 0°C – 85°C (1) 46.5 48 49.5 % Vadpt3_hi D- High Comparator Threshold for Nonstandard adapter Divider-3 As Percentage of REGN, 0°C – 85°C (1) 58.5 60 61.5 % 45 mins BAT OVER-VOLTAGE PROTECTION VBATOVP Battery over-voltage threshold VBAT rising, as percentage of VBAT_REG 104 % VBATOVP_HYST Battery over-voltage hysteresis VBAT falling, as percentage of VBAT_REG 2 % tBATOVP Battery over-voltage deglitch time to disable charge 1 µs THERMAL REGULATION AND THERMAL SHUTDOWN TJunction_REG Junction temperature regulation accuracy REG06[1:0] = 11 120 °C TSHUT Thermal shutdown rising temperature Temperature increasing 160 °C TSHUT_HYS Thermal shutdown hysteresis 30 °C Thermal shutdown rising deglitch Temperature increasing delay 1 ms Thermal shutdown falling deglitch Temperature decreasing delay 1 ms COLD/HOT THERMISTER COMPARATOR VLTF Cold temperature threshold, TS pin voltage rising threshold Charger suspends charge. As Percentage to VREGN VLTF_HYS Cold temperature hysteresis, TS pin voltage falling As Percentage to VREGN VHTF Hot temperature TS pin voltage falling threshold As Percentage to VREGN 46.6 47.7 48.8 % VTCO Cut-off temperature TS pin voltage falling threshold As Percentage to VREGN 44.2 44.7 45.2 % Deglitch time for temperature out of range detection VTS > VLTF, or VTS < VTCO, or VTS < VHTF Cold Temperature Threshold, TS pin Voltage Rising Threshold As Percentage to VREGN REG02[1]=0 (Approx. -10◦C w/ 103AT) VBCOLD0 Cold Temperature Threshold 1, TS pin Voltage Rising Threshold As Percentage to VREGN REG02[1]=1 (Approx. -20◦C w/ 103AT) VBHOT0 Hot Temperature Threshold, TS pin Voltage falling Threshold Hot Temperature Threshold 1, TS pin Voltage falling Threshold (1) 10 As Percentage to VREGN REG06[3:2]= 00 (Approx. 60◦C w/ 103AT) Hot Temperature Threshold 2, TS pin Voltage falling Threshold As Percentage to VREGN REG06[3:2]= 10 (Approx. 65◦C w/ 103AT) 76 78.5 79 ms 76.5 36 79.5 33 36.5 30 % % 33.5 3 29.5 % % 3 32.5 % % 1 35.5 % % 1 As Percentage to VREGN REG06[3:2]= 00 (Approx. 3◦C w/ 103AT) VBHOT1_HYS VBHOT2 75.5 As Percentage to VREGN REG06[3:2]= 01 (Approx. 3◦C w/ 103AT) VBHOT0_HYS VBHOT1 As Percentage to VREGN REG06[3:2]= 01 (Approx. 55◦C w/ 103AT) 74 10 As Percentage to VREGN REG02[1]=1 (Approx. 1◦C w/ 103AT) VBCOLD1_HYS 73.5% 0.4 As Percentage to VREGN REG02[1]=0 (Approx. 1◦C w/ 103AT) VBCOLD0_HYS VBCOLD1 73 % % 30.5 % REGN LDO is configured in drop-out mode. VBUS is close to REGN when IREGN= 0mA. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 ELECTRICAL CHARACTERISTICS (continued) VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other noted. PARAMETER TEST CONDITIONS MIN As Percentage to VREGN REG06[3:2]= 10 (Approx. 3◦C w/ 103AT) VBHOT2_HYS TYP MAX UNITS 3 % CHARGE OVER-CURRENT COMPARATOR IHSFET_OCP HSFET cycle by cycle over-current threshold 5.3 7.5 A IBATFET_OCP System over load threshold 5.5 6.6 A VLSFET_UCP LSFET charge under-current falling threshold 100 mA FSW PWM Switching frequency, and digital clock DMAX Maximum PWM duty cycle VBTST_REFRESH Bootstrap refresh comparator threshold From sync mode to non-sync mode 1300 VBTST-VSW when LSFET refresh pulse is requested, VBUS=5V 1500 1700 % 3.6 V Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 kHz 97 11 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VVBUS_UVLOZ < VVBUS < VACOV and VVBUS > VBAT + VSLEEP, TJ = –40°C to 125°C and TJ = 25°C for typical values unless other noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS BOOST MODE OPERATION VOTG_REG Boost mode output voltage I(PMID) = 0, REG06[7:4]=1001 (5.126V) VOTG_REG_ACC Boost mode output voltage accuracy I(PMID) = 0, REG06[7:4]=1001 (5.126V) VOTG_BAT Battery voltage exiting boost mode BAT falling, REG04[1]=1 IOTG Boost mode output current on PMID VOTG_OVP OTG over-voltage threshold Rising Threshold VOTG_OVP_HYS OTG over-voltage threshold hysteresis Falling Threshold IOTG_LSOCP LSFET cycle by cycle current limit IOTG_HSZCP HSFET under current falling threshold 5.12 -3 V 3 2.9 V 1.3 5.8 % A 6 V 300 mV 100 mA 5 A REGN LDO VREGN REGN LDO output voltage IREGN REGN LDO current limit VVBUS = 6V, IREGN = 40mA 4.8 5 VVBUS = 5V, IREGN = 20mA 4.7 4.8 5.5 V VVBUS = 5V, VREGN = 3.8V 50 mA 2 ms V QON Timing tQON QON pin high time to turn on BATFET LOGIC I/O PIN CHARACTERISTICS (OTG, CE, STAT, QON) VILO Input low threshold VIH Input high threshold 0.4 VOUT_LO Output low saturation voltage Sink current = 5 mA IBIAS High level leakage current (OTG, CE, STAT ) IBIAS High level leakage current (QON) 1.3 V V 0.4 V Pull up rail 1.8V 1 µA Pull up rail 3.6V 8 µA I2C INTERFACE (SDA, SCL, INT) VIH Input high threshold level VPULL-UP = 1.8V, SDA and SCL VIL Input low threshold level VPULL-UP = 1.8V, SDA and SCL 1.3 0.4 V VOL Output low threshold level Sink current = 5mA 0.4 V IBIAS High-level leakage current VPULL-UP = 1.8V, SDA and SCL 1 µA fSCL SCL clock frequency 400 kHz V DIGITAL CLOCK AND WATCHDOG TIMER fHIZ Digital crude clock REGN LDO disabled 15 35 50 kHz fDIG Digital clock REGN LDO enabled 1300 1500 1700 kHz tWDT REG05[5:4]=11 REGN LDO disabled 112 160 REGN LDO enabled 136 160 sec Figure 2. I2C-Compatible Interface Timing Diagram 12 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 TYPICAL CHARACTERISTICS Table 1. Tables of Figures FIGURE NO. CHARGING EFFICIENCY vs. CHARGING CURRENT (DCR = 10mΩ) Figure 3 SYSTEM EFFICIENCY vs. SYSTEM LOAD CURRENT (DCR = 10mΩ) Figure 4 BOOST MODE EFFICIENCY vs VBUS LOAD CURRENT (DCR = 10mΩ) Figure 5 SYS VOLTAGE REGULATION vs SYSTEM LOAD CURRENT Figure 6 BOOST MODE PMID VOLTAGE REGULATION (Typical Output = 5.126V ; REG06[7:4]=1001) vs PMID LOAD CURRENT Figure 7 SYS VOLTAGE vs TEMPERATURE Figure 8 BAT VOLTAGE vs TEMPERATURE Figure 9 INPUT CURRENT LIMIT vs TEMPERATURE Figure 10 CHARGE CURRENT vs PACKAGE TEMPERATURE Figure 11 bq24295 Power Up with Charge Enabled (VBAT =3.2V) Figure 12 bq24295 Power Up with Charge Disabled (VBAT =3.2V) Figure 13 Charge Enable (VBUS = 5V) Figure 14 Charge Disable Figure 15 PWM Switching in Buck Mode (VBUS = 5V, No Battery, ISYS = 40mA, Charge Disable) Figure 16 Input Current DPM Response Without Battery (VBUS = 5V, IIN = 3A, No Battery, Charge Disable Figure 18 Load Transient During Supplement Mode (VBUS = 5V, IIN = 1.5A, VBAT = 3.8V) Figure 19 Boost Mode Switching (VBAT = 3.8V, ILOAD = 1A) Figure 20 Boost Mode Load Transient (VBAT = 3.8V) Figure 21 CHARGE EFFICIENCY vs CHARGE CURRENT SYSTEM EFFICIENCY vs SYSTEM LOAD CURRENT 95 95 90 85 Efficiency (%) Efficiency (%) 90 80 75 85 80 75 70 VBUS = 5V VBUS = 5V 65 70 0 0.5 1 1.5 2 2.5 3 3.5 0 Charge Current (A) 0.5 1 1.5 2 2.5 3 Load Current (A) Figure 3. Figure 4. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 13 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com SYS VOLTAGE REGULATION vs SYSTEM LOAD CURRENT 100 4 95 3.9 90 3.8 SYS Voltage (V) Efficiency (%) BOOST MODE EFFICIENCY vs VBUS LOAD CURRENT 85 80 75 70 60 0 0.5 1 3.6 SYSMIN = 3.5 SYSMIN = 3.2 SYSMIN = 3.7 3.5 3.4 VBAT = 3.2V VBAT = 3.5V VBAT = 3.8V 65 3.7 3.3 3.2 1.5 0 0.5 1 VBUS Load Current (A) 2.5 Figure 6. BOOST MODE PMID VOLTAGE REGULATION (Typical Output = 5.126V ; REG06[7:4]=1001) vs PMID LOAD CURRENT SYS VOLTAGE vs TEMPERATURE 3 3.5 3.7 5.1 3.65 SYS Voltage (V) BOOST Mode Output Voltage (V) 2 Figure 5. 5.2 5 4.9 4.8 0 0.5 1 3.6 3.55 VBAT = 3.2V VBAT = 3.5V VBAT = 3.8V 4.7 4.6 SYSMIN = 3.5V 3.5 -50 1.5 -25 0 25 50 75 100 125 150 Temperature (oC) VBUS Load Current (A) Figure 7. Figure 8. BAT VOLTAGE vs TEMPERATURE INPUT CURRENT LIMIT vs TEMPERATURE 4.4 2.5 Input Current Limit (A) 4.35 BAT Voltage (V) 1.5 System Load Current (A) 4.3 4.25 4.2 1.5 IIN = 500mA IIN = 1.5A IIN = 2A 1 0.5 VREG = 4.208V 4.15 2 VREG = 4.35V 4.1 0 -50 -25 0 25 50 75 100 125 150 -50 Temperature (oC) 0 25 50 75 100 125 150 Temperature (oC) Figure 9. 14 -25 Figure 10. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 CHARGE CURRENT vs PACKAGE TEMPERATURE 2.5 bq24295 Power Up with Charge Enabled (VBAT =3.2V) TREG = 120C TREG = 80C Charge Current (A) 2 VBUS 5V/div 1.5 REGN 5V/div 1 SYS 2V/div 0.5 IBAT 2A/div 0 60 80 100 120 Package Temperature 140 100ms/div 160 (oC) Figure 11. Figure 12. bq24295 Power Up with Charge Disabled (VBAT =3.2V) VBUS 5V/div REGN 5V/div SYS 2V/div IBAT 2A/div 100ms/div Figure 13. Charge Disable PWM Switching in Buck Mode (VBUS = 5V, No Battery, ISYS = 40mA, Charge Disable) STAT 2V/div CE 5V/div IL 1A/div SW 5V/div SW 2V/div IBAT 1A/div 4ms/div 400ns/div Figure 15. Figure 16. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 15 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com PFM Switching in Buck Mode (VBUS = 5V, VBAT = 3.6V, ICHG = 2.5A) Input Current DPM Response Without Battery (VBUS = 5V, IIN = 3A, No Battery, Charge Disable) SYS3p5 500mV/div SYS3p7 100mV/div ISYS 2A/div SW 2V/div IL 1A/div IVBUS 2A/div 4ms/div 2ms/div Figure 17. Figure 18. Load Transient During Supplement Mode (VBUS = 5V, IIN = 1.5A, VBAT = 3.8V) Boost Mode Switching (VBAT = 3.8V, ILOAD = 1A) SYS3p8 500mV/div ISYS 2A/div SW 2V/div IBAT 2A/div IVBUS 2A/div IL 1A/div 20ms/div 400ns/div Figure 19. Figure 20. Boost Mode Load Transient (VBAT = 3.8V) VBUS 200mV/div IBAT 1A/div IVBUS 1A/div 4ms/div Figure 21. 16 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 I2C Registers Address: 6BH. REG00-07 support Read and Write. REG08-0A are read only. Input Source Control Register REG00 (default 01011000, or 58) BIT DESCRIPTION Bit 7 EN_HIZ 0 – Disable, 1 – Enable Input Voltage Limit Bit 6 VINDPM[3] 640mV Bit 5 VINDPM[2] 320mV Bit 4 VINDPM[1] 160mV Bit 3 VINDPM[0] 80mV Input Current Limit (Actual input current limit is the lower of I2C and ILIM) Bit 2 IINLIM[2] 000 – 100mA, 001 – 150mA, 010 – 500mA, 011 – 900mA, 100 – 1A, 101 – 1.5A, Bit 1 IINLIM[1] 110 – 2A, 111 – 3A Bit 0 IINLIM[0] Default: Disable (0) Offset 3.88V, Range: 3.88V-5.08V Default: 4.76V (1011) Default Default Default Default SDP: 500mA (010) DCP/CDP: 3A (101) Divider 1 & 2: 2A (110) Divider 3: 1A (100) Power-On Configuration Register REG01 (default 00011011, or 1B) BIT Bit 7 Bit 6 Register Reset DESCRIPTION 0 – Keep current register setting, 1 – Reset to default I2C Watchdog Timer Reset 0 – Normal ; 1 – Reset Charger Configuration Bit 5 OTG_CONFIG 0 – OTG Disable; 1 – OTG Enable Bit 4 CHG_CONFIG 0- Charge Disable; 1- Charge Enable Minimum System Voltage Limit Bit 3 SYS_MIN[2] 0.4V Bit 2 SYS_MIN[1] 0.2V Bit 1 SYS_MIN[0] 0.1V Bit 0 Reserved 1 - Reserved NOTE Default: Keep current register setting (0) Note: Register Reset bit does not reset device to default mode Default: Normal (0) Note: Consecutive I2C watchdog timer reset requires minimum 20uS delay Default: OTG Enable (1) Note: OTG_CONFIG would over-ride Charge Enable Function in CHG_CONFIG Default: Charge Battery (1) Offset: 3.0V, Range 3.0V-3.7V Default: 3.5V (101) Charge Current Control Register REG02 (default 01100000, or 60) BIT Fast Charge Current Limit Bit 7 ICHG[5] Bit 6 ICHG[4] Bit 5 ICHG[3] Bit 4 ICHG[2] Bit 3 ICHG[1] Bit 2 ICHG[0] Bit 1 BCOLD Bit 0 FORCE_20PCT DESCRIPTION NOTE 2048mA 1024mA 512mA 256mA 128mA 64mA Set Boost Mode temperature monitor threshold voltage to disable boost mode 0 – Vbcold0 (Typ. 76% of REGN or -10◦C w/ 103AT thermistor ) 1 – Vbcold1 (Typ. 79% of REGN or -20◦C w/ 103AT thermistor) 0 – ICHG as Fast Charge Current (REG02[7:2]) and IPRECH as Pre-Charge Current (REG03[7:4]) programmed 1 – ICHG as 20% Fast Charge Current (REG02[7:2]) and IPRECH as 50% Pre-Charge Current (REG03[7:4]) programmed Offset: 512mA Range: 512-3008mA (000000 - 100111) Default: 2048mA (011000) Note: ICHG higher than 3008mA is not suported Default: Vbcold0 (0) Default: ICHG as Fast Charge Current (REG02[7:2]) and IPRECH as Pre-Charge Current (REG03[7:4]) programmed (0) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 17 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com Pre-Charge/Termination Current Control Register REG 03 (default 00010001, or 0x11) BIT DESCRIPTION Pre-Charge Current Limit Bit 7 IPRECHG[3] 1024mA Bit 6 IPRECHG[2] 512mA Bit 5 IPRECHG[1] 256mA Bit 4 IPRECHG[0] 128mA Termination Current Limit Bit 3 ITERM[3] 1024mA Bit 2 ITERM[2] 512mA Bit 1 ITERM[1] 256mA Bit 0 ITERM[0] 128mA NOTE Offset: 128mA, Range: 128mA – 2048mA Default: 256mA (0001) Offset: 128mA Range: 128mA – 2048mA Default: 256mA (0001) Charge Voltage Control Register REG04 (default 10110010, or 0xB2) BIT DESCRIPTION Charge Voltage Limit Bit 7 VREG[5] 512mV Bit 6 VREG[4] 256mV Bit 5 VREG[3] 128mV Bit 4 VREG[2] 64mV Bit 3 VREG[1] 32mV Bit 2 VREG[0] 16mV Bit 1 BATLOWV 0 – 2.8V, 1 – 3.0V Battery Recharge Threshold (below battery regulation voltage) Bit 0 VRECHG 0 – 100mV, 1 – 300mV NOTE Offset: 3.504V Range: 3.504V – 4.400V Default: 4.208V Default: 3.0V (1) (pre-charge to fast charge) Default: 100mV (0) Charge Termination/Timer Control Register REG05 (default 10011010, or 0x9A) BIT DESCRIPTION Charging Termination Enable Bit 7 EN_TERM 0 – Disable, 1 – Enable Bit 6 Reserved 0 - Reserved I2C Watchdog Timer Setting Bit 5 WATCHDOG[1] 00 – Disable timer, 01 – 40s, 10 – 80s, 11 – Bit 4 WATCHDOG[0] 160s Charging Safety Timer Enable Bit 3 EN_TIMER 0 – Disable, 1 – Enable Fast Charge Timer Setting Bit 2 CHG_TIMER[1] 00 – 5 hrs, 01 – 8 hrs, 10 – 12 hrs, 11 – 20 Bit 1 CHG_TIMER[0] hrs Bit 0 Reserved 0 - Reserved 18 NOTE Default: Enable termination (1) Default: 40s (01) Default: Enable (1) Default: 12 hrs (10) (See Charging Safety Timer for details) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 Boost Voltage/Thermal Regulation Control Register REG06 (default 10010011, or 0x93) BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 DESCRIPTION 512mV 256mV 128mV 64mV Set Boost Mode temperature monitor threshold voltage to disable boost mode Voltage to disable boost mode 00 – Vbhot1 (33% of REGN or 55◦C w/ 103AT thermistor) 01 – Vbhot0 (36% of REGN or 60◦C w/ 103AT thermistor) 10 – Vbhot2 (30% of REGN or 65◦C w/ 103AT thermistor) 11 – Disable boost mode thermal protection. Thermal Regulation Threshold Bit 1 TREG[1] 00 – 60°C, 01 – 80°C, 10 – 100°C, 11 – 120°C Bit 0 TREG[0] BOOSTV[3] BOOSTV[2] BOOSTV[1] BOOSTV[0] BHOT[1] BHOT[0] NOTE Offset: 4.55V Range: 4.55V – 5.51V Default:5.126V(1001) Default: Vbhot1 (00) Note: For BHOT[1:0]=11, boost mode operates without temperature monitor and the NTC_FAULT is generated based on Vbhot1 threshold Default: 120°C (11) Misc Operation Control Register REG07 (default 01001011, or 4B) BIT Force DPDM detection Bit 7 DPDM_EN DESCRIPTION NOTE 0 – Not in D+/D– detection; 1 – Force D+/D– detection when VBUS power is presence Safety Timer Setting during Input DPM and Thermal Regulation Bit 6 TMR2X_EN 0 – Safety timer not slowed by 2X during input DPM or thermal regulation, 1 – Safety timer slowed by 2X during input DPM or thermal regulation Force BATFET Off Bit 5 BATFET_Disable 0 – Allow BATFET (Q4) turn on, 1 – Turn off BATFET (Q4) Bit 4 Reserved 0 - Reserved Bit 3 Reserved 1 - Reserved Bit 2 Reserved 0 - Reserved Bit 1 INT_MASK[1] 0 – No INT during CHRG_FAULT, 1 – INT on CHRG_FAULT Bit 0 INT_MASK[0] 0 – No INT during BAT_FAULT, 1 – INT on BAT_FAULT Default: Not in D+/D– detection (0), Back to 0 after detection complete Default: Safety timer slowed by 2X (1) Default: Allow BATFET (Q4) turn on(0) Default: INT on CHRG_FAULT (1) Default: INT on BAT_FAULT (1) System Status Register REG08 BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VBUS_STAT[1] VBUS_STAT[0] CHRG_STAT[1] CHRG_STAT[0] DPM_STAT PG_STAT THERM_STAT VSYS_STAT DESCRIPTION 00 – Unknown (no input, or DPDM detection incomplete), 01 – USB host, 10 – Adapter port, 11 – OTG 00 – Not Charging, 01 – Pre-charge (<VBATLOWV), 10 – Fast Charging, 11 – Charge Termination Done 0 – Not DPM, 1 – VINDPM or IINDPM 0 – Not Power Good, 1 – Power Good 0 – Normal, 1 – In Thermal Regulation 0 – Not in VSYSMIN regulation (BAT>VSYSMIN), 1 – In VSYSMIN regulation (BAT<VSYSMIN) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 19 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com New Fault Register REG09 (1) (2) (3) BIT Bit 7 Bit 6 WATCHDOG_FAULT OTG_FAULT Bit Bit Bit Bit Bit CHRG_FAULT[1] CHRG_FAULT[0] BAT_FAULT Reserved NTC_FAULT[1] 5 4 3 2 1 Bit 0 (1) (2) (3) NTC_FAULT[0] DESCRIPTION 0 – Normal, 1- Watchdog timer expiration 0 – Normal, 1 – VBUS overloaded in OTG, or VBUS OVP, or battery is too low (any conditions that we cannot start boost function) 00 – Normal, 01 – Input fault (OVP or bad source), 10 - Thermal shutdown, 11 – Charge Timer Expiration 0 – Normal, 1 – System OVP Reserved – 0 0-Normal 1–Cold Note: Cold temperature threshold is different based on device operates in buck or boost mode 0-Normal 1–Hot Note: Hot temperature threshold is different based on device operates in buck or boost mode REG09 only supports single byte i2c read. All register bits in REG09 are latched fault. First time read of REG09 will clear the previous fault and second read will update fault register to any fault that still presents. When adapter is unplugged, input fault (bad source) in CHRG_FAULT bits[5:4] will be set to 01 once. Vender / Part / Revision Status Register REG0A BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PN[2] PN[1] PN[0] Reserved Reserved Rev[2] Rev[1] Rev[0] DESCRIPTION 110 (bq24295) 0 – Reserved 0 – Reserved 000 DETAILED DESCRIPTION The bq24295 is an I2C controlled power path management device and a single cell Li-Ion battery charger. It integrates the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4) between system and battery. The device also integrates the bootstrap diode for the high-side gate drive. Device Power Up Power-On-Reset (POR) The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS or VBAT rises above UVLOZ, the sleep comparator, battery depletion comparator and BATFET driver are active. I2C interface is ready for communication and all the registers are reset to default value. The host can access all the registers after POR. By default, the BATFET driver is inactive when battery power is first applied. The BATFET driver can be enabled by plugging in DC source, by clearing BATFET_Disable bit (REG07[5]), or logic low to high transition on QON pin. Power Up from Battery without DC Source If only battery is present and the voltage is above depletion threshold (VBAT_DEPL), the BATFET turns on and connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDSON in BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time. During both boost and charge mode, the device always monitors the discharge current through BATFET. When the system is overloaded or shorted, the device will immediately turn off BATFET and keep BATFET off until the input source plugs in again. 20 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 BATFET Turn Off The BATFET can be forced off by the host through I2C REG07[5]. This bit allows the user to independently turn off the BATFET when the battery condition becomes abnormal during charging. When BATFET is off, there is no path to charge or discharge the battery. When battery is not attached, the BATFET should be turned off by setting REG07[5] to 1 to disable charging and supplement mode. Shipping Mode To extend battery life and minimize power when system is powered off during system idle, shipping, or storage, the device can turn off BATFET so that the system voltage is zero to minimize the leakage. The BATFET can be turned off by setting REG07[5] (BATFET_DISABLE) bit. In order to keep BATFET off during shipping mode, the host has to disable the watchdog timer (REG05[5:4]=00) and disable BATFET (REG07[5]=1) at the same time. Once the BATFET is disabled, one of the following events can turn on BATFET and clear REG07[5] (BATFET_DISABLE) bit. 1. Plug in adapter 2. Write REG07[5]=0 3. watchdog timer expiration 4. Register reset (REG01[7]=1) 5. A logic low to high transition on QON pin (refer to Figure 22 for detail timing) Min. 2ms QON BATFET Status Turn on by QON REG07[5]=0 Turn off by i2c command REG07[5]=1 Figure 22. QON Timing Boost Mode Operation from Battery The device supports boost converter operation to deliver power from the battery to other portable devices through PMID pin. The boost mode output current rating meets the 1.5A charging requirements for smartphone and tablet. The boost operation is enabled by default if the conditions are valid: 1. BAT above BATLOWV threshold (VBATLOWV set by REG04[1]) 2. VBUS less than BAT+VSLEEP (in sleep mode) 3. Boost mode operation is enabled (OTG pin HIGH and REG01[5:4]=10) 4. After 30ms delay from boost mode enable In battery boost mode, the device employs a 1.5MHz step-up switching regulator. During boost mode, the status register REG08[7:6] is set to 11, the PMID output voltage is 5.1V. In addition, the device provides adjustable boost voltage from 4.55V to 5.5V by changing BOOSTV bits in REG06[7:4]. Any fault during boost operation, including PMID over-voltage, sets the fault register REG09[6] to 1 and an INT is asserted. For power bank applications, the boost current is supported from PMID pin as in the application diagram. It is recommended to use the minimum PMID cap value 20uF for boost current. Please note that there is no boost current limit setting when the boost current is sourced from PMID pin, hence it is important not to overload the boost current under this condition. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 21 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com Integrated Control to Switch Between USB Charge Mode and Boost Mode The device features integrated control to switch between charge mode and boost mode by monitoring VBUS voltage. When VBUS is higher than VBAT+VSLEEP , the RBFET is enabled and charge mode is enabled. When VBUS power source is removed, the RBFET is automatically turn off to isolate VBUS from PMID. The boost mode is started when the conditions described above are met. Power Up from DC Source When the DC source plugs in, the charger device checks the input source voltage to turn on REGN LDO and all the bias circuits. It also checks the input current limit before starts the buck converter. REGN LDO The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The REGN is enabled when all the conditions are valid. 1. VBUS above VVBUS_UVLOZ 2. VBUS above VBAT + VSLEEPZ in buck mode or VBUS below VBAT + VSLEEP in boost mode 3. After typical 220ms delay (100ms minimum) is complete If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The device draws less than IVBUS (15µA typical) from VBUS during HIZ state. The battery powers up the system when the device is in HIZ. Input Source Qualification After REGN LDO powers up, the device checks the current capability of the input source. The input source has to meet the following requirements to start the buck converter. 1. VBUS voltage below VACOV (not in VBUS over-voltage) 2. VBUS voltage above VBADSRC (3.8V typical) when pulling IBADSRC (30mA typical) (poor source detection) Once the input source passes all the conditions above, the status register REG08[2] goes high and the PG pin goes low. An INT is asserted to the host. If the device fails the poor source detection, it will repeat the detection every 2 seconds. Input Current Limit Detection The USB ports on personal computers are convenient charging source for portable devices (PDs). If the portable device is attached to a USB host, the USB specification requires the portable device to draw limited current (500mA in USB 2.0, and 150mA/900mA in USB 3.0). If the portable device is attached to a charging port, it is allowed to draw up to 3A. After the REG08[2] goes HIGH, the charger device always runs input current limit detection when a DC source plugs in unless the charger is in HIZ during host mode. The bq24295 follows Battery Charging Specification 1.2 (BC1.2) to detect input source through USB D+/D- lines. After the input current limit detection is done, the detection result is reported in VBUS_STAT registers (REG08[7:6]) and input current limit is updated in IINLIM register (REG00[2:0]). In additon, host can write to REG00[2:0] to change the input current limit. D+/D– Detection Sets Input Current Limit The bq24295 contains a D+/D– based input source detection to program the input current limit. The D+/Ddetection has three steps: data contact detect (DCD), primary detection, and non-standard adapter detection. When the charging source passes data contact detect, the device would proceed to run primary detection. Otherwise the charger would proceed to run non-standard adapter detection. 22 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 D+ VDP_SRC VLGC_HI IDP_SRC CHG_DET VDAC_REF IDM_SINK D- RDM_DWN Figure 23. USB D+/D- Detection DCD (Data Contact Detection) uses a current source to detect when the D+/D– pins have made contact during an attach event. The protocol for data contact detect is as follows: • Detect VBUS present and REG08[2]=1 (power good) • Turn on D+ IDP_SRC and the D– pull-down resistor RDM_DWN for 40ms • If the USB connector is properly attached, the D+ line goes from HIGH to LOW, wait up to 0.5 sec. • Turn off IDP_SRC and disconnect RDM_DWN The primary detection is used to distinguish between USB host (Standard Down Stream Port, or SDP) and different type of charging ports (Charging Down Stream Port, or CDP, and Dedicated Charging Port, or DCP). The protocol for primary detection is as follows: • Turn on VDP_SRC on D+ and IDM_SINK on D– for 40ms • If PD is attached to a USB host (SDP), the D– is low. If PD is attached to a charging port (CDP or DCP), the D– is high • Turn off VDP_SRC and IDM_SINK Table 2 shows the input current limit setting after D+/D– detection. Table 2. bq24295 USB D+/D– Detection D+/D– DETECTION INPUT CURRENT LIMIT REG08[7:6] 0.5 sec timer expired in DCD (D+/Dfloating) Proceed to Non-standard adapter detection 00 USB Host 500 mA 01 Charging Port 3A 10 When DCD 0.5 sec timer expires, the non-standard adapter detection is used to distinguish three different divider bias conditions on D+/D- pins. When non-standard adapter is detected, the input current limit (REG0[2:0]) is set based on the table shown below and REG08[7:6] is set to 10 (Adapter port). If non-standard adapter is not detected, REG08[7:6] is set to 00 (Unknown) and the input current limit is set in REG0[2:0] to 500mA by default. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 23 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com Table 3. bq24295 Non-Standard Adapter Detection Non-Standard Adapter Input Current Limit D+ Threshold D- Threshold Divider 1 Vadpt1_lo < VD+ < Vadpt1_hi For VBUS=5V, typical range 2.4V < VD+ < 3.1V Vadpt1_lo > VD- or VD- < Vadpt1_hi For VBUS=5V, typical range 2.4V > VD- or VD- > 3.1V 2A Divider 2 Vadpt2_lo < VD+ < Vadpt2_hi For VBUS=5V, typical range 0.85V < VD+ < 1.5V NA 2A Divider 3 Vadpt3_lo < VD+ < Vadpt3_hi For VBUS=5V, typical range 2.4V > VD+ or VD+ > 3.1V Vadpt3_lo < VD- < Vadpt3_hi For VBUS=5V, typical range 2.4V < VD- < 3.1V 1A Force Input Current Limit Detection While adapter is plugged-in, the host can force the charger device to run input current limit detection by setting REG07[7]=1 or when watchdog timeout. During the forced detection, the input current limit is set to 100mA. After the detection is completed, REG07[7] will return to 0 by itself and new input current limit is set based on D+/D-. Converter Power-Up After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery. The device provides soft-start when ramp up the system rail. When the system rail is below 2.2V, the input current limit is forced to 100mA. After the system rises above 2.2V, the charger device sets the input current limit set by the lower value between register and ILIM pin. As a battery charger, the charger deploys a 1.5MHz step-down switching regulator. The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current and temperature, simplifying output filter design. A type III compensation network allows using ceramic capacitors at the output of the converter. An internal sawtooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage. In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is set by the ratio of SYS and VBUS. Low Power HIZ State The host can configure the converter to go into HIZ State by setting EN_HIZ (REG00[7]) to 0. The device is in the lowest quiescent state with REGN LDO and the bias circuits off, the VBUS current during HIZ state will be less than 30µA while the system is supplied by the battery. Once the charger device enters HIZ state in host mode, it stays in HIZ until the host writes REG00[7]=0. When the processor host wakes up, it is recommended to first check if the charger is in HIZ state. Power Path Management The device accommodates a wide range of input sources from USB, wall adapter, to car battery. The device provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or both. Narrow VDC Architecture The device deploys Narrow VDC architecture (NVDC) with BATFET separating system from battery. The minimum system voltage is set by REG01[3:1]. Even with a fully depleted battery, the system is regulated above the minimum system voltage (default 3.5V). When the battery is below minimum system voltage setting, the BATFET operates in linear mode (LDO mode), and the system is 150mV above the minimum system voltage setting. As the battery voltage rises above the minimum system voltage, BATFET is fully on and the voltage difference between the system and battery is the VDS of BATFET. 24 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 When the battery charging is disabled or terminated, the system is always regulated at 150mV above the minimum system voltage setting. The status register REG08[0] goes high when the system is in minimum system voltage regulation. 4.5 4.3 Charge Enabled 4.1 SYS (V) Charge Disabled 3.9 3.7 3.5 Minimum System Voltage 3.3 3.1 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 BAT (V) Figure 24. V(SYS) vs V(BAT) Dynamic Power Management To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic Power Management (DPM), which continuously monitors the input current and input voltage. When input source is over-loaded, either the current exceeds the input current limit (REG00[2:0]) or the voltage falls below the input voltage limit (REG00[6:3]). The device then reduces the charge current until the input current falls below the input current limit and the input voltage rises above the input voltage limit. When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to drop. Once the system voltage falls below the battery voltage, the device automatically enters the supplement mode where the BATFET turns on and battery starts discharging so that the system is supported from both the input source and battery. During DPM mode (either VINDPM or IINDPM), the status register REG08[3] will go high. Figure 25 shows the DPM response with 5V/1.2A adapter, 3.2V battery, 2.0A charge current and 3.4V minimum system voltage setting. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 25 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com Voltage VBUS 5V SYS 3.6V 3.4V 3.2V 3.18V BAT Current 3A ICHG 2.3A 2.0A ISYS 1.5A 1.0A 0.5A IIN -0.7A DPM DPM Supplement Figure 25. DPM Response Supplement Mode When the system voltage falls below the battery voltage, the BATFET turns on and the BATFET gate is regulated the gate drive of BATFET so that the minimum BATFET VDS stays at 30mV when the current is low. This prevents oscillation from entering and exiting the supplement mode. As the discharge current increases, the BATFET gate is regulated with a higher voltage to reduce RDSON until the BATFET is in full conduction. At this point onwards, the BATFET VDS linearly increases with discharge current. Figure 26 shows the V-I curve of the BATFET gate regulation operation. BATFET turns off to exit supplement mode when the battery is below battery depletion threshold. 4.5 4.0 CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 V(BAT-SYS) (mV) Figure 26. BATFET V-I Curve Battery Charging Management The device charges 1-cell Li-Ion battery with up to 3A charge current for high capacity tablet battery. The 24mΩ BATFET improves charging efficiency and minimizes the voltage drop during discharging. Autonomous Charging Cycle With battery charging enabled at POR (REG01[5:4]=01), the charger device complete a charging cycle without host involvement. The device default charging parameters are listed in the following table. 26 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 Table 4. Charging Parameter Default Setting (1) A • • • • • DEFAULT MODE bq24295 Charging Voltage 4.208 V Charging Current 1.024A Pre-charge Current 256 mA Termination Current 256 mA Temperature Profile Hot/Cold Safety Timer 12 hours (1) See section Charging Safety Timer for more information. new charge cycle starts when the following conditions are valid: Converter starts Battery charging is enabled by I2C register bit (REG01[5:4]) = 01 and CE is low No thermistor fault on TS No safety timer fault BATFET is not forced to turn off (REG07[5]) The charger device automatically terminates the charging cycle when the charging current is below termination threshold and charge voltage is above recharge threshold. When a full battery voltage is discharged below recharge threshold (REG04[0]), the device automatically starts another charging cycle.After the charge done, either toggle /CE pin or REG01[5:4] will initiate a new charging cycle. The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH) or charging fault (Blinking). The status register REG08[5:4] indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is complete, an INT is asserted to notify the host. The host can always control the charging operation and optimize the charging parameters by writing to the registers through I2C. Battery Charging Profile The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the beginning of a charging cycle, the device checks the battery voltage and applies current. Table 5. Charging Current Setting VBAT CHARGING CURRENT REG DEFAULT SETTING REG08[5:4] VBAT < VSHORT (Typical 2V) 100mA – 01 VSHORT ≤ VBAT < VBATLOWV (Typical 2V ≤ VBAT < 3V) REG03[7:4] 256mA 01 VBAT ≥ VBATLOWV (Typical VBAT ≥ 3V) REG02[7:2] 2048mA 10 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 27 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com If the charger device is in DPM regulation or thermal regulation during charging, the actual charging current will be less than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is counted at half the clock rate. Regulation Voltage (3.5V – 4.4V) Battery Voltage Fast Charge Current (500mA-3008mA) Charge Current VBAT_LOWV (2.8V/3V) VBAT_SHORT (2V) IPRECHARGE (128mA-2048mA) ITERMINATION (128mA-2048mA) IBATSHORT (100mA) Trickle Charge Pre-charge Fast Charge and Voltage Regulation Safety Timer Expiration Figure 27. Battery Charging Profile Thermistor Qualification The charger device provides a single thermistor input for battery temperature monitor. Cold/Hot Temperature Window The device continuously monitors battery temperature by measuring the voltage between the TS pin and ground, typically determined by a negative temperature coefficient thermistor and an external voltage divider. The device compares this voltage against its internal thresholds to determine if charge or boost is allowed. To initiate a charge cycle, the battery temperature must be within the VLTF to VHTF thresholds. During the charge cycle the battery temperature must be within the VLTF to VTCO thresholds, else the device suspends charging and waits until the battery temperature is within the VLTF to VHTF range. For battery protection during boost mode, the device monitors the battery temperature to be within the VBCOLDx to VBHOTx thresholds unless boost mode temperature is disabled by setting BHOT bits (REG06[3:2]) to 11. When temperature is outside of the temperature thresholds, the boost mode and BATFET are disabled and BATFET_Disable bit is set (REG07[5] bit) to reduce leakage current on PMID. Once temperature returns within thresholds, the host can clear BATFET_Disable bit (REG07[5]) or provide logic low to high transition on QON pin to enable BATFET and boost mode. 28 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 REGN bq24295 RT1 TS RTH 103AT RT2 Figure 28. TS Resistor Network When the TS fault occurs, the fault register REG09[2:0] indicates the actual condition on each TS pin and an INT is asserted to the host. The STAT pin indicates the fault when charging is suspended. TEMPERATURE RANGE TO INITIATE CHARGE TEMPERATURE RANGE DURING A CHARGE CYCLE VREF VREF CHARGE SUSPENDED CHARGE SUSPENDED VLTF VLTF VLTFH VLTFH CHARGE at full C CHARGE at full C VHTF VTCO CHARGE SUSPENDED CHARGE SUSPENDED AGND AGND Figure 29. TS Pin Thermistor Sense Thresholds in Charge Mode Temperature Range to Boost VREF V BCOLDx Boost Disable ( - 10ºC / 20ºC) Boost Enable V BHOTx (55ºC / 60ºC / 65ºC) Boost Disable AGND Figure 30. TS Pin thermistor Sense Thresholds in Boost Mode Assuming a 103AT NTC thermistor is used on the battery pack , the value RT1 and RT2 can be determined by using the following equation: Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 29 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com æ 1 1 ö VVREF ´ RTHCOLD ´ RTHHOT ´ ç ÷ è VLTF VTCO ø RT2 = æV ö æV ö RTHHOT ´ ç VREF - 1÷ - RTHCOLD ´ ç VREF - 1÷ è VLTF ø è VTCO ø VVREF -1 VLTF RT1 = 1 1 + RT2 RTHCOLD (1) Select 0°C to 45°C range for Li-ion or Li-polymer battery, RTHCOLD = 27.28 kΩ RTHHOT = 4.911 kΩ RT1 = 5.52 kΩ RT2 = 31.23 kΩ Charging Termination The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is below termination current. After the charging cycle is complete, the BATFET turns off. The converter keeps running to power the system, and BATFET can turn back on to engage supplement mode. When termination occurs, the status register REG08[5:4] is 11, and an INT is asserted to the host. Termination is temporarily disabled if the charger device is in input current/voltage regulation or thermal regulation. Termination can be disabled by writing 0 to REG05[7]. Termination when REG02[0] = 1 When REG02[0] is HIGH to reduce the charging current by 80%, the charging current could be less than the termination current. The charger device termination function should be disabled. When the battery is charged to fully capacity, the host disables charging through CE pin or REG01[5:4]. Charging Safety Timer The device has safety timer to prevent extended charging cycle due to abnormal battery conditions. The safety timer is 4 hours when the battery is below batlowv threshold. The user can program fast charge safety timer (default 12 hours)through I2C (REG05[2:1]). When safety timer expires, the fault register REG09[5:4] goes 11 and an INT is asserted to the host. The safety timer feature can be disabled via I2C (REG05[3]). The following actions restart the safety timer after safety timer expires: • Toggle the CE pin HIGH to LOW to HIGH (charge enable) • Write REG01[5:4] from 00 to 01 (charge enable) • Write REG05[3] from 0 to 1 (safety timer enable) During input voltage/current regulation, thermal regulation, or FORCE_20PCT bit (REG02[0]) is set , the safety timer counting at half clock rate since the actual charge current is likely to be below the register setting. For example, if the charger is in input current regulation (IINDPM) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will expire in 10 hours. This feature can be disabled by writing 0 to REG07[6]. Safety Timer Configuration Change When safety timer value needs to be changed, it is recommended that the timer is disabled first before new configuration is written to REG05[2:1]. The safety timer can be disable by writing 1 to REG05[3]. This ensures the safety timer restart counting after new value is configured. 30 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 Host Mode and Default Mode The device is a host controlled device, but it can operate in default mode without host management. In default mode, the device can be used as an autonomous charger with no host or with host in sleep. When the charger is in default mode, REG09[7] is HIGH. When the charger is in host mode, REG09[7] is LOW. After power-on-reset, the device starts in watchdog timer expiration state, or default mode. All the registers are in the default settings. The device keeps charging the battery by default with 12-hour fast charging safety timer. At the end of the 12 hours, the charging is stopped and the buck converter continues to operate to supply system load. Any write command to device transitions the device from default mode to host mode. All the device parameters can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1 to REG01[6] before the watchdog timer expires (REG05[5:4]), or disable watchdog timer by setting REG05[5:4]=00. When the host changes watchdog timer configuration (REG05[5:4]), it is recommended to first disable watchdog by writing 00 to REG05[5:4] and then change the watchdog to new timer values. This ensures the watchdog timer is restarted after new value is written. POR watchdog timer expired Reset registers I2C interface enabled Host Mode Y I2C Write? Start watchdog timer Host programs registers N Default Mode Reset watchdog timer Reset registers N Reset REG01 bit[6]? Y Y N I2C Write? Y Watchdog Timer Expired? N Figure 31. Watchdog Timer Flow Chart Status Outputs (STAT, and INT) Charging Status Indicator (STAT) The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED as the application diagram shows. Table 6. STAT Pin State CHARGING STATE STAT Charging in progress (including recharge) LOW Charging complete HIGH Sleep mode, charge disable HIGH Interrupt to Host (INT) In some applications, the host does not always monitor the charger operation. The INT notifies the system on the device operation. The following events will generate 256us INT pulse. 1. USB/adapter source identified (through DPDM detection) Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 31 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com 2. Good input source detected – not in sleep – VBUS below VACOV threshold – current limit above IBADSRC 3. Input removed or VBUS above VACOV threshold 4. Charge Complete 5. Any FAULT event in REG09 For the first four events, INT pulse is always generated. For the last event, when a fault occurs, the charger device sends out INT and latches the fault state in REG09 until the host reads the fault register. If a prior fault exists, the charger device would not send any INT upon new faults except NTC fault (REG09[2:0]). The NTC fault is not latched and always reports the current thermistor conditions. In order to read the current fault status, the host has to read REG09 two times consecutively. In order to read the current fault status, the host has to read REG09 two times consecutively. The 1st reads fault register status from the last read and the 2nd reads the current fault register status. Protections Input Current Limit on ILIM For safe operation, the device has an additional hardware pin on ILIM to limit maximum input current on ILIM pin. The input maximum current is set by a resistor from ILIM pin to ground as: 1V IINMAX = ´ KLIM RILIM (2) The actual input current limit is the lower value between ILIM setting and register setting (REG00[2:0]). For example, if the register setting is 111 for 3A, and ILIM has a 316Ω resistor to ground for 1.5A, the input current limit is 1.5A. ILIM pin can be used to set the input current limit rather than the register settings. The device regulates ILIM pin at 1V. If ILIM voltage exceeds 1V, the device enters input current regulation (Refer to Dynamic Power Path Management section). The voltage on ILIM pin is proportional to the input current. ILIM pin can be used to monitor the input current following Equation 3: V IIN = ILIM ´ IINMAX (3) 1V For example, if ILIM pin sets 2A, and the ILIM voltage is 0.75V, the actual input current 1.5A. If ILIM pin is open, the input current is limited to zero since ILIM voltage floats above 1V. If ILIM pin is short, the input current limit is set by the register. Thermal Regulation and Thermal Shutdown During charge operation, the device monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface temperature. When the internal junction temperature exceeds the preset limit (REG06[1:0]), the device lowers down the charge current. The wide thermal regulation range from 60°C to 120°C allows the user to optimize the system thermal performance. During thermal regulation, the actual charging current is usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register REG08[1] goes high. Additionally, the device has thermal shutdown to turn off the converter. The fault register REG09[5:4] is 10 and an INT is asserted to the host. Voltage and Current Monitoring in Buck Mode The device closely monitors the input and system voltage, as well as HSFET and LSFET current for safe buck mode operation. 32 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 Input Over-Voltage (ACOV) The maximum input voltage for buck mode operation is VVBUS_OP. If VBUS voltage exceeds VACOV, the device stops switching immediately. During input over voltage (ACOV), the fault register REG09[5:4] will be set to 01. An INT is asserted to the host. System Over-Voltage Protection (SYSOVP) The charger device clamps the system voltage during load transient so that the components connect to system would not be damaged due to high voltage. When SYSOVP is detected, the converter stops immediately to clamp the overshoot. Current Monitoring in Boost Mode The bq24295 closely monitors LSFET current to ensure safe boost mode operation. Battery Protection Battery Over-Voltage Protection (BATOVP) The battery over-voltage limit is clamped at VBAT_OVP (4% nominal) above the battery regulation voltage. When battery over voltage occurs, the charger device immediately disables charge. The fault register REG09[5] goes high and an INT is asserted to the host. Battery Short Protection If the battery voltage falls below Vshort (2V typical), the device immediately turns off BATFET to disable the battery charging or supplement mode. 1ms later, the BATFET turns on and charge the battery with 100mA current. The device does not turn on BATFET to discharge a battery that is below 2.5V. System Over-Current Protection If the system is shorted or exceeds the over-current limit, the device latches off BATFET. DC source insertion on VBUS is required to reset the latch-off condition and turn on BATFET. Serial Interface The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I2CTM is a bi-directional 2-wire serial interface developed by Philips Semiconductor (now NXP Semiconductors). Only two bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave. The device operates as a slave device with address 6BH, receiving control inputs from the master device like micro controller or a digital signal processor. The I2C interface supports both standard mode (up to 100kbits), and fast mode (up to 400kbits). Both SDA and SCL are bi-directional lines, connecting to the positive supply voltage via a current source or pullup resistor. When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain. Data Validity The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 33 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com SDA SCL Change of data allowed Data line stable; Data valid Figure 32. Bit Transfer on the I2C Bus START and STOP Conditions All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the SCL is HIGH defines a STOP condition. START and STOP conditions are always generated by the master. The bus is considered busy after the START condition, and free after the STOP condition. SDA SDA SCL SCL STOP (P) START (S) Figure 33. START and STOP conditions Byte Format Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL. Acknowledgement signal from receiver Acknowledgement signal from slave MSB SDA SCL S or Sr 1 2 START or Repeated START 7 8 9 ACK 1 2 8 9 ACK P or Sr STOP or Repeated START Figure 34. Data Transfer on the I2C Bus 34 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 Acknowledge (ACK) and Not Acknowledge (NACK) The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock pulse, are generated by the master. The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse. When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then generate either a STOP to abort the transfer or a repeated START to start a new transfer. Slave Address and Data Direction Bit After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ). SDA SCL S 1-7 8 9 START ADDRESS R/W ACK 8 1-7 9 8 1-7 ACK DATA DATA 9 P ACK STOP Figure 35. Complete Data Transfer Single Read and Write 1 7 1 1 8 1 8 1 1 S Slave Address 0 ACK Reg Addr ACK Data Addr ACK P Figure 36. Single Write 1 7 1 1 8 1 1 7 1 1 S Slave Address 0 ACK Reg Addr ACK S Slave Address 1 ACK 8 1 1 Data NCK P Figure 37. Single Read If the register address is not defined, the charger IC send back NACK and go back to the idle state. Multi-Read and Multi-Write The charger device supports multi-read and multi-write on REG00 through REG08. 1 7 1 1 8 1 S Slave Address 0 ACK Reg Addr ACK 8 1 8 1 8 1 1 Slave Address ACK Data to Addr+1 ACK Data to Addr+1 ACK P Figure 38. Multi-Write Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 35 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com 1 7 1 1 8 1 1 7 1 1 S Slave Address 0 ACK Reg Addr ACK S Slave Address 1 ACK 8 Data @ Addr 1 8 1 8 1 1 ACK Data @ Addr+1 ACK Data @ Addr+1 ACK P Figure 39. Multi-Read The fault register REG09 locks the previous fault and only clears it after the register is read. For example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG09 reports the fault when it is read the first time, but returns to normal when it is read the second time. To verify real time fault, the fault register REG09 should be read twice to get the real condition. In addition, the fault register REG09 does not support multi-read or multi-write. REG09 is a fault register. It keeps all the fault information from last read until the host issues a new read. For example, if there is a TS fault but gets recovered immediately, the host still sees TS fault during the first read. In order to get the fault information at present, the host has to read REG09 for the second time. REG09 doesn’t support multi-read and multi-write. 36 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 bq24295 www.ti.com SLUSBC1 – SEPTEMBER 2013 APPLICATION INFORMATION Inductor Selection The device has 1.5 MHz switching frequency to allow the use of small inductor and capacitor values. The Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE): ISAT ³ ICHG + (1/ 2 ) IRIPPLE (4) The inductor ripple current depends on input voltage (VBUS), duty cycle (D = VBAT/VVBUS), switching frequency (fs) and inductance (L): V ´ D ´ (1 - D) IRIPPLE = IN ¦s ´ L (5) The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in the range of (20–40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design. Input Capacitor Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current ICIN occurs where the duty cycle is closest to 50% and can be estimated by the following equation: ICIN = ICHG ´ D ´ (1 - D) (6) For best performance, VBUS should be decouple to PGND with 1μF capacitance. The remaining input capacitor should be place on PMID. Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage rating of the capacitor must be higher than normal input voltage level. 25V rating or higher capacitor is preferred for 15V input voltage. 22μF capacitance is suggested for typical of 3-4A charging current. Output Capacitor Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The output capacitor RMS current ICOUT is given: I ICOUT = RIPPLE » 0.29 ´ IRIPPLE 2´ 3 (7) The output capacitor voltage ripple can be calculated as follows: VOUT æç VOUT ö÷ 1 DVO = VIN ÷ 8LC¦ s2 çè ø (8) At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the output filter LC. The charger device has internal loop compensator. To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 15kHz and 25kHz. The preferred ceramic capacitor is 6V or higher rating, X7R or X5R. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 37 bq24295 SLUSBC1 – SEPTEMBER 2013 www.ti.com PCB Layout The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 40) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential. 1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper trace connection or GND plane. 2. Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane. 3. Put output capacitor near to the inductor and the IC. Ground connections need to be tied to the IC ground with a short copper trace connection or GND plane. 4. Route analog ground separately from power ground. Connect analog ground and connect power ground separately. Connect analog ground and power ground together using power pad as the single ground connection point. Or using a 0Ω resistor to tie analog ground to power ground. 5. Use single ground connection to tie charger power ground to charger analog ground. Just beneath the IC. Use ground copper pour but avoid power pins to reduce inductive and capacitive noise coupling. 6. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible. 7. It is critical that the exposed power pad on the backside of the IC package be soldered to the PCB ground. Ensure that there are sufficient thermal vias directly under the IC, connecting to the ground plane on the other layers. 8. The via size and number should be enough for a given current path. See the EVM design for the recommended component placement with trace and via locations. For the QFN information, refer to SCBA017 and SLUA271. Figure 40. High Frequency Current Path 38 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: bq24295 PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) BQ24295RGER ACTIVE VQFN RGE 24 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ 24295 BQ24295RGET ACTIVE VQFN RGE 24 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 BQ 24295 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 27-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BQ24295RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ24295RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 27-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ24295RGER VQFN RGE 24 3000 367.0 367.0 35.0 BQ24295RGET VQFN RGE 24 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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