ACX306BKM
3.86cm (1.5-type) NTSC/PAL Color LCD Panel Module with LED Backlight
Description
The ACX306BKM is an LCD panel module with LED
backlight developed exclusively for the ACX306BKM
3.86cm diagonal active matrix TFT-LCD panel
addressed by low temperature polycrystalline silicon
transistors with built-in peripheral driving circuitry.
This module provides full-color representation for
NTSC and PAL systems. In addition, RGB dots are
arranged in a delta pattern that provides smooth
picture quality without fixed color patterns compared
to vertical stripe and mosaic patterns.
Features
• Total module thickness: 3.9mm (typ.) ultra-thin, narrow frame type
• Center luminance
Standard mode:
260cd/m2 (backlight 210mW typ.)
High luminance mode: 330cd/m2 (backlight 290mW typ.)
• White LED backlight eliminates the need for an inverter, achieves instant luminance rise, and maintains high
luminance even at cold temperatures
• Backlight life (luminance half-life) guaranteed at 5000h for normal temperature operation and 1000h for high
temperature operation
• Number of active dots: 118,000, 3.86cm (1.5-type) in diagonal
• Horizontal resolution: 240 TV lines
• Optical transmittance: 9.0% (typ.)
• High contrast ratio with normally white mode: 200 (typ.)
• Built-in H and V driving circuitry (built-in input level conversion circuit, 3V drive possible)
• Low voltage, low power consumption: 12V drive, 43mW (panel block, typ.)
• Smooth pictures with a RGB delta arrangement
• Supports NTSC/PAL
• Built-in picture quality improvement circuit
• Up/down and/or right/left inverse display function
• LR (low reflectance) surface treatment provides an easy-to-see display even outdoors
• Dirt-resistant surface treatment
• Narrow frame
Element Structure
• Active matrix TFT-LCD panel with built-in peripheral driving circuitry using low temperature polycrystalline
silicon transistors
• Edge-light type backlight using high luminance white LEDs
• Number of pixels
Total number of dots:
494 (H) × 242 (V) = 119,548
Number of active dots:
490 (H) × 240 (V) = 117,600
• Module dimensions
Package dimensions:
37.1 (W) × 32.7 (D) × 3.9 (H) (mm)
Effective display dimensions: 31.115 (H) × 22.86 (V) (mm)
Applications
Compact digital still cameras, compact video cameras, etc.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00X53A14
ACX306BKM
Module Configuration
Panel Block Diagram
The panel block diagram is shown below.
H Level Shifter & Shift Register
COM
LC
V Shift Register
CS
Boost, Negative
Voltage Generation
Circuit
Level Shifter
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
TESTL
COM
VST
VCK
EN
DWN
VDD
VSS
VDDG
VSSG
TEST2
WIDE
HST
REF
TEST
Cext/Rext
HCK2
HCK1
PSIG
GREEN
RED
BLUE
RGT
TESTR
Common
Voltage
–2–
ACX306BKM
Absolute Maximum Ratings (VSS = 0V)
• H driver supply voltage
• V driver boost supply voltage
• V driver negative supply voltage
• Common voltage of panel
• H driver input pin voltage
• V driver input pin voltage
• Video signal, uniformity improvement
signal input pin voltage
• Operating temperature
• Storage temperature
• LED backlight DC forward voltage
• LED backlight DC forward current
• LED backlight reverse withstand voltage
VDD, Cext/Rext
VDDG
VSSG
COM
HST, HCK1, HCK2, RGT, WIDE
VST, VCK, EN, DWN, REF
GREEN, RED, BLUE, PSIG
Topr
Tstg
Vfbl
Ifbl
Vrbl
–1.0 to +17
VDD – 1.0 to +18
–3.0 to +1.0
–1.0 to +17
–1.0 to +17
–1.0 to +15
–1.0 to +13
–10 to +60
–30 to +80
18
25
0
V
V
V
V
V
V
V
°C
°C
V
mA
V
Operating Conditions of Panel Block
1. Input/output supply voltage conditions∗1
Item
(VSS = 0V)
Symbol
Min.
Typ.
Max
Unit
11.4
12.0
12.6
V
VDD – 3.4
12.0
—
V
VDDG
14.0
15.0
16.3
V
VSSG
–2.3
–1.8
–1.5
V
—
10
160
kΩ
VDD
Supply voltage
Cext/Rext∗2
VDDG output voltage setting
VSSG output voltage setting∗3
Resistor connected to Cext/Rext pin∗2 Rext
∗1 The VDD typical voltage setting is noted as 12.0V in the above table.
∗2 Connect the resistor and capacitor to the Cext/Rext pin as shown in the figure below.
The Cext/Rext value differs according to the rising time of the panel supply voltage.
∗3 For the VDDG, VSSG output setting, connect an external smoothing capacitor and a voltage stabilizing
Zener diode as shown in the figure below.
Cext/Rext constant setting conditions
Recommended voltage applied example
IDD measurement circuit diagram
ACX306BKM
VDD
VDD
Cext/Rext
Voltage
VDD
VSSG
Cext/Rext
VDD – Cext/Rext
7
1µF
Recommended voltage applied
example Zener diode
(RD2.7UM is recommended.)
1µF
Recommended voltage applied
example Zener diode
(RD4.3UM is recommended.)
Rext
Cext
VSS
text
Time
VDDG
Set a Cext value that satisfies text > 1ms.
–3–
ACX306BKM
2. Panel input signal voltage conditions
Item
H/V driver input voltage
(VSS = 0V)
Symbol
Min
Typ.
Max.
Unit
(Low)
VIL
–0.3
0.0
0.3
V
(High)
VIH
2.6
3.0
5.5
V
VIH/2 – 0.3
VIH/2
VIH/2 + 0.3
V
VVC
5.8
6.0
6.2
V
REF input voltage
VREF
Video signal center voltage∗4
Video signal input range∗4
Vsig
1.0
VVC ± 4.0
VDDG – 2.0
V
Uniformity improvement signal∗4
Vpsig
VVC ± 2.3
VVC ± 2.5
VVC ± 2.7
V
Common voltage of panel (Ta = 25°C)
VCOM
VVC – 0.6
VVC – 0.5
VVC – 0.4
V
∗4 Input video and uniformity improvement signals should be input with the voltage amplitude symmetrical to
VVC as shown in Fig. 1.
PSIG waveform
Vpsig
VVC
Fig. 1
Operating Conditions of Backlight Block
1. Input supply voltage conditions
Standard mode: luminance 260cd/m2 operation
Item
Symbol
Min.
Typ.
Max.
Unit
—
15
—
mA
Backlight DC forward current
IfBL
Backlight DC forward voltage
Vfbl15
12.3
13.9
15.5
V
Backlight power consumption
Pbl15
185
209
233
mW
Min.
Typ.
Max.
Unit
—
20
—
mA
High luminance mode: luminance 330cd/m2 operation
Item
Symbol
Backlight DC forward current
IfBL
Backlight DC forward voltage
Vfbl20
12.8
14.4
16.0
V
Backlight power consumption
Pbl20
256
288
320
mW
BL1
(GND)
BL2
(DC constant current input)
Backlight equivalent circuit
–4–
ACX306BKM
Pin Description of Panel Block
Pin
No.
Symbol
Panel test output; no connection
13
HST
Start pulse input for H shift register
drive
COM
Common voltage input of panel
14
REF
Level shifter circuit REF voltage
input
3
VST
Start pulse input for V shift register
drive
15
TEST
Panel test output; no connection
4
VCK
Clock input for V shift register drive
16
Cext/
Rext
Time constant power supply input
for H shift register drive
5
EN
Gate selection pulse enable input
17
HCK2
Clock input for H shift register drive
6
DWN
V shift register drive direction signal
input
18
HCK1
Clock input for H shift register drive
7
VDD
Power supply input for H and V
driver
19
PSIG
Uniformity improvement signal input
8
VSS
H and V driver GND
20
GREEN
Video signal (G) input to panel
9
VDDG
Boost power supply setting for V
driver
21
RED
Video signal (R) input to panel
10
VSSG
Negative power supply setting for
V driver
22
BLUE
Video signal (B) input to panel
11
TEST2
No connection inside the panel.
(with 1MΩ terminating resistor)
23
RGT
H shift register drive direction
signal input
12
WIDE
Uniformity improvement signal
control pulse input
24
TESTR
Panel test output; no connection
Pin
No.
Symbol
1
TESTL
2
Description
Pin Description of Backlight Block
Pin
No.
Symbol
Description
1
BL1
Power supply GND for backlight
lighting
2
BL2
Power supply input for backlight
lighting
–5–
Description
ACX306BKM
Input Equivalent Circuits of Panel Block
To prevent static charges, protective diodes are provided for each pin except the power supplies. In addition,
protective resistors are added to all pins except the video signal input pins. All pins are connected to VSS with
a high resistance of 1MΩ (typ.). The equivalent circuit of each input pin is shown below: (Resistor value: typ.)
(1) RED, GREEN, BLUE, PSIG
VDD
Input
1MΩ
Signal line
(2) HCK1, HCK2
VDD
VDD
H level shifter
and shift register
circuit
HCK1
1MΩ
HCK2
1MΩ
(3) WIDE, REF
VDD
VDD
350Ω
350Ω
Level conversion
circuit
Input
1MΩ
REF
1MΩ
(4) HST
VDD
VDD
175Ω
175Ω
Level conversion
circuit
Input
1MΩ
REF
1MΩ
(5) RGT, REF
VDD
VDD
2kΩ
Input
2kΩ
Level conversion
circuit
1MΩ
REF
1MΩ
–6–
ACX306BKM
(6) VST, VCK, EN, REF
VDD
VDD
800Ω
800Ω
Level conversion
circuit
Input
1MΩ
REF
1MΩ
(7) DWN, REF
VDD
VDD
2kΩ
2kΩ
Level conversion
circuit
Input
1MΩ
REF
1MΩ
(8) VDDG, VSSG
VDD
Boost, Negative
voltage generation
circuit
VDDG, VSSG
(9) COM
Input
LC
1MΩ
(10) Cext/Rext
VDD
1MΩ
H driver
Cext/Rext
2.7MΩ
(11) TEST/TEST2
VDD
350Ω
350Ω
TEST
TEST2
1MΩ
1MΩ
VDD
(12) TESTL, TESTR
4MΩ
TESTL
TESTR
–7–
ACX306BKM
Clock Timing Conditions of Panel Block
(VIH = 3.0V, VDD = 12V, Ta = 25°C)
Item
HST
HCK
VST
VCK
EN
WIDE
Symbol
Min.
Typ.
Max.
HST rise time
trHst
—
—
30
HST fall time
tfHst
—
—
30
HST data setup time
tdHst
300
333
363
HST data hold time
HCKn∗5 rise time
thHst
–30
0
30
trHckn
—
—
30
HCKn∗5 fall time
tfHckn
—
—
30
HCK1 fall to HCK2 rise time
to1Hck
–15
0
15
HCK1 rise to HCK2 fall time
to2Hck
–15
0
15
VST rise time
trVst
—
—
100
VST fall time
tfVst
—
—
100
VST data setup time
tdVst
30
32
34
VST data hold time
thVst
–30
–32
–34
VCK rise time
trVckn
—
—
100
VCK fall time
tfVckn
—
—
100
EN rise time
trEn
—
—
100
EN fall time
tfEn
—
—
100
EN fall to VCK rise/fall time
tdEn
500
600
700
EN pulse width
twEn
2900
3000
3100
WIDE rise time
trWide
—
—
100
WIDE fall time
tfWide
—
—
100
WIDE (H) rise to VCK rise/fall time
tdhWide
–0.4
–0.5
–0.6
WIDE (H) pulse width
twhWide
1.4
1.5
1.6
∗5 HCKn means HCK1 and HCK2. (fHCKn = 1.5MHz)
–8–
Unit
ns
µs
ns
µs
ACX306BKM
Horizontal Standard Timing
3.0µs
HST
HCK1
HCK2
FRP
0.6µs
VCK
3.0µs
EN
WIDE
1.1µs
0.4µs
1.5µs
–9–
ACX306BKM
<Horizontal Shift Register Driving Waveforms>
Item
HST rise time
Symbol
Waveform
90%
trHst
HST
HST fall time
HST
tfHst
90%
10%
10%
trHst
tfHst
HST data setup time
HST data hold time
tdHst
HST
50%
50%
HCKn∗5 rise time
• HCKn∗5 duty cycle
50%
to1Hck = 0ns
to2Hck = 0ns
50% 50%
thHst
thHst
tdHst
trHckn
∗5
90%
HCKn
HCKn∗5 fall time
tfHckn
HCK1 fall to HCK2 rise
time
to1Hck
• HCKn∗5 duty cycle
50%
to1Hck = 0ns
to2Hck = 0ns
tdHst = 333ns
thHst = 0ns
90%
10%
10%
trHckn
tfHckn
∗6
HCK1 50%
50%
50%
• tdHst = 333ns
thHst = 0ns
50%
HCK2
HCK1 rise to HCK2 fall
time
to2Hck
WIDE rise time
trWide
to2Hck
to1Hck
90%
90%
WIDE
10%
WIDE fall time
∗7
WIDE
• HCKn∗5 duty cycle
50%
to1Hck = 0ns
to2Hck = 0ns
∗6
HCK1
HCK
Conditions
tfWide
10%
trWide
tfWide
∗6
WIDE rise to VCK rise/fall
tdhWide
time
VCK
50%
WIDE
WIDE pulse width
50%
twhWide
50%
twhWide
tdhWide
∗6 Definitions:
The right-pointing arrow (
) means +.
The left-pointing arrow (
) means –.
The black dot at an arrow (
) indicates the start of measurement.
∗7 WIDE represents every 1H pulse as shown in Horizontal Timing.
– 10 –
ACX306BKM
Vertical Standard Timing
NTSC 4:3 (in case of EVEN field)
VST
VCK
FRP
HST
EN
WIDE
– 11 –
ACX306BKM
<Vertical Shift Register Driving Waveforms>
Item
VST rise time
Symbol
Waveform
90%
trVst
Conditions
90%
VST
10%
VST
VST fall time
tfVst
VST data setup time
tdVst
10%
trVst
tfVst
∗6
VST
50%
50%
VST data hold time
thVst
tdVst
VCK rise time
50%
50%
VCK
VCK
VCK fall time
tfVck
EN rise time
trEn
90%
10%
10%
trVck
tfVck
90%
90%
10%
10%
EN
EN fall time
tfEn
EN fall to VCK rise/fall
time
tdEn
tfEn
50%
50%
EN
EN pulse width
trEn
∗6
VCK
twEn
tdEn
– 12 –
• VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
thVst
90%
trVck
VCK
EN
• VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
50%
twEn
• VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
tdVst = 32µs
thVst = –32µs
• VCK duty cycle
50%
to1Vck = 0ns
to2Vck = 0ns
ACX306BKM
Electrical Characteristics of Panel Block
1. Horizontal drivers
(Ta = 25°C, VDD = 12.0V, VIH = 3.0V, VREF = 1.5V)
Item
Symbol
Min.
Typ.
Max.
Unit
Conditions
HCKn input pin capacitance
CHckn
—
55
65
pF
HST input pin capacitance
CHst
—
30
50
pF
Video signal input pin capacitance
Csig
—
120
150
pF
Psig input pin capacitance (4:3 display)
Cpsig
—
5.2
8.0
nF
Input pin current
HCK1
I Hck1
–600
–300
—
µA
HCK1: actual driving
HCK2
I Hck2
–600
–300
—
µA
HCK2: actual driving
HST
I Hst
–200
–100
—
µA
HST = GND
RGT
I RGT
–150
–50
—
µA
RGT = GND
REF
I REF
–900
–300
—
µA
REF = VIH/2
Symbol
Min.
Typ.
Max.
Unit
HCKn: HCK1, HCK2 (1.5MHz)
2. Vertical drivers
Item
Conditions
VCK input pin capacitance
CVck
—
10
15
pF
VST input pin capacitance
CVst
—
10
15
pF
Input pin current
VCK
I Vck
–150
–50
—
µA
VCK = GND
VST
I Vst
–150
–50
—
µA
VST = GND
EN
I En
–150
–50
—
µA
EN = GND
DWN
I DWN
–150
–50
—
µA
DWN = GND
WIDE
I WIDE
–150
–50
—
µA
WIDE = GND
Symbol
Min.
Typ.
Max.
Unit
(Ta = 25°C) PWR25
—
43
55
mW
(Ta = 60°C) PWR60
—
—
75
mW
Symbol
Min.
Typ.
Max.
Unit
Rin1
0.5
1
—
MΩ
3. Total power consumption of the panel
Item
Total power consumption
of the panel (NTSC)
4. Pin input resistance
Item
Pin – VSS input resistance 1
– 13 –
ACX306BKM
Electro-optical Characteristics of Module/Panel Block
Item
Symbol
(Ta = 25°C, NTSC mode)
Measurement
method
Min.
Typ.
Max.
Unit
Contrast ratio
CR25
1
100
200
—
—
Panel block optical transmittance∗1
T
2
7.8
9.0
—
%
Iled = 15mA
Lm15
2
180
260
—
Iled = 20mA
Lm20
2
240
330
—
—
0.295
0.325
—
0.310
0.360
CIE
standard
5900
7800
—
K
Center luminance
cd/m2
X
Wx
Y
Wy
Tc
Tcm
∆uv
duvm
–0.016
0.003
0.022
X
Rx
0.590
0.620
0.650
Y
Ry
0.320
0.350
0.380
X
Gx
0.260
0.290
0.320
Y
Gy
0.460
0.500
0.540
X
Bx
0.120
0.150
0.180
Y
By
0.080
0.130
0.180
25°C
V90-25
1.30
1.50
1.70
60°C
V90-60
1.30
1.50
1.70
25°C
V50-25
1.70
1.90
2.10
60°C
V50-60
1.70
1.90
2.10
25°C
V10-25
2.30
2.50
2.70
60°C
V10-60
2.30
2.50
2.70
R–G
V50RG
–0.115
–0.080
–0.045
B–G
V50BG
0
0.03
0.05
0°C
ton0
—
70
90
25°C
ton25
—
17
25
0°C
toff0
—
120
180
25°C
toff25
—
30
75
Flicker∗1
60°C
F
7
—
–60
–30
dB
Image retention time∗1
60°C
YT1
8
—
—
10
s
9
15
50
35
35
20
60
40
40
—
Degree
(°)
W
Chromaticity
(Iled = 15mA)
R
G
B
V90
V-T characteristics∗1
V50
V10
Half tone color reproduction
range∗1
ON time
Response time∗1
OFF time
Viewing angle range
Surface reflection ratio
Cross talk∗1
3
3
θT
θB
CR ≥ 10
θL
θR
4
5
6
CIE
standard
V
V
ms
θ = 0°
Rf
10
—
0.9
1.5
%
25°C
CTK
11
—
0.9
1.5
%
∗1 Conforms to the measurement results for the discrete panel.
– 14 –
ACX306BKM
Electro-optical Characteristics of Backlight Block
Item
Conditions
(Ta = 25°C, discrete backlight)
Symbol
Measurement
method
Min.
Typ.
Max.
Backlight DC forward Ifbl = 15mA
voltage
Ifbl = 20mA
Vfbl15
12
12.3
13.9
15.5
Vfbl20
12
12.8
14.4
16.0
Backlight power
consumption
Ifbl = 15mA
Pbl15
12
185
209
233
Ifbl = 20mA
Pbl20
12
256
288
320
Backlight center
luminance
Ifbl = 15mA
Lbl15
12
2200
3000
—
Ifbl = 20mA
Lbl20
12
2700
3700
—
xbl
12
0.280
0.305
0.330
ybl
12
0.255
0.308
0.360
Tcbl
12
6100
8000
19000
duvbl
12
Ifbl = 15mA
BLunif
13
60
—
—
Ta = less than
55°C
Ifbl = 15mA
BLl1555
14
5000
—
—
Ta = 55 to 70°C BLl1570
14
1000
—
—
Ta = less than
BLl2040
40°C
Ifbl = 20mA
Ta = 40 to 60°C BLl2065
14
5000
—
—
14
1000
—
—
Backlight center
chromaticity
Backlight luminance
uniformity
Backlight life
(Luminance half-life)
Ifbl = 15mA
– 15 –
Unit
V
W
cd/m2
K
+0.011 –0.003 –0.015
%
hr
ACX306BKM
<Panel/Module/Backlight Electro-optical Characteristics Measurement>
Basic measurement conditions
(1) Driving voltage
VDD = 12.0V, VIH = 3.0V, VREF = 1.5V
VVC = 6.0V, VCOM = 5.5V, Vpsig = 6.0 ± 2.5V
(2) Measurement temperature
25°C unless otherwise specified.
(3) Measurement point
One point in the center of the screen unless otherwise specified.
(4) Measurement systems
Three types of measurement systems are used as shown below.
(5) R, G and B input signal voltage Vsig
Vsig = 6.0 ± VAC [V] (VAC: signal amplitude)
• Measurement system I
Surface A∗
Luminance
Meter
TOPCON BM-5A luminance meter
LED backlight
LCD panel
V
A
Constant
current circuit
15mA
• Measurement system II
Optical fiber
Light receptor lens
Light Detector
Surface A∗
Measurement
Equipment
Measure using the discrete LCD panel.
Drive Circuit
Light Source
• Measurement system III
Light
Source
Optical fiber
Spectroscope
Surface A∗
∗ Surface A: See the Package Outline.
1. Contrast Ratio
Contrast ratio (CR) is given by the following formula.
CR = L (White)/L (Black)
L (White): Surface luminance of the TFT-LCD panel at the input signal amplitude VAC = 0.5V.
L (Black): Surface luminance of the panel at VAC = 4.0V.
Both luminosities are measured by System I.
– 16 –
ACX306BKM
2. Optical Transmittance of Panel, Center Luminance of Module, Color Temperature
Optical transmittance (T) is given by the following formula.
T = L (White)/Luminance of Backlight × 100 [%]
L (White) is the same expression as defined in "Contrast Ratio".
Lm = White luminance at the center of the panel
Tcm = Color temperature at the center of the panel
Measured by System I using the TOPCON BM-5A.
3. Chromaticity
Chromaticity of the panels is measured by System I. Raster modes of each color are defined by the
representations at the input signal amplitude conditions shown in the table below. System I uses x and y of
the CIE standards as the chromaticity here.
Signal amplitudes (VAC) supplied to each input
Raster
R input
G input
B input
R
0.5
4.0
4.0
G
4.0
0.5
4.0
B
4.0
4.0
0.5
W
0.0
0.0
0.0
4. V-T Characteristics
V-T characteristics, or the relationship between signal
amplitude and the transmittance of the panel, are
measured by System II by inputting the same signal
amplitude V AC to each input pin. V90, V50, and V10
correspond to the voltages which define 90%, 50%, and
10% of transmittance respectively.
Transmittance [%]
(Unit: V)
90
50
10
V90 V50 V10
VAC – Signal amplitude [V]
V50RG = V50R – V50G
V50BG = V50B – V50G
100
Transmittance [%]
5. Half Tone Color Reproduction Range
The half tone color reproduction range of LCD panels
is characterized by the differences between the V-T
characteristics of R, G and B. The differences of these
V-T characteristics are measured by System II.
System II defines signal voltages of each R, G and B
raster mode which correspond to 50% of transmittance,
V50R, V50G and V50B, respectively. V50RG and V50BG, that
is to say the differences between V50R and V50G and
between V50B and V50G, are given by the following
formulas respectively.
V50RG
V50BG
50
R raster
G raster
B raster
0
V50R V50B
V50G
VAC – Signal amplitude [V]
– 17 –
ACX306BKM
6. Response Time
Response times ton and toff are measured
by System II by applying the input signal
voltages in the figure to the right to each
4.0V
input pin. These times are defined by the 5.5V
following formulas.
ton = t1 – tON
toff = t2 – tOFF
t1: time which gives 10% transmittance
of the panel.
t2: time which gives 90% transmittance
of the panel.
Input signal voltage (Waveform applied to measured pixels)
0.5V
0V
Optical transmittance output
waveform
100%
90%
The relationships between t1, t2, tON and
tOFF are shown in the figure to the right.
10%
0%
tON
t1
ton
tOFF
t2
toff
7. Flicker
Flicker (F) is given by the following formula. DC and AC components (NTSC: 30Hz, rms; PAL: 25Hz, rms) of
the panel output signal for gray raster∗ mode are measured by a DC voltmeter and a spectrum analyzer in
System II.
F [dB] = 20 log {AC component/DC component}
∗ R, G, B input signal voltage for gray raster mode is given by Vsig = 5.5 ± V50 [V]
where: V50 is the signal amplitude which gives 50% of transmittance in V-T curve.
8. Image Retention Time
Image retention time is given by the following procedures.
Apply the monoscope pattern ∗ to the LCD panel for 1 minute and then change to a gray scale signal
(Vsig = 6.0 ± VAC [V]; VAC = 3 to 4V). Judging by sight at the VAC that holds the maximum image retention,
measure the time for the residual image to disappear.
∗ Monoscope pattern input conditions
Vsig = 6.0 ± 4.0 or 6.0 ± 2.0 [V]
(shown in the figure to the right)
VCOM = 5.5V
Black level
White level
4.0V
2.0V
6.0V
2.0V
4.0V
0V
Vsig waveform
– 18 –
ACX306BKM
9. Definition of Viewing Angle Range
Viewing angle range is measured by System I. The
contrast ratio (CR) is measured at the angles
defined in the figure to the right and the range
where CR ≥ 10 is taken as the viewing angle range.
Measure with surface A∗ facing upwards.
∗ Surface A: See the Package Outline.
Normal (θ = 0˚)
θB
θT
θL
Left
θR
Top
Bottom
Right
Surface A
10. Surface Reflection Ratio
Surface reflection ratio (Rf) is given by the following formula.
Rf = Reflected optical luminance of the panel surface A∗/Reflected optical luminance of Al (wafer) × 100 [%]
The incident and reflected angles of light are both 0°.
Both luminosities are measured by System III.
∗ Surface A: See the Package Outline.
11. Cross Talk
Cross talk is determined by the luminance differences between adjacent areas represented by Wi' and Wi
(i = 1 to 4) around the black window (Vsig = 4.0V/1V).
W1
Cross talk value CTK =
W1'
W2
W4
W2'
W4'
W3
W3'
– 19 –
Wi' – Wi
Wi
× 100 [%]
ACX306BKM
12. Backlight Center Luminance and Chromaticity Measurement Method
1. Environmental conditions
Temperature: 25 ± 5°C
Humidity: 30 to 85%
Start measurement after leaving the module in the above environment for one hour.
Measurement should be performed in a dark room with a luminance of 10 lx or less and which is not
subject to the effects of reflective or external light.
There should be no heat insulating objects around the module unit, and measurement should be
performed in a draftless condition.
2. Luminance and chromaticity measurement method
Measurement equipment: TOPCON BM-5A, viewing angle: 0.2°, distance: 450 ± 50mm
Measure 30s after the backlight is lit.
Using a constant current circuit, measure the luminance under both conditions of Ifbl = 15mA and
20mA, and measure the chromaticity under only the condition of Ifbl = 15mA.
13. Backlight Luminance Uniformity Measurement Method
1. Environmental conditions
Measure under the same conditions as "12. Backlight Center Luminance and Chromaticity Measurement
Method" above.
2. Light the backlight at Ifbl = 15mA using a constant current circuit, and start measurement 30s after the
backlight is lit.
Backlight luminance uniformity is obtained by dividing the effective pixel area into 9 equal sections as
shown below, measuring the luminance at each of the centers 1 to 9, and calculating Min. luminance ÷
Max. luminance × 100 [%].
1/3
1/3
1/3
1/3
1
2
3
1/3
4
5
6
1/3
Effective pixel area of the panel
Effective pixel area of the panel
7
8
9
14. Backlight Life Measurement Method
Definition of life:
When the backlight center luminance drops to 50% of the initial value.
Lighting conditions: Discrete backlight under the following conditions.
Leave the module in a normal temperature (25°C) environment for one hour before
performing optical measurement.
(1) Ifbl = 15mA
1-1) Continuous
1-2) Continuous
(2) Ifbl = 20mA
2-1) Continuous
2-2) Continuous
lighting at an ambient temperature of 55°C. (5000h or more)
lighting at an ambient temperature of 70°C. (1000h or more)
lighting at an ambient temperature of 40°C. (5000h or more)
lighting at an ambient temperature of 65°C. (1000h or more)
– 20 –
ACX306BKM
Description of Panel Block Operation
1. Color Coding
The color filters are coded in a delta arrangement. The shaded area is used for the dark border around the
display.
Gate SW
Gate SW
Gate SW
Gate SW
Gate SW
1
Gate SW
R
G
B
R
B
R
G
B
G
B
R
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
R
G
B
G
B
R
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
R
G
B
R
G
B
R
R
G
B
2
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
490
494
– 21 –
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
B
R
G
R
G
B
R
2
1
R
242
240
Active area
ACX306BKM
2. Description of LCD Panel Operations
• A vertical driver, which consists of vertical shift registers, enable-gates and buffers, applies a selected pulse
to each of 240 line electrodes sequentially one line electrode at a time in a single horizontal scanning period.
• The selected pulse is output when the enable pin goes to high level. PAL signal pulse elimination display is
possible by using the enable pin and simultaneously controlling VCK.
• A horizontal driver, which consists of horizontal shift registers, gates and CMOS sample-and-hold circuitry,
applies selected pulses to each of 490 signal electrodes sequentially in a single horizontal scanning period.
These pulses are used to supply the sampled video signal to the row signal lines.
• The scanning direction of the horizontal shift registers can be switched with the RGT pin. The scanning
direction is left to right (right scan) for RGT pin at high level (2.6 to 5.5V), and right to left (left scan) for RGT
pin at low level (0V). In addition, the scanning direction of the vertical shift registers can be switched with the
DWN pin. The scanning direction is top to bottom for DWN pin at high level (2.6 to 5.5V), and bottom to top
for DWN pin at low level (0V). (These scanning directions are from a front view.)
• The vertical and horizontal drivers address one pixel, and then thin film transistors (TFTs; two TFTs for one
pixel) turn on to apply a video signal to the pixel. The same procedures lead to the entire 240 × 490 pixels to
display a picture in a single vertical scanning period.
• Pixel dots are arranged in a delta pattern, where sets of RGB pixels are positioned shifted by 1.5 dots
against adjacent horizontal lines. The horizontal driver output pulse must be shifted by 1.5 dots for each
horizontal line against the horizontal sync signal to apply a video signal to each pixel properly.
• The video signal should be input with the polarity-inverted every horizontal cycle.
• The relationships between the vertical shift register start pulse VST and the vertical display period, and
between the horizontal shift register start pulse HST and the horizontal display period are shown below for
top to bottom and left to right scan.
(1) Vertical display period (DWN: high level)
VD
VST
VCK
2
1
239
240
Vertical display period 240H (14.5ms)
(2) Vertical display period (DWN: low level)
VD
VST
1
VCK
2
239
240
Vertical display period 240H (14.5ms)
(3) Horizontal display period (RGT: high level)
BLK
HST
165
HCK1
1
2
3
164
166
Horizontal display period (54.6µs)
HCK2
– 22 –
ACX306BKM
3. RGB Simultaneous Sampling
The horizontal driver samples R, G and B video signals simultaneously, which requires phase matching
between the R, G and B signals to prevent the horizontal resolution from deteriorating. Thus phase matching
by an external signal delay circuit is needed before applying the video signal to the LCD panel.
Two methods are applied for the delaying procedure: Sample-and-hold and Delay circuit. These two block
diagrams are as follows.
The ACX306BKM has a right/left inversion function. The following phase relationship diagram indicates the
phase setting for right scan (RGT = high level). For left scan (RGT = low level), the phase setting should be
inverted for the B and G signals.
B
S/H
S/H
CKB
CKG
R
S/H
S/H
CKR
CKG
G
S/H
AC Amp
22
BLUE
AC Amp
21
RED
AC Amp
20
GREEN
ACX306BKM
(1) Sample-and-hold (right scan)
CKG
<Phase relationship of delaying sample-and-hold pulses> (right scan)
HCKn
CKB
CKR
CKG
B
R
Delay
Delay
AC Amp
22
BLUE
Delay
AC Amp
21
RED
AC Amp
20
GREEN
G
– 23 –
ACX306BKM
(2) Delay element (right scan)
ACX306BKM
System Configuration
+12.0V
+12.0V
+3.0V
Rext∗
PSIG
Y/color difference
Cext/Rext
RED
R/G/B
Cext∗
GREEN
BLUE
∗ See page 3 for
the value setting.
COM
HST
Zener diode
RD4.3UM
HCK1
CXA3572R
Serial data
VDDG
HCK2
LCD panel
ACX306BK
VST
1µF
VCK
VDD
DWN
EN
RGT
Zener diode
RD2.7UM
REF
VSSG
WIDE
1µF
Dedicated LED
backlight
Constant current circuit
LCD module with backlight
– 24 –
ACX306BKM
Notes on Handling
(1) Static charge prevention
Be sure to take the following protective measures. TFT-LCD panels and LED backlights are easily damaged
by static charges.
a) Use non-chargeable gloves, or simply use bare hands.
b) Use an earth-band when handling.
c) Do not touch any electrodes of a panel.
d) Wear non-chargeable clothes and conductive shoes.
e) Install grounded conductive mats on the working floor and working table.
f) Keep panels away from any charged materials.
g) Use ionized air to discharge the panels.
(2) Protection from dust and dirt
a) Operate in a clean environment.
b) When delivered, the panel surface (Polarizer) is covered by a protective sheet. Peel off the protective
sheet carefully so as not to damage the panel.
c) Do not touch the polarizer surface. The surface is easily scratched. When cleaning, use a clean-room
wiper with isopropyl alcohol. Be careful not to leave stains on the surface.
d) Use ionized air to blow dust off the panel.
(3) Module fixing method
a) The following items should be taken into account for the positioning guide design.
• The design reference edges are the upper and left edges of the panel as viewed from the front.
Design the guides using the panel frame as the reference and not the backlight.
• Set the guides on the same side of the set as the monitor window frame.
• To prevent LCD image unevenness, the guides should be the maximum package tolerance or more
so that a clasping load is not applied to the panel from the x and y directions.
• Make sure the guides do not block the panel FPC outlet and backlight lead wire outlet.
b) The guaranteed area of the polarizer is the outer circumference of 0.7mm of the effective display area
(Fig. 1). Design the monitor window frame of the set so that it is within this range including variance.
c) Set the holders on the rear of the backlight around the circumference as far from the center of the
backlight as possible. Local pressure applied to the center of the rear of the backlight for an extended
period may result in uneven luminance, so the holder pressure on the center of the backlight should be
500g/cm2 or less.
d) Connect the panel or backlight frame to GND.
e) Use a design that does not repeatedly bend or place stress on the backlight lead wires (maximum load
in the lead wire pull-out direction: 500g) as this may cause lead wire disconnection at the solder
junction on the backlight unit side. (Forced bending of 90° or more is permitted up to 2 times, and
repeated bending of 45° up to 8 times.)
– 25 –
ACX306BKM
(4) Others
a) Do not twist or bend the flexible PC board especially at the connecting region because the board is
easily deformed.
b) Do not drop the panel or backlight.
c) Do not twist or bend the panel, panel frame or backlight.
d) Keep the panel and backlight away from heat sources.
e) Do not dampen the panel or backlight with water or other solvents.
f) Avoid storage or use of the panel at high temperatures or high humidity, as this may result in damage.
Polarizer package
0.7mm
Guaranteed area
0.7mm
Effective display area
Fig. 1
– 26 –
Unit: mm
1.5
0
R1 -0.1
1.5
No.
1
2
3
4
5
6
(White)
10.88 ± 0.5
3 ± 0.5
9.5 ± 0 5
5
AWM3633 AWG28
1.84
0.5
2.1
3.94 +0.2
- 0.1
4
(Surface B)
6
3
3.1
0.5
Rear View
(32.72)
0.42
38.1 ± 0.3
37.1 ± 0.3
15.1
1
(17.2)
1.7
2
0.5
32.3
2.17
1
11.01 ± 0.5
6.6 ± 0.5
PI28A02F 1: GND, 2: Input
108 ± 3
(GND side)
(Pink)
3.3 ± 0.2
31.94 ± 0.1
(Corner portion)
22.86
(Active area)
25 ± 0.4
(Polarizer)
49.98 ± 0.5
45.38 ± 0.5
37.98 ± 0.5
24.29 ± 0.5
(16.42)
– 27 –
57.48 ± 0.5
Front View (Surface A)
26.35 (Window)
C
Model No.
ACX306BK
Corner portion (4 places)
C portion enlarged
(3.42)
(1.13)
15.52
1.13
37.1 ± 0.3
(Bending portion)
36.56 ± 0.1
(Corner portion)
34.3 (Window)
33.3 ± 0.4 (Polarizer)
31.115 (Active area)
18.55
Name
LCD panel
Backlight
Label (10.5 × 4mm)
Connector (Sumiko Tec)
Harness (Sumitomo Electric Industries)
Reflective film
77 ± 3 (+ side)
Package Outline
4
φ0.85 ± 0.05
D
12.5 ± 0.5
0.3 ± 0.05
2
Pin 1
4 ± 0.5
Pin 24
3 ± 0.15
1
Electrode
0.35
0.5 ± 0.1
P: 0.5 ± 0.02 × 23
=11.5 ± 0.03
D portion enlarged
Electrode
Note 1. Tolerance with no indication (±0.2mm)
2. Design the guaranteed area of the polarizer
within the outer circumference of 0.7mm of
the active area.
3. Mass: approximately 10.3g
ACX306BKM
Sony Corporation
2-R0.3
(0.5)