Revised May 2005 MM74HCT240 • MM74HCT244 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer General Description The MM74HCT240 and MM74HCT244 3-STATE buffers utilize advanced silicon-gate CMOS technology and are general purpose high speed inverting and non-inverting buffers. They possess high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits achieve speeds comparable to low power Schottky devices, while retaining the low power consumption of CMOS. All three devices are TTL input compatible and have a fanout of 15 LS-TTL equivalent inputs. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug-in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs. The MM74HCT240 is an inverting buffer and the MM74HCT244 is a non-inverting buffer. Each device has two active low enables (1G and 2G), and each enable independently controls 4 buffers. All inputs are protected from damage due to static discharge by diodes to VCC and Ground. Features ■ TTL input compatible ■ Typical propagation delay: 14 ns ■ 3-STATE outputs for connection to system buses ■ Low quiescent current: 80 PA ■ High output drive current: 6 mA (min) Ordering Code: Order Number Package Number MM74HCT240WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT240SJ MM74HCT240MTC MM74HCT240N MTC20 Package Description 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide MM74HCT244WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide MM74HCT244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HCT244MTC MM74HCT244N MTC20 N20A 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP, SOIC, SOP and TSSOP Top View MM74HCT240 © 2005 Fairchild Semiconductor Corporation Top View MM74HCT244 DS005365 www.fairchildsemi.com MM74HCT240 • MM74HCT244 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer February 1984 MM74HCT240 • MM74HCT244 Truth Tables MM74HCT240 H MM74HCT244 1G 1A 1Y 2G 2A 2Y 1G 1A 1Y 2G 2A 2Y L L H L L H L L L L L L H L H L L H L L H H L H H L Z H L Z H L Z H L Z H H Z H H Z H H Z H H Z HIGH Level L LOW Level Z High Impedance Logic Diagrams MM74HCT240 www.fairchildsemi.com MM74HCT244 2 Recommended Operating Conditions 0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r20 mA r35 mA r70 mA 65qC to 150qC Supply Voltage (VCC ) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Supply Voltage (VCC) DC Input or Output Voltage 600 mW S.O. Package only 500 mW Max 4.5 5.5 Units V 0 VCC V 40 85 qC 500 ns (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) Power Dissipation (PD) (Note 3) Min Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating — plastic “N” package: 12 mW/qC from 65qC to 85qC. Lead Temperature (TL) 260qC (Soldering 10 seconds) DC Electrical Characteristics VCC 5V r10% (unless otherwise specified) Symbol VIH Parameter TA Conditions 25qC Typ Minimum HIGH Level TA 40 to 85qC TA 55q to 125qC Guaranteed Limits Units 2.0 2.0 2.0 V 0.8 0.8 0.8 V Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level VIN-EE Output Voltage |IOUT | 20 PA VIH or VIL VCC VCC0.1 VCC0.1 VCC0.1 V |IOUT | 6.0 mA, VCC 4.5V 4.2 3.98 3.84 3.7 V 7.2 mA, VCC 5.5V 5.2 4.98 4.84 4.7 V |IOUT | VOL Maximum LOW Level VIN VIH or VIL Voltage |IOUT | 20 PA 0 0.1 0.1 0.1 V |IOUT | 6.0 mA, VCC 4.5V 0.2 0.26 0.33 0.4 V 7.2 mA, VCC 5.5V 0.2 |IOUT | IIN IOZ ICC Maximum Input VIN VCC or GND, Current VIH or VIL Maximum 3-STATE VOUT Output Leakage G VIH Current G VIL Maximum Quiescent VIN Supply Current IOUT VIN VCC or GND VCC or GND 0.26 0.33 0.4 V r0.05 r0.5 r1.0 PA r0.25 r2.5 r10 PA 4.0 40 160 PA 1.0 1.3 1.5 mA 0 PA 2.4V or 0.5V (Note 4) 0.6 Note 4: Measured per input. All other inputs at VCC or GND. 3 www.fairchildsemi.com MM74HCT240 • MM74HCT244 Absolute Maximum Ratings(Note 1) (Note 2) MM74HCT240 • MM74HCT244 AC Electrical Characteristics MM74HCT240, MM74HCT244 VCC Symbol tPHL, tPLH 5.0V, tr 6 ns, TA 25qC (unless otherwise specified) tf Parameter Conditions Maximum Output Typ Guaranteed Limits Units CL 45 pF 14 18 ns Maximum Output CL 45 pF 20 30 ns Enable Time RL 1 k: Maximum Output CL 5 pF 16 25 ns Disable Time RL 1 k: Propagation Delay tPZL, tPZH tPLZ, tPHZ AC Electrical Characteristics MM74HCT240, MM74HCT244 VCC Symbol tPHL, tPLH tPZH, tPZL 5.0V r 10%, tr Parameter tTHL, tTLH TA Conditions 25qC Typ TA 40 to 85qC TA 55q to 125qC Guaranteed Limits Units Maximum Output CL 50 pF 14 20 25 30 ns Propagation Delay CL 150 pF 20 28 35 42 ns Maximum Output RL 1 k: Enable Time tPHZ, tPLZ tf 6 ns (unless otherwise specified) Maximum Output RL 1 k: Disable Time CL 50 pF Maximum Output CL 50 pF CL 50 pF 21 30 38 45 ns CL 150 pF 26 42 53 63 ns 16 25 32 38 ns 6 12 15 18 ns 10 15 15 15 pF 15 20 20 20 pF Rise and Fall Time CIN Maximum Input Capacitance COUT Maximum Output Capacitance CPD Power Dissipation Capacitance (Note 5) (per buffer) G V CC, G GND 5 pF G GND, G VCC 90 pF Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC f I CC. www.fairchildsemi.com C PD VCC2 f ICC VCC, and the no load dynamic current consumption, 4 MM74HCT240 • MM74HCT244 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com MM74HCT240 • MM74HCT244 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D www.fairchildsemi.com 6 MM74HCT240 • MM74HCT244 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com MM74HCT240 • MM74HCT244 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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