ON NL17SZ74 Single d flip flop Datasheet

NL17SZ74
Single D Flip Flop
The NL17SZ74 is a high performance, full function Edge triggered
D Flip Flop, with all the features of a standard logic device such as the
74LCX74.
•
•
•
•
•
•
•
Extremely High Speed: tPD 2.6 ns (typical) at VCC = 5 V
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Designed for 1.65 V to 5.5 V VCC Operation
5 V Tolerant Inputs – Interface Capability with 5 V TTL Logic
PR
LVTTL Compatible
LVCMOS Compatible
7
24 mA Balanced Output Sink and Source Capability
Near Zero Static Supply Current (10 µA) Substantially Reduces
System Power Requirements
Replacement for NC7SZ74
•
• Tiny Ultra Small Package Only 2.1 X 3.0 mm
• High ESD Ratings: 2000 V Human Body Model
•
D
2
5
Q
CP
1
3
Q
6
VCC = 8, GND = 4
CLR
High ESD Ratings: 200 V Machine Model
Chip Complexity: FET = 64
Figure 1. Logic Diagram
TRUTH TABLE
Inputs
Outputs
PR
CLR
CP
D
Q
Q
Operating Mode
L
H
L
H
L
L
X
X
X
X
X
X
H
L
H
L
H
H
Asynchronous Set
Asynchronous Clear
Undetermined
H
H
H
H
↑
↑
h
l
H
L
L
H
Load and Read Register
H
H
↑
X
NC
NC
Hold
H
h
L
l
NC
X
↑
↑
US8
CASE 493
US SUFFIX
MARKING DIAGRAM
= High Voltage Level
= High Voltage Level One Setup Time Prior to the Low–to–High Clock Transition
= Low Voltage Level
= Low Voltage Level One Setup Time Prior to the Low–to–High Clock Transition
= No Change
= High or Low Voltage Level and Transitions are Acceptable
= Low–to–High Transition
= Not a Low–to–High Transition
MH D
MH = Specific Device Code
D
= Date Code
For ICC reasons, DO NOT FLOAT Inputs
PINOUT
CP
D
Q
GND
1
8
7
6
5
2
3
4
VCC
PR
CLR
Q
ORDERING INFORMATION
Device
NL17SZ74US
 Semiconductor Components Industries, LLC, 2002
May, 2002 – Rev. 2
1
Package
Shipping
US8
3000/Tape & Reel
Publication Order Number:
NL17SZ74/D
NL17SZ74
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage
–0.5 to +7.0
V
VI
DC Input Voltage
–0.5 to +7.0
V
VO
DC Output Voltage – Output in High or Low State (Note 1)
–0.5 to VCC +0.5
V
IIK
DC Input Diode Current
VI < GND
–50
mA
IOK
DC Output Diode Current
VO < GND
–50
mA
IO
DC Output Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
–65 to +150
°C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
260
°C
TJ
Junction Temperature Under Bias
+150
°C
JA
Thermal Resistance (Note 2)
250
°C/W
PD
Power Dissipation in Still Air at 85°C
250
mW
MSL
Moisture Sensitivity
FR
Flammability Rating
Oxygen Index: 28 to 34
VESD
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
Level 1
UL 94 V–0 @ 0.125 in
>2000
>200
N/A
V
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
1. IO absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm X 1 inch, 2 ounce copper trace with no air flow.
3. Tested to EIA/JESD22–A114–A.
4. Tested to EIA/JESD22–A115–A.
5. Tested to JESD22–C101–A.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
1.65
1.5
5.5
5.5
V
VCC
Supply Voltage
Operating
Data Retention Only
VI
Input Voltage
(Note 6)
0
5.5
V
VO
Output Voltage
(HIGH or LOW State)
0
VCC
V
TA
Operating Free–Air Temperature
–40
+85
°C
t/∆V
Input Transition Rise or Fall Rate
0
0
0
20
10
5.0
ns/V
VCC = 2.5 V ±0.2 V
VCC = 3.0 V ±0.3 V
VCC = 5.0 V ±0.5 V
6. Unused inputs may not be left open. All inputs must be tied to a high–logic voltage level or a low–logic input voltage level.
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2
NL17SZ74
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
VIH
High–Level Input Voltage
VIL
Low–Level Input Voltage
Condition
40C TA 85C
TA = 25C
VCC
(V)
Min
Typ
Max
Min
1.65
0.75 VCC
0.75 VCC
2.3 to 5.5
0.7 VCC
0.7 VCC
Max
V
1.65
0.25 VCC
0.25 VCC
2.3 to 5.5
0.3 VCC
0.3 VCC
VOH
High Level Out
High–Level
Output
ut Voltage
VIN = VIL or VIL
IOH = 100 A
IOH = –3
3 mA
IOH = –8
8 mA
IOH = –12
12 mA
IOH = –16
16 mA
IOH = –24
24 mA
IOH = –32 mA
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
VOL
Low Level Output
Low–Level
Out ut Voltage
VIN = VIH
IOL = 100 A
IOL = 3 mA
IOL = 8 mA
IOL = 12 mA
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
1.65 to 5.5
1.65
2.3
2.7
3.0
3.0
4.5
IIN
Input Leakage Current
VIN = VCC or GND
IOFF
Power off Input
Leakage Current
5.5V or VIN = GND
ICC
Quiescent Supply Current
VIN = VCC or GND
VCC – 0.1
1.29
1.9
2.2
2.4
2.3
3.8
VCC
1.52
2.1
2.4
2.7
2.5
4.0
VCC – 0.1
1.29
1.9
2.2
2.4
2.3
3.8
V
V
0.1
0.24
0.3
0.4
0.4
0.55
0.55
0.1
0.24
0.3
0.4
0.4
0.55
0.55
V
5.5
0.1
1.0
A
0
1.0
10
A
5.5
1.0
10
A
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3
0.008
0.10
0.12
0.15
0.19
0.30
0.30
Unit
NL17SZ74
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0 ns)
TA = 25°C
Symbol
fMAX
Parameter
Maximum Clock
F
Frequency
(50% Duty Cycle)
(Waveform 1)
VCC (V)
1.8 ± 0.15
2.5 ± 0.2
3.3 ± 0.3
Test Conditions
CL = 15 pF
RD = 1 M
S1 = Open
5.0 ± 0.5
tPLH,
tPHL
Propagation Delay,
t Q or Q
CP to
(Waveform 1)
1.8 ± 0.15
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
tPLH,
tPHL
Propagation Delay,
PR or CLR tto Q
or Q
(Waveform 2)
1.8 ± 0.15
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
tS
Setup Time,
D to
t CP
(Waveform 1)
1.8 ± 0.15
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
tH
Hold Time,
D to
t CP
(Waveform 1)
1.8 ± 0.15
2.5 ± 0.2
3.3 ± 0.3
200
250
250
CL = 50 pF,
RD = 500 , S1 = O
Open
175
175
CL = 15 pF
RD = 1 M
S1 = Open
2.5
6.5
12.5
2.5
13
1.5
3.8
7.5
1.5
8.0
1.0
2.8
6.5
1.0
7.0
0.8
2.2
4.5
0.8
5.0
CL = 50 pF,
RD = 500 , S1 = O
Open
1.0
3.4
7.0
1.0
7.5
1.0
2.6
5.0
1.0
5.5
CL = 15 pF
RD = 1 M
S1 = Open
2.5
6.5
14
2.5
14.5
1.5
3.8
9.0
1.5
9.5
1.0
2.8
6.5
1.0
7.0
0.8
2.2
5.0
0.8
5.5
CL = 50 pF,
RD = 500 , S1 = O
Open
1.0
3.4
7.0
1.0
7.5
1.0
2.6
5.0
1.0
5.5
CL = 15 pF
RD = 1 M
S1 = Open
6.5
6.5
3.5
3.5
2.0
2.0
1.5
1.5
CL = 50 pF,
RD = 500 , S1 = O
Open
2.0
2.0
1.5
1.5
CL = 15 pF
RD = 1 M
S1 = Open
0.5
0.5
0.5
0.5
0.5
0.5
5.0 ± 0.5
tW
Pulse Width,
CP CLR,
CP,
CLR PR
(Waveform 3)
1.8 ± 0.15
2.5 ± 0.2
3.3 ± 0.3
5.0 ± 0.5
tREC
Recover Time
PR CLR tto CP
PR;
(Waveform 3)
1.8 ± 0.15
2.5 ± 0.2
3.3 ± 0.3
0.5
0.5
0.5
0.5
0.5
0.5
CL = 15 pF
RD = 1 M
S1 = Open
6.0
6.0
4.0
4.0
3.0
3.0
2.0
2.0
CL = 50 pF,
RD = 500 , S1 = O
Open
3.0
3.0
2.0
2.0
CL = 15 pF
RD = 1 M
S1 = Open
8.0
8.0
4.5
4.5
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
200
CL = 50 pF,
RD = 500 , S1 = O
Open
5.0 ± 0.5
3.3 ± 0.3
200
CL = 50 pF,
RD = 500 , S1 = O
Open
Unit
MHz
200
5.0 ± 0.5
3.3 ± 0.3
Max
150
5.0 ± 0.5
3.3 ± 0.3
Min
150
5.0 ± 0.5
3.3 ± 0.3
TA = –40 to 85°C
Max
75
5.0 ± 0.5
3.3 ± 0.3
Typ
75
5.0 ± 0.5
3.3 ± 0.3
Min
ns
ns
ns
ns
ns
MHz
7. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC/2 (per flip–flop). CPD is used to determine the
no–load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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4
NL17SZ74
CAPACITANCE (Note 8)
Typical
Unit
CIN
Input Capacitance
VCC = 5.5 V
7.0
pF
COUT
Output Capacitance
VCC = 5.5 V
7.0
pF
CPD
Power Dissipation Capacitance (Note 9)
Frequency = 10 MHz
VCC = 3.3 V
VCC = 5.0 V
16
21
pF
Symbol
Parameter
Condition
8. TA = +25°C, f = 1 MHz
9. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current consumption (I CCD) at
no output loading and operating at 50% duty cycle. (See Figure 2) C PD is related to ICCD dynamic operating current by the expression:
ICCD = CPD VCC fin + ICC(static).
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5
NL17SZ74
Vcc
D
50%
0V
th
ts
Vcc
tw
CP
50%
0V
fmax
tPLH, tPHL
VOH
Q,
Q
50%
VOL
WAVEFORM 1 – PROPAGATION DELAYS, SETUP AND HOLD TIMES
tR = tF = 3.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Vcc
PR
50%
0V
Vcc
CLR
50%
0V
tPLH
tPHL
Q
50%
50%
VOL
VOH
tPLH
Q
50%
50%
tPHL
WAVEFORM 2 – PROPAGATION DELAYS
tR = tF = 3.0 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Vcc
tw
PR, CLR
50%
0V
trec
Vcc
50%
CP
tw
0V
WAVEFORM 3 – RECOVERY TIME
tR = tF = 3.0 ns from 10% to 90%; f = 1 MHz; tw = 500 ns
Output Reg: VOL ≤ 0.8 V, VOH ≥ 2.0 V
Figure 2. AC Waveforms
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6
NL17SZ74
VCC
PULSE
GENERATOR
DUT
RT
CL
RL
Figure 3. Test Circuit
DEVICE ORDERING INFORMATION
Device Nomenclature
Device Order
Number
NL17SZ74US
Logic
Circuit
Indicator
No. of
Gates per
Package
Temp
Range
Identifier
Technology
Device
Function
Package
Suffix
Package
Type
Tape and
Reel Size
NL
1
7
SZ
74
US
US8
178 mm, 3000 Unit
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7
NL17SZ74
CAVITY
TAPE
TOP TAPE
TAPE TRAILER
(Connected to Reel Hub)
NO COMPONENTS
160 mm MIN
COMPONENTS
TAPE LEADER
NO COMPONENTS
400 mm MIN
DIRECTION OF FEED
Figure 4. Tape Ends for Finished Goods
TAPE DIMENSIONS mm
4.00
1.50 TYP
4.00
2.00
1.75
3.50 0.25
0.30
8.00 +
– 0.10
1
1.00 ± 0.25 TYP
DIRECTION OF FEED
Figure 5. US8 Reel Configuration/Orientation
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8
NL17SZ74
t MAX
1.5 mm MIN
(0.06 in)
A
13.0 mm 0.2 mm
(0.512 in 0.008 in)
50 mm MIN
(1.969 in)
20.2 mm MIN
(0.795 in)
FULL RADIUS
G
Figure 6. Reel Dimensions
REEL DIMENSIONS
Tape Size
T and R Suffix
A Max
G
t Max
8 mm
US
178 mm
(7 in)
8.4 mm, + 1.5 mm, –0.0
(0.33 in + 0.059 in, –0.00)
14.4 mm
(0.56 in)
DIRECTION OF FEED
BARCODE LABEL
POCKET
Figure 7. Reel Winding Direction
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9
HOLE
NL17SZ74
PACKAGE DIMENSIONS
US8
US SUFFIX
CASE 493–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS
3. DIMENSION A" DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR. MOLD
FLASH. PROTRUSION AND GATE BURR SHALL
NOT EXCEED 0.140 MM (0.0055") PER SIDE.
4. DIMENSION B" DOES NOT INCLUDE
INTER-LEAD FLASH OR PROTRUSION.
INTER-LEAD FLASH AND PROTRUSION SHALL
NOT E3XCEED 0.140 (0.0055") PER SIDE.
5. LEAD FINISH IS SOLDER PLATING WITH
THICKNESS OF 0.0076-0. 0203 MM. (300-800
mINCH).
6. ALL TOLERANCE UNLESS OTHERWISE
SPECIFIED ±0.0508 (0.0002").
–X–
A
8
J
–Y–
5
DETAIL E
B
L
1
4
R
S
G
P
U
C
–T–
SEATING
PLANE
H
0.10 (0.004) T
K
D
N
0.10 (0.004)
M
T X Y
R 0.10 TYP
V
M
F
DETAIL E
3.8
0.5 TYP
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
1.8 TYP
1.0
http://onsemi.com
10
0.3 TYP
(mm)
DIM
A
B
C
D
F
G
H
J
K
L
M
N
P
R
S
U
V
MILLIMETERS
MIN
MAX
1.90
2.10
2.20
2.40
0.60
0.90
0.17
0.25
0.20
0.35
0.50 BSC
0.40 REF
0.10
0.18
0.00
0.10
3.00
3.20
0
6
5
10 0.28
0.44
0.23
0.33
0.37
0.47
0.60
0.80
0.12 BSC
INCHES
MIN
MAX
0.075
0.083
0.087
0.094
0.024
0.035
0.007
0.010
0.008
0.014
0.020 BSC
0.016 REF
0.004
0.007
0.000
0.004
0.118
0.126
0
6
5
10 0.011
0.017
0.009
0.013
0.015
0.019
0.024
0.031
0.005 BSC
NL17SZ74
Notes
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11
NL17SZ74
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make
changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or
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12
NL17SZ74/D