ISSI IS41LV16400-50TI 4mx16 (64-mbit) dynamic ram with edo page mode Datasheet

ISSI
®
IS41LV16400
4M x 16 (64-MBIT) DYNAMIC RAM
WITH EDO PAGE MODE
NOVEMBER 1999
FEATURES
DESCRIPTION
• Extended Data-Out (EDO) Page Mode access cycle
The ISSI IS41LV16400 is 4,194,304 x 16-bit high-performance CMOS Dynamic Random Access Memories.
These devices offer an accelerated cycle access called
EDO Page Mode. EDO Page Mode allows 1,024 random
accesses within a single row with access cycle time as
short as 20 ns per 16-bit word. The Byte Write control, of
upper and lower byte, makes the IS41LV16400 ideal for
use in 16-bit wide data bus systems.
• TTL compatible inputs and outputs; tristate I/O
• Refresh Interval: 4,096 cycles / 64 ms
• Auto refresh Mode: RAS-Only, CAS-before-RAS
(CBR), and Hidden
• Low Standby power dissipation:
– 1.8mW(max) CMOS Input Level
• Single power supply: 3.3V ± 10%
• Byte Write and Byte Read operation via two CAS
• Extended Temperature Range -30oC to 85oC
These features make the S41LV16400 ideally suited for
high-bandwidth graphics, digital signal processing,
high-performance computing systems, and peripheral
applications.
• Industrail Temperature Range -40 C to 85 C
The IS41LV16400 is packaged in a 50-pin TSOP (Type II).
JEDEC standard pinout.
PIN CONFIGURATION
PIN DESCRIPTIONS
o
o
50-Pin TSOP (Type II)
A0-A11
Address Inputs
I/O0-15
Data Inputs/Outputs
VCC
1
50
GND
I/O0
2
49
I/O15
WE
Write Enable
I/O1
3
48
I/O14
OE
Output Enable
I/O2
4
47
I/O13
I/O3
5
46
I/O12
RAS
Row Address Strobe
VCC
6
45
GND
UCAS
Upper Column Address Strobe
I/O4
7
44
I/O11
I/O5
8
43
I/O10
LCAS
Lower Column Address Strobe
I/O6
9
42
I/O9
Vcc
Power
I/O7
10
41
I/O8
NC
11
40
NC
GND
Ground
VCC
12
39
GND
NC
No Connection
W
13
38
LCAS
RAS
14
37
UCAS
NC
15
36
OE
NC
16
35
NC
NC
17
34
NC
NC
18
33
NC
Parameter
-50
-60
Unit
A0
19
32
A11
A1
20
31
A10
Max. RAS Access Time (tRAC)
50
60
ns
A2
21
30
A9
Max. CAS Access Time (tCAC)
13
15
ns
A3
22
29
A8
A4
23
28
A7
Max. Column Address Access Time (tAA)
25
30
ns
A5
24
27
A6
Min. EDO Page Mode Cycle Time (tPC)
20
25
ns
VCC
25
26
GND
Min. Read/Write Cycle Time (tRC)
84
104
ns
KEY TIMING PARAMETERS
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 1999, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
1
ISSI
IS41LV16400
®
FUNCTIONAL BLOCK DIAGRAM
OE
WE
LCAS
UCAS
CAS
CLOCK
GENERATOR
WE
CONTROL
LOGICS
CAS
WE
OE
CONTROL
LOGIC
OE
RAS
CLOCK
GENERATOR
RAS
DATA I/O BUS
COLUMN DECODERS
SENSE AMPLIFIERS
ADDRESS
BUFFERS
A0-A11
2
ROW DECODER
REFRESH
COUNTER
DATA I/O BUFFERS
RAS
I/O0-I/O15
MEMORY ARRAY
4,194,304 x 16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
ISSI
IS41LV16400
®
TRUTH TABLE
Function
Standby
Read: Word
Read: Lower Byte
RAS
H
L
L
LCAS
H
L
L
UCAS
H
L
H
WE
X
H
H
OE
X
L
L
Address tR/tC
X
ROW/COL
ROW/COL
Read: Upper Byte
L
H
L
H
L
ROW/COL
Write: Word (Early Write)
Write: Lower Byte (Early Write)
L
L
L
L
L
H
L
L
X
X
ROW/COL
ROW/COL
Write: Upper Byte (Early Write)
L
H
L
L
X
ROW/COL
L
L
L
L
L
L
L
L
L→H→L
L→H→L
L
→
H L
L
→
H L
H→L
L→H
H→L
H→L
H→L
H→L
L
L
H
L
L
→
H L
H→L
L→H
H→L
H→L
H→L
H→L
L
L
H
L
H→L
H
H
H
L
L
H→L
H→L
H
L
X
X
L→H
L
L
L
X
X
L→H
L→H
L
X
X
X
ROW/COL
ROW/COL
NA/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
NA/COL
ROW/COL
ROW/COL
ROW/NA
X
Read-Write(1,2)
EDO Page-Mode Read(2) 1st Cycle:
2nd Cycle:
Any Cycle:
EDO Page-Mode Write(1) 1st Cycle:
2nd Cycle:
EDO Page-Mode(1,2)
1st Cycle:
Read-Write
2nd Cycle:
Hidden Refresh
Read(2)
Write(1,3)
RAS-Only Refresh
CBR Refresh(4)
I/O
High-Z
DOUT
Lower Byte, DOUT
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DOUT
DIN
Lower Byte, DIN
Upper Byte, High-Z
Lower Byte, High-Z
Upper Byte, DIN
DOUT, DIN
DOUT
DOUT
DOUT
DIN
DIN
DOUT, DIN
DOUT, DIN
DOUT
DOUT
High-Z
High-Z
Notes:
1. These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).
2. These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).
3. EARLY WRITE only.
4. At least one of the two CAS signals must be active (LCAS or UCAS).
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
3
ISSI
IS41LV16400
®
FUNCTIONAL DESCRIPTION
Refresh Cycle
The IS41LV16400 is a CMOS DRAM optimized for
high-speed bandwidth, low power applications. During
READ or WRITE cycles, each bit is uniquely addressed
through the 22 address bits: 12 row address bits (A0~A11)
and 10 column address bits (A0~A9). The row address is
latched by the Row Address Strobe (RAS). The column
address is latched by the Column Address Strobe (CAS).
RAS is used to latch the first twelve bits and CAS is used
the latter ten bits.
To retain data, 4,096 refresh cycles are required in each
64 ms period. There are two ways to refresh the memory.
The IS41LV16400 has two CAS controls, LCAS and
UCAS. The LCAS and UCAS inputs internally generates
a CAS signal functioning in an identical manner to the
single CAS input on the other 4M x 16 DRAMs. The key
difference is that each CAS controls its corresponding
I/O tristate logic (in conjunction with OE and WE and
RAS). LCAS controls I/O0 through I/O7 and UCAS
controls I/O8 through I/O15.
The IS41LV16400 CAS function is determined by the first
CAS (LCAS or UCAS) transitioning LOW and the last
transitioning back HIGH. The two CAS controls give the
IS41LV16400 both BYTE READ and BYTE WRITE cycle
capabilities.
Memory Cycle
A memory cycle is initiated by bring RAS LOW and it is
terminated by returning both RAS and CAS HIGH. To
ensures proper device operation and data integrity any
memory cycle, once initiated, must not be ended or
aborted before the minimum tRAS time has expired. A new
cycle must not be initiated until the minimum precharge
time tRP, tCP has elapsed.
Read Cycle
A read cycle is initiated by the falling edge of CAS or OE,
whichever occurs last, while holding WE HIGH. The
column address must be held for a minimum time
specified by tAR. Data Out becomes valid only when tRAC,
tAA, tCAC and tOEA are all satisfied. As a result, the access
time is dependent on the timing relationships between
these parameters.
Write Cycle
A write cycle is initiated by the falling edge of CAS and
WE, whichever occurs last. The input data must be valid
at or before the falling edge of CAS or WE, whichever
occurs last.
4
1. By clocking each of the 4,096 row addresses (A0
through A11) with RAS at least once every 64 ms. Any
read, write, read-modify-write or RAS-only cycle
refreshes the addressed row.
2. Using a CAS-before-RAS refresh cycle. CAS-before-RAS
refresh is activated by the falling edge of RAS, while
holding CAS LOW. In CAS-before-RAS refresh cycle,
an internal 12-bit counter provides the row addresses
and the external address inputs are ignored.
CAS-before-RAS is a refresh-only mode and no data
access or device selection is allowed. Thus, the output
remains in the High-Z state during the cycle.
Extended Data Out Page Mode
EDO page mode operation permits all 1,024 columns
within a selected row to be randomly accessed at a high
data rate.
In EDO page mode read cycle, the data-out is held to the
next CAS cycle’s falling edge, instead of the rising edge.
For this reason, the valid data output time in EDO page
mode is extended compared with the fast page mode. In
the fast page mode, the valid data output time becomes
shorter as the CAS cycle time becomes shorter. Therefore, in EDO page mode, the timing margin in read cycle
is larger than that of the fast page mode even if the CAS
cycle time becomes shorter.
In EDO page mode, due to the extended data function, the
CAS cycle time can be shorter than in the fast page mode
if the timing margin is the same.
The EDO page mode allows both read and write
operations during one RAS cycle, but the performance is
equivalent to that of the fast page mode in that case.
Power-On
After application of the VCC supply, an initial pause of
200 µs is required followed by a minimum of eight
initialization cycles (any combination of cycles containing
a RAS signal).
During power-on, it is recommended that RAS track with
VCC or be held at a valid VIH to avoid current surges.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
ISSI
IS41LV16400
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
VT
VCC
IOUT
PD
TA
TSTG
Parameters
Voltage on Any Pin Relative to GND
Supply Voltage
Output Current
Power Dissipation
Commercial Operation Temperature
Extended Temperature
Industrail Temperature
Storage Temperature
Rating
–0.5 to +4.6
–0.5 to +4.6
50
1
0 to +70
–30 to +85
–40 to +85
–55 to +125
Unit
V
V
mA
W
°C
°C
°C
°C
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)
Symbol
VCC
VIH
VIL
TA
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Commercial Ambient Temperature
Extended Ambient Temperature
Industrail Ambient Temperature
Min.
3.0
2.0
–0.3
0
–30
–40
Typ.
3.3
—
—
—
—
—
Max.
3.6V
VCC + 0.3
0.8
70
85
85
Unit
V
V
V
°C
°C
°C
CAPACITANCE(1,2)
Symbol
Parameter
CIN1
CIN2
CIO
Input Capacitance: A0-A11
Input Capacitance: RAS, UCAS, LCAS, WE, OE
Data Input/Output Capacitance: I/O0-I/O15
Max.
Unit
5
7
7
pF
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
5
ISSI
IS41LV16400
®
ELECTRICAL CHARACTERISTICS(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol Parameter
IIL
Input Leakage Current
IIO
Output Leakage Current
VOH
VOL
I CC1
Output High Voltage Level
Output Low Voltage Level
Standby Current: TTL
I CC2
I CC3
Standby Current: CMOS
Operating Current:
Random Read/Write(2,3,4)
Average Power Supply Current
Operating Current:
EDO Page Mode(2,3,4)
Average Power Supply Current
Refresh Current:
RAS-Only(2,3)
Average Power Supply Current
Refresh Current:
CBR(2,3,5)
Average Power Supply Current
I CC4
I CC5
I CC6
Test Condition
Speed
Min.
Max.
Unit
–5
5
µA
–5
5
µA
—
0.4
1
2
2
0.5
160
145
V
V
mA
mA
mA
mA
mA
Any input 0V ≤ VIN ≤ Vcc
Other inputs not under test = 0V
Output is disabled (Hi-Z)
0V ≤ VOUT ≤ Vcc
IOH = –2.0 mA
IOL = 2.0 mA
RAS, LCAS, UCAS ≥ VIH Commerical
Extended
Industrial
RAS, LCAS, UCAS ≥ VCC – 0.2V
RAS, LCAS, UCAS,
Address Cycling, tRC = tRC (min.)
-50
-60
2.4
—
—
—
—
—
—
—
RAS = VIL, LCAS, UCAS,
Cycling tPC = tPC (min.)
-50
-60
—
—
90
80
mA
RAS Cycling, LCAS, UCAS ≥ VIH
tRC = tRC (min.)
-50
-60
—
—
160
145
mA
RAS, LCAS, UCAS Cycling
tRC = tRC (min.)
-50
-60
—
—
160
145
mA
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each EDO page cycle.
5. Enables on-chip refresh and address counters.
319 Ω
AC TEST CONDITIONS
Output load: One TTL Load and 50 pF
Input timing reference levels: VIH = 2.0V, VIL = 0.8V
Output timing reference levels: VOH = 2.0V, VOL = 0.8V
3.3V
OUTPUT
50 pF
Including
jig and
scope
6
353 Ω
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
ISSI
IS41LV16400
®
AC CHARACTERISTICS(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
-50
Symbol
Parameter
t RC
t RAC
t CAC
tAA
tRAS
t RP
tCAS
t CP
t CSH
t RCD
tASR
t RAH
tASC
t CAH
t AR
Random READ or WRITE Cycle Time
Access Time from RAS(6, 7)
Access Time from CAS(6, 8, 15)
Access Time from Column-Address(6)
RAS Pulse Width
RAS Precharge Time
CAS Pulse Width(26)
CAS Precharge Time(9, 25)
CAS Hold Time (21)
RAS to CAS Delay Time(10, 20)
Row-Address Setup Time
Row-Address Hold Time
Column-Address Setup Time(20)
Column-Address Hold Time(20)
Column-Address Hold Time
(referenced to RAS)
RAS to Column-Address Delay Time(11)
Column-Address to RAS Lead Time
RAS to CAS Precharge Time
RAS Hold Time(27)
RAS Hold Time from CAS Precharge
CAS to Output in Low-Z(15, 29)
CAS to RAS Precharge Time(21)
Output Disable Time(19, 28, 29)
Output Enable Time(15, 16)
Output Enable Data Delay (Write)
OE HIGH Hold Time from CAS HIGH
OE HIGH Pulse Width
OE LOW to CAS HIGH Setup Time
Read Command Setup Time(17, 20)
Read Command Hold Time
(referenced to RAS)(12)
Read Command Hold Time
(referenced to CAS)(12, 17, 21)
Write Command Hold Time(17, 27)
Write Command Hold Time
(referenced to RAS)(17)
Write Command Pulse Width(17)
t RAD
t RAL
t RPC
t RSH
t RHCP
tCLZ
t CRP
tOD
tOE
tOED
tOEHC
tOEP
tOES
t RCS
t RRH
t RCH
t WCH
t WCR
tWP
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
-60
Min.
Max.
Min.
Max.
Units
84
—
—
—
50
30
8
9
38
12
0
8
0
8
30
—
50
13
25
10K
—
10K
—
—
37
—
—
—
—
—
104
—
—
—
60
40
10
9
40
14
0
10
0
10
40
—
60
15
30
10K
—
10K
—
—
45
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
25
5
8
37
0
5
3
—
20
5
10
5
0
0
25
—
—
—
—
—
—
15
13
—
—
—
—
—
—
12
30
5
10
37
0
5
3
—
20
5
10
5
0
0
30
—
—
—
—
—
—
15
15
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
—
0
—
ns
8
40
—
—
10
50
—
—
ns
ns
8
—
10
—
ns
7
ISSI
IS41LV16400
®
AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
tWPZ
t RWL
t CWL
tWCS
t DHR
t ACH
WE Pulse Widths to Disable Outputs
Write Command to RAS Lead Time(17)
Write Command to CAS Lead Time(17, 21)
Write Command Setup Time(14, 17, 20)
Data-in Hold Time (referenced to RAS)
Column-Address Setup Time to CAS
Precharge during WRITE Cycle
OE Hold Time from WE during
READ-MODIFY-WRITE cycle(18)
Data-In Setup Time(15, 22)
Data-In Hold Time(15, 22)
READ-MODIFY-WRITE Cycle Time
RAS to WE Delay Time during
READ-MODIFY-WRITE Cycle(14)
CAS to WE Delay Time(14, 20)
Column-Address to WE Delay Time(14)
EDO Page Mode READ or WRITE
Cycle Time(24)
RAS Pulse Width in EDO Page Mode
Access Time from CAS Precharge(15)
EDO Page Mode READ-WRITE
Cycle Time(24)
Data Output Hold after CAS LOW
Output Buffer Turn-Off Delay from
CAS or RAS(13,15,19, 29)
Output Disable Delay from WE
Last CAS going LOW to First CAS
returning HIGH(23)
CAS Setup Time (CBR REFRESH)(30, 20)
CAS Hold Time (CBR REFRESH)(30, 21)
OE Setup Time prior to RAS during
HIDDEN REFRESH Cycle
Refresh Period (4,096 Cycles)
Transition Time (Rise or Fall)(2, 3)
tOEH
t DS
t DH
t RWC
t RWD
t CWD
tAWD
t PC
t RASP
t CPA
t PRWC
t COH
tOFF
tWHZ
t CLCH
t CSR
t CHR
t ORD
tREF
tT
8
-50
Min.
Max.
-60
Min.
Max.
Units
10
13
8
0
39
15
—
—
—
—
—
—
10
15
10
0
39
15
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
8
—
10
—
ns
0
8
108
64
—
—
—
—
0
10
133
77
—
—
—
—
ns
ns
ns
ns
26
39
20
—
—
—
32
47
25
—
—
—
ns
ns
ns
50
—
56
100K
30
—
60
—
68
100K
35
—
ns
ns
ns
5
1.6
—
12
5
1.6
—
15
ns
ns
3
10
10
—
3
10
10
—
ns
ns
5
8
0
—
—
—
5
10
0
—
—
—
ns
ns
ns
—
1
64
50
—
1
64
50
ms
ns
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
IS41LV16400
ISSI
®
Notes:
1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device
operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.
2. VIH (MIN) and VIL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between VIH and
VIL (or between VIL and VIH) and assume to be 1 ns for all inputs.
3. In addition to meeting the transition rate specification, all input signals must transit between VIH and VIL (or between VIL and VIH) in a
monotonic manner.
4. If CAS and RAS = VIH, data output is High-Z.
5. If CAS = VIL, data output may contain data from the last valid READ cycle.
6. Measured with a load equivalent to one TTL gate and 50 pF.
7. Assumes that tRCD ≤ tRCD (MAX). If tRCD is greater than the maximum recommended value shown in this table, tRAC will increase by
the amount that tRCD exceeds the value shown.
8. Assumes that tRCD ≥ tRCD (MAX).
9. If CAS is LOW at the falling edge of RAS, data out will be maintained from the previous cycle. To initiate a new cycle and clear the data
output buffer, CAS and RAS must be pulsed for tCP.
10. Operation with the tRCD (MAX) limit ensures that tRAC (MAX) can be met. tRCD (MAX) is specified as a reference point only; if tRCD is
greater than the specified tRCD (MAX) limit, access time is controlled exclusively by tCAC.
11. Operation within the tRAD (MAX) limit ensures that tRCD (MAX) can be met. tRAD (MAX) is specified as a reference point only; if tRAD is
greater than the specified tRAD (MAX) limit, access time is controlled exclusively by tAA.
12. Either tRCH or tRRH must be satisfied for a READ cycle.
13. tOFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL.
14. tWCS, tRWD, tAWD and tCWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If tWCS ≥ tWCS
(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If tRWD ≥ tRWD (MIN),
tAWD ≥ tAWD (MIN) and tCWD ≥ tCWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected
cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to VIH) is
indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE-controlled) cycle.
15. Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS.
16. During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATE
WRITE or READ-MODIFY-WRITE is not possible.
17. Write command is defined as WE going low.
18. LATE WRITE and READ-MODIFY-WRITE cycles must have both tOD and tOEH met (OE HIGH during WRITE cycle) in order to ensure
that the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and
OE is taken back to LOW after tOEH is met.
19. The I/Os are in open during READ cycles once tOD or tOFF occur.
20. The first χCAS edge to transition LOW.
21. The last χCAS edge to transition HIGH.
22. These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READMODIFY-WRITE cycles.
23. Last falling χCAS edge to first rising χCAS edge.
24. Last rising χCAS edge to next cycle’s last rising χCAS edge.
25. Last rising χCAS edge to first falling χCAS edge.
26. Each χCAS must meet minimum pulse width.
27. Last χCAS to go LOW.
28. I/Os controlled, regardless UCAS and LCAS.
29. The 3 ns minimum is a parameter guaranteed by design.
30. Enables on-chip refresh and address counters.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
9
ISSI
IS41LV16400
®
READ CYCLE
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
tRRH
UCAS/LCAS
tAR
tRAD
tASR
ADDRESS
tRAH
tRAL
tCAH
tASC
Row
Column
Row
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLC
I/O
tOFF(1)
Open
Open
Valid Data
tOE
tOD
OE
tOES
Undefined
Don’t Care
Note:
1. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
10
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
ISSI
IS41LV16400
®
EARLY WRITE CYCLE (OE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
UCAS/LCAS
tAR
tRAD
tRAH
tASR
ADDRESS
tRAL
tCAH
tACH
tASC
Row
Column
Row
tCWL
tRWL
tWCR
tWCS
tWCH
tWP
WE
tDHR
tDS
I/O
tDH
Valid Data
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
11
ISSI
IS41LV16400
®
READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)
tRWC
tRAS
tRP
RAS
tCSH
tCRP
tRSH
tCAS tCLCH
tRCD
UCAS/LCAS
tAR
tRAD
tASR
tRAH
tRAL
tCAH
tASC
tACH
ADDRESS
Row
Column
Row
tRWD
tCWL
tRWL
tCWD
tRCS
tAWD
tWP
WE
tAA
tRAC
tCAC
tCLZ
I/O
tDS
Open
Valid DOUT
tOE
tDH
Valid DIN
Open
tOD
tOEH
OE
Undefined
Don’t Care
12
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
ISSI
IS41LV16400
®
EDO-PAGE-MODE READ CYCLE
tRASP
tRP
RAS
tCSH
tCRP
tPC(1)
tCAS,
tCLCH
tRCD
tCAS,
tCLCH
tCP
tCP
tRSH
tCAS,
tCLCH
tCP
UCAS/LCAS
tAR
tRAD
tASR
ADDRESS
tASC
tCAH tASC
Row
Column
tRAL
tCAH
tCAH tASC
Column
Column
Row
tRAH
tRRH
tRCS
tRCH
WE
tAA
tRAC
tCAC
tCLZ
I/O
Open
tAA
tCPA
tCAC
tCOH
Valid Data
tOE
tOES
tAA
tCPA
tCAC
tCLZ
tOFF
Valid Data
tOEHC
Valid Data
Open
tOE
tOD
tOES
tOD
OE
tOEP
Undefined
Don’t Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
13
ISSI
IS41LV16400
®
EDO-PAGE-MODE EARLY-WRITE CYCLE
tRASP
tRP
tRHCP
RAS
tCSH
tCRP
tPC
tCAS,
tCLCH
tRCD
tCAS,
tCLCH
tCP
tCP
tRSH
tCAS,
tCLCH
tCP
UCAS/LCAS
tAR
tACH
tCAH tASC
tRAD
tASR
ADDRESS
tASC
Row
Column
tRAH
tACH
tRAL
tCAH
tACH
tCAH tASC
Column
tCWL
tWCS
Column
tCWL
tWCS
tWCH
tCWL
tWCS
tWCH
tWCH
tWP
tWP
Row
tWP
WE
tWCR
tDHR
tRWL
tDS
tDS
tDH
I/O
Valid Data
tDS
tDH
Valid Data
tDH
Valid Data
OE
Don’t Care
14
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
ISSI
IS41LV16400
®
EDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)
tRASP
tRP
RAS
tCSH
tCRP
tCAS, tCLCH
tRCD
tCP
tPC / tPRWC(1)
tCAS, tCLCH
tRSH
tCAS, tCLCH
tCP
tCP
UCAS/LCAS
tASR
tRAH
ADDRESS
tAR
tRAD
tASC
tCAH
Row
tASC
tCAH
Column
tRWD
tRCS
tRAL
tCAH
tASC
Column
tCWL
tWP
Column
tRWL
tCWL
tWP
tCWL
tWP
tAWD
tCWD
Row
tAWD
tCWD
tAWD
tCWD
WE
tAA
tAA
tCPA
tDH
tDS
tRAC
tCAC
tCLZ
I/O
Open
tAA
tCPA
tDH
tDS
tCAC
tCLZ
DOUT
DIN
tOE
tCAC
tCLZ
DOUT
tOD
DIN
DOUT
tOD
tOE
tDH
tDS
Open
DIN
tOD
tOE
tOEH
OE
Undefined
Don’t Care
Note:
1. tPC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both
measurements must meet the tPC specifications.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
15
ISSI
IS41LV16400
®
EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)
tRASP
tRP
RAS
tCSH
tPC
tPC
tCRP
tCAS
tRCD
tCAS
tCP
tRSH
tCAS
tCP
tCP
UCAS/LCAS
tASR
tRAH
ADDRESS
tAR
tRAD
tASC
Row
tCAH
tASC
tCAH
Column (A)
tASC
Column (B)
tRCS
tACH
tRAL
tCAH
Column (N)
Row
tRCH
tWCS
tWCH
WE
tAA
tRAC
tCAC
I/O
Open
tCPA
tCAC
tCOH
Valid Data (A)
tAA
tWHZ
tDS
Valid Data (B)
tDH
DIN
Open
tOE
OE
Don’t Care
16
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
ISSI
IS41LV16400
®
AC WAVEFORMS
READ CYCLE (With WE-Controlled Disable)
RAS
tCSH
tCRP
tRCD
tCP
tCAS
UCAS/LCAS
tAR
tRAD
tASR
ADDRESS
tRAH
tCAH
tASC
Row
tASC
Column
Column
tRCS
tRCH
tRCS
WE
tAA
tRAC
tCAC
tCLZ
Open
I/O
tWHZ
tCLZ
Valid Data
Open
tOE
tOD
OE
Undefined
Don’t Care
RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)
tRC
tRAS
tRP
RAS
tCRP
tRPC
UCAS/LCAS
tASR
ADDRESS
tRAH
Row
I/O
Row
Open
Don’t Care
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
17
ISSI
IS41LV16400
®
CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)
tRP
tRAS
tRP
tRAS
RAS
tCHR
tRPC
tCP
tCHR
tRPC
tCSR
tCSR
UCAS/LCAS
Open
I/O
HIDDEN REFRESH CYCLE(1) (WE = HIGH; OE = LOW)
tRAS
tRP
tRAS
RAS
tCRP
tRCD
tRSH
tCHR
UCAS/LCAS
tAR
tRAD
tRAH tASC
tASR
ADDRESS
Row
tRAL
tCAH
Column
tAA
tRAC
tOFF(2)
tCAC
tCLZ
I/O
Open
Valid Data
tOE
Open
tOD
tORD
OE
Undefined
Don’t Care
Notes:
1. A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.
2. tOFF is referenced from rising edge of RAS or CAS, whichever occurs last.
18
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
ISSI
IS41LV16400
®
ORDERING INFORMATION: 5V
Commercial Range: 0°C to 70°C
Speed (ns)
50
60
Order Part No.
Package
IS41LV16400-50T
IS41LV16400-60T
400-mil TSOP (Type II)
400-mil TSOP (Type II)
ORDERING INFORMATION: 3.3V
Extended Temperature Range: -30°C to 85°C
Speed (ns)
50
60
Order Part No.
Package
IS41LV16400-50TE
IS41LV16400-60TE
400-mil TSOP (Type II)
400-mil TSOP (Type II)
ORDERING INFORMATION: 3.3V
Industrial Temperature Range: -40°C to 85°C
Speed (ns)
50
60
Order Part No.
Package
IS41LV16400-50TI
IS41LV16400-60TI
400-mil TSOP (Type II)
400-mil TSOP (Type II)
ISSI
®
Integrated Silicon Solution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: [email protected]
www.issi.com
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
11/18/99
19
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