ON NCP1032 Low power pwm controller Datasheet

NCP1032
Low Power PWM Controller
with On-Chip Power Switch
and Startup Circuits for
Telecom Systems
The NCP1032 is a miniature high−voltage monolithic switching
converter with on−chip power switch and startup circuits. It
incorporates in a single IC all the active power control logic and
protection circuitry required to implement, with minimal external
components several switching regulator applications, such as a
secondary side bias supply or a low power DC−DC converter. This
converter is ideally suited for 24 V and 48 V telecom and medical
isolated power supply applications. The NCP1032 can be configured
in any single−ended topology such as forward or flyback converter.
The NCP1032 is targeted for applications requiring up to 3 W.
The internal error amplifier allows the NCP1032 to be easily
configured for secondary or primary side regulation operation in
isolated and non−isolated configurations. The fixed frequency
oscillator is optimized for operation up to 1 MHz and is capable of
external frequency synchronization, providing additional design
flexibility. In addition, the NCP1032 incorporates undervoltage and
overvoltage line detectors, programmable cycle−by−cycle current
limit, internal soft−start, and thermal shutdown to protect the
controller under fault conditions.
Features
•
•
•
•
•
•
•
•
•
•
•
•
On Chip High 200 V Power Switch Circuit and Startup Circuit
Internal Startup Regulator with Auxiliary Winding Override
Programmable Oscillator Frequency Operation up to 1 MHz
External Frequency Synchronization Capability
Frequency Fold−down Under Fault Conditions
Trimmed ± 2% Internal Reference
Programmable Cycle−by−Cycle Current Limit
Internal Soft−Start
Active Leading Edge Blanking Circuit
Line Under and Over Voltage Protection
Over Temperature Protection
These are Pb−Free Devices
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MARKING
DIAGRAMS
WDFN8
MN SUFFIX
CASE 511BH
1
1032x
ALYW G
G
1032 = Specific Device Marking
x = A or B
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
GND
CT
VFB
COMP
Ç
Ç
Ç
Ç
ÇÇ
ÇÇ
ÇÇ
ÇÇ
VDRAIN
GND
VCC
UV/OV
CL
WDFN8 (Top View)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 20 of this data sheet.
Typical Applications
•
•
•
•
•
•
•
POE (Power Over Ethernet)/PD. Refer to Application Note AND8247
Secondary Side Bias Supply for Isolated DC−DC Converters
Stand Alone Low Power DC−DC Converter
Low Power Bias Supply
Low Power Boost Converter
Medical Isolated Power Supplies
Bias Supply for Telecom Systems. Refer to App Note AND8119/D
© Semiconductor Components Industries, LLC, 2014
October, 2016 − Rev. 3
1
Publication Order Number:
NCP1032/D
NCP1032
VOUT
VIN
D1
COUT
22 mF
Cin
2.2 mF
D2
CVCC
2.2 mF
VDRAIN
R3
UV/OV
VCC
CL
RCL
R4
CC
RC
NCP 1032
CT
GND
COMP
CP
R1
VFB
R2
CCT
Figure 1. Typical Application – Dual Output Auxiliary Regulated Isolated Flyback
PGND
VDRAIN
Internal Bias
I1
UVBAR
150 kW
Driver
LEB
LEBOUT
2 kW
Duty
Cycle
= 75%
3.0 V/
3.5 V
UVBAR
Fault
I2
2.5 V
2 kW
1.0 V
+
−
UV
Comp
Q
SET
R
7.6 V
HIVCC
10.2 V
Internal Bias
2 kW
NSS
LEBOUT
NCL
3.5 V
2 kW
OV
Comp
−
2.24 V +
Q
S
30 ns
One Shot
PWM
COMP
−
+
Error
Amplifier
−
+
2 kW
NLOWVCC
Delay
CLR
OV/UV
VCC
6.6 V
2 kW
COMP
12.5 mA
nstart
NUVLO
RT
FB
+
−
5.7 V
NOV
NUV
Fault
IN1 Logic
IN2
IN3
IN4 OUT2
IN5 OUT3
IN6
IN7
NUVLO
UVBAR
NLOWVCC
NUV
HIVCC
NOV
Thermal Trip
Internal Bias
Fault
nstart
Current
Limit
SS
(all pins except VDRAIN pin are protected by 10 V ESD diodes)
Figure 2. NCP1032 Simplified Block Diagram
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2
Fault
ISET
NCP1032
Table 1. FUNCTIONAL PIN DESCRIPTION
Pin
Name
Function
1
GND
IC Ground
Description
2
CT
Oscillator Frequency
Selection
3
VFB
Feedback Signal Input
The regulated voltage is scaled down to 2.5 V by means of a resistor divider. Regulation is
achieved by comparing the scaled voltage to an internal 2.5 V reference.
4
COMP
Error Amplifier
Compensation
The output of the internal error amplifier. External compensation network between COMP
and VFB pin is required for stable operation.
5
CL
Current Limit Threshold
Selection
A resistor RCL connected between this pin and ground sets the peak current value of the
current limit. If the CL pin is left open, the current limit value is set to its initial maximum value
of approximately 12 mA (CLIM_MAX). Programmable current limit threshold, together with
internal soft−start feature effectively limits the primary transformer high current peaks during
startup phase.
6
UV/OV
Input Line Undervoltage
and Overvoltage
Shutdown
Input line voltage is scaled down using an external resistor divider. The minimum operating
Vin voltage is achieved when the voltage on UV/OV pin reaches UV threshold 1.0 V. The
maximum operating voltage is then limited by 2.4 V on UV/OV pin. A device version without
OV protection feature is available, see ordering information section.
7
VCC
Powers the Internal
Circuitry
8
VDRAIN
Drain Connection
EP
EP
Thermal Flag
Ground reference pin for the circuit.
An external capacitor connected to this pin sets the oscillator frequency up to 1 MHz. The
oscillator can be synchronized to a higher frequency by charging or discharging CT to trip the
internal 3.0 V/3.5 V comparators. If a fault condition exists, the power switch is disabled and
the frequency is reduced.
Supplies power to the internal control circuitry. Connect an external capacitor for energy
storage during startup. The Vcc voltage should not exceed 16 V during operation.
Connects the power switch and startup circuit to the primary transformer windings.
This is the thermal flag for the IC and should be soldered to the ground plane.
Table 2. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
BVdss
−0.3 to +200
V
VCC Power Supply Voltage
VCC
−0.3 to +16
V
Power Supply Voltage on all Pins, except VDRAIN and VCC
VIO
−0.3 to +10
V
IDS(pk)
1.0
A
Power Switch and Startup Circuits Voltage
Drain Current Peak During Transformer Saturation
Thermal Resistance Junction−to−Air –W DFN8 3x3, case 511BH
(100 sq mm, 2oz) (Note 4)
(500 sq mm, 2oz) (Note 4)
(100 sq mm,2oz,) (Note 5)
RqJA
°C/W
109
64
44
Maximum Junction Temperature
TJMAX
150
°C
Storage Temperature Range
TSTG
−60 to +150
°C
ESD Capability, Human Body Model Pins 1−7 (Note 1)
4.0
kV
ESD Capability, Machine Model Pins 1−7 (Note 1)
400
V
Pin 8 is connected to the high voltage startup and power switch which is protected to
the maximum drain voltage
200
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series contains ESD protection and passes the following tests:
Human Body Model (HBM) ± 2.0 kV per JEDEC standard: JESD22−A114.
Machine Model (MM) ± 200 V per JEDEC standard: JESD22−A115.
2. This device contains latch−up protection and it exceeds ± 100 mA per JEDEC standard: JESD78 class II
3. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A
4. EIA JEDEC 51.3, single layer PCB with added heat spreader
5. EIA JEDEC 51.7, four layer PCB with added heat spreader
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NCP1032
Table 3. ELECTRICAL CHARACTERISTICS
(For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, VDRAIN = 48 V, VCC = 12 V, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SUPPLY SECTION AND VCC MANAGEMENT
VCC_ON
Vcc Voltage at Which the Switcher
Starts Operation
VCC Increasing
9.9
10.2
10.5
V
VCC_MIN
Minimum Operating VCC After Turn on
at Which HV Current Source Restarts
VCC Decreasing
7.40
7.55
7.7
V
VCC_RST
Vcc Undervoltage Lockout Voltage
VCC Decreasing, VFB = VCOMP
6.75
6.95
7.15
V
ICC1
Internal IC Consumption
Power Switch Enabled
MOSFET is switching at 300 kHz
2.0
2.9
4.0
mA
ICC2
Internal IC Consumption
Power Switch Disabled
No Fault condition, VFB = 2.7 V
−
2.0
2.5
mA
ICC3
Internal IC Consumption
Power Switch Disabled
Fault condition,
VFB = 2.7 V, VUV/OV < 1.0 V
−
0.75
1.5
mA
−
−
4.2
4.9
5.1
8.0
200
−
−
POWER SWITCH CIRCUIT
W
Power Switch Circuit On−State
Resistance
ID = 100 mA
TJ = 25°C
TJ = 125°C
BVdss
Power Switch Circuit and Startup
Breakdown Voltage
IDS_OFF = 100 mA, VUV_OV < 1.0 V
Tj = 25°C
IDS_OFF
Power Switch Circuit and Startup
Circuit Off−State Leakage Current
VDRAIN = 200 V, VUV_OV < 1.0 V
TJ = 25°C
TJ = −40°C to 125°C
−
−
20
20
25
30
tR
Switching Characteristics − Rise Time
VDS = 48 V, RL = 480 W, Time
(10%−90%)
−
7
−
ns
tf
Switching Characteristics − Fall Time
VDS = 48 V, RL = 480 W, Time
(90%−10%)
−
10
−
ns
Vcc = 0 V,
Tj = 25°C
Tj = −40°C to 125°C
10.0
9.0
12.0
−
14.0
15.0
Vcc = VCC_ON − 0.2 V
Tj = 25°C
Tj = −40°C to 125°C
9.0
8.0
11.0
−
13.0
16.0
−
16.3
−
VCOMP = VFB, Follower Mode
TJ = 25°C
TJ = −40°C to 125°C
2.45
2.40
2.5
2.5
2.55
2.60
Line Regulation
VCC = 8 V to 16 V, TJ = 25°C
−
1.0
3.0
mV
RDSON
V
mA
INTERNAL STARTUP CURRENT SOURCE
ISTART1
ISTART2
Vstart_min
HV Current Source
HV Current Source
Minimum Startup Voltage
ISTART2 = 0.5 mA,
Vcc = VCC_ON − 0.2 V, Tj = 25°C
mA
mA
V
ERROR AMPLIFIER
VREF
REGLINE
Reference Voltage
V
IVFB
Input Bias Current
VFB = 2.3 V
−
70
150
nA
ISRC
COMP Source Current
VFB = 2.3 V
80
95
125
mA
ISNK
COMP Sink Current
VFB = 2.7 V
500
700
900
mA
VC_MAX
COMP Maximum Voltage
ISRC = 0 mA, VFB = 2.3 V
3.95
4.17
4.5
V
VC_MIN
COMP Minimum Voltage
ISNK = 0 mA, VFB = 2.7 V
−
91
200
mV
AVOL
Open Loop Voltage Gain
(Note 6)
−
80
−
dB
GBW
Gain Bandwidth Product
(Note 6)
−
1.0
−
MHz
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NCP1032
Table 3. ELECTRICAL CHARACTERISTICS
(For typical values Tj = 25°C, for min/max values Tj = −40°C to +125°C, VDRAIN = 48 V, VCC = 12 V, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
420
512
600
−
57
−
Unit
CURRENT LIMIT AND PWM COMPARATOR
CLIM_MAX
CLIM_MIN
TPLH
TON_MIN
Tss
Max Current Limit Threshold
Min Current Limit Threshold
CL pin Floating, TJ = 25°C,
(di/dt = 0.5 A/ms)
RCL = 20 kW, TJ = 25°C,
(di/dt = 0.1 A/ms)
mA
mA
Propagation Delay
from Current Limit Detection to the
Drain OFF State (Note 6)
−
100
−
ns
Min On Time Pulse Width
FSW = 300 kHz (Note 6)
−
240
−
ns
Soft−Start Duration
(Note 6)
−
2.0
−
ms
0.95
1.067
1.18
V
−
70
−
mV
−
0
1
mA
2.3
2.41
2.5
V
−
158
−
mV
LINE UNDER/OVERVOLTAGE PROTECTIONS
Vuv
Undervoltage Lockout Threshold
VUV_hys
Undervoltage Lockout Hysteresis
VFB = VCOMP, Vin decreasing
Iuv
Input Bias Current
VFB = 2.3 V
VOV
Overvoltage Lockout Threshold
VFB = VCOMP, Vin increasing (Note 7)
Vov_hys
Overvoltage Lockout Hysteresis
TEMPERATURE MANAGEMENT
TSD
Thermal Shutdown
(Note 6)
165
°C
Hysteresis in Shutdown
(Note 6)
20
°C
INTERNAL OSCILLATOR
fOSC1
Oscillation Frequency, 300 kHz
CT = 560 pF (Note 8)
TJ = 25°C
TJ = −40°C to 125°C
275
270
300
−
325
335
kHz
fOSC2
Oscillation Frequency, 960 kHz
CT = 100 pF, TJ = 25°C
−
960
−
kHz
ICT_C
Timing Charge Current
VCT = 3.25 V
−
172
−
mA
ICT_D
Timing Discharge Current
VCT = 3.25 V
VR_pk
Oscillator Ramp Peak Voltage
−
3.492
−
V
VR_VLY
Oscillator Ramp Valley
−
2.992
−
V
DCMAx
Maximum Duty Cycle
70
76.5
80
%
mA
517
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Guaranteed by design and characterized
7. The OV/UV option is disabled on the NCP1032B version
8. Oscillator frequency can be externally synchronized to the maximum frequency of the device
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NCP1032
TYPICAL OPERATING CHARACTERISTICS – Dual Output Isolated Flyback Converter
12.100
80
18 V
12.095
72 V
12.090
60
48 V
50
VOUT (V)
EFFICIENCY (%)
70
36 V
24 V
40
48 V
12.080
30
12.075
20
12.070
10
12.065
72 V
24 V
12.085
18 V
36 V
12.060
0
0
25
50
75
100
125
150
175
200
0
225
25
50
75
100
125
150
175
200 225
IOUT (mA)
IOUT (mA)
Figure 3. Efficiency vs. IOUT at VIN = 24, 36, 48
and 72 V, T1 = CoilCraft B0226−EL
Figure 4. VCC Pin Load Regulation at VIN = 24,
36, 48 and 72 V
Figure 5. Startup Sequence, RCL Open, Output
Load = 80 W (IOUT = 150 mA), 1 VCC 3.0 V/
div DC, 2 VOUT 3.0 V/div DC, 3 VIN 10.0 V/
div DC, 4 IPRI 100 mA/div DC, T = 20 ms/div
Figure 6. Soft−Start, RCL open, Output No
Load 1 VCC 3.0 V/div DC, 2 VOUT 3.0 V/div DC,
3 VIN 10.0 V/div DC, 4 IPRI 100 mA/div DC,
T = 500 ms/div
Figure 7. Soft−Start, RCL = 32 kW (CLIM =
250 mA), Output Load = 240 W (IOUT = 50 mA),
1 VCC 3.0 V/div DC, 2 VOUT 3.0 V/div DC, 3 VIN
10.0 V/div DC, 4 IPRI 100 mA/div DC,
T = 1.0 ms/div
Figure 8. Discontinuous Conduction Mode
(DCM), IOUT = 150 mA, 2 VDRAIN 20 V/div DC,
3 ISEC 30 mA/div DC, 4 IPRI 100 mA/div, DC,
T = 500 ns/div
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NCP1032
TYPICAL OPERATING CHARACTERISTICS
1100
SWITCHING FREQUENCY (kHz)
1600
FREQUENCY (kHz)
800
400
200
100
CT = 82 pF
1000
900
800
700
500
400
50
80
560
1040
1520
2000
300
−40
2480
−20
0
20
40
60
80
100 120
AMBIENT TEMPERATURE (°C)
Figure 9. Frequency vs. Timing Capacitor CT
at 255C
Figure 10. Oscillator Frequency vs. Junction
Temperature
75.5
75.8
VDRAIN = 100 V
597 kHz
320 kHz
75.6
75.2
1.04 MHz
DUTY CYCLE (%)
DUTY CYCLE (%)
CT = 560 pF
CAPACITANCE (pF)
76.0
75.4
75.2
75.0
128 kHz
74.8
74.6
74.4
VDRAIN = 48 V
74.9
VDRAIN = 15 V
74.6
74.3
74.0
−20
0
20
40
60
80
100
9
10
11
12
13
14
15
AMBIENT TEMPERATURE (°C)
VCC (V)
Figure 11. Maximum Duty Ratio vs.
Temperature
Figure 12. Maximum Duty Ratio vs. VCC
Voltage
300
280
260
VDRAIN = 15 V
240
220
200
VDRAIN = 48 V
180
160
140
VDRAIN = 100 V
120
100
8
8
120
IDS(off), POWER SWITCH AND STARTUP
CIRCUITS LEAKAGE CURRENT (mA)
74.2
74.0
−40
MIN ON TIME (ns)
CT = 220 pF
600
9
10
11
12
13
14
15
30
28
26
24
22
20
18
16
14
12
10
8
6
4
2
0
125°C
25°C
−40°C
0
16
16
40
80
120
160
200
240
VCC (V)
DRAIN VOLTAGE (V)
Figure 13. Minimum On Time vs. VCC
Figure 14. Power Switch Circuit and Startup
Circuit Leakage Current vs. Drain Voltage
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NCP1032
5.5
5.3
5.1
4.9
4.7
4.5
4.3
4.1
3.9
3.7
3.5
3.3
3.1
2.9
−40
VCC = 8 V
VCC = 12 V
VCC = 16 V
−20
0
20
40
60
80
100
VCC(reset), UNDERVOLTAGE
LOCKOUT THRESHOLD (V)
RDS(on), POWER SWITCH ON
RESISTANCE (W)
TYPICAL OPERATING CHARACTERISTICS
120
16.40
16.38
16.36
16.34
16.32
16.30
16.28
16.26
16.24
16.22
16.20
16.18
16.16
16.14
16.12
16.10
−40
−20
TJ, JUNCTION TEMPERATURE (°C)
60
80
100
120
VCC(reset), UNDERVOLTAGE
LOCKOUT THRESHOLD (V)
6.965
VCC = 0 V
VCC = VCC(on) − 0.2 V
−20
0
20
40
60
80
100
6.960
6.955
6.950
6.945
6.940
6.935
6.930
−40
120
−20
0
20
40
60
80
100
120
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 17. Startup Current vs. Junction
Temperature
Figure 18. Undervoltage Lockout Threshold
vs. Junction Temperature
Startup Threshold
INPUT CURRENT (mA)
ISTART, STARTUP CURRENT (mA)
40
Figure 16. Vdrain Startup Threshold over
Temperature
UV THRESHOLD (V)
10.50
10.25
10.00
9.75
9.50
9.25
9.00
8.75
8.50
8.25
8.00
7.75
7.50
7.25
−40
20
TJ, JUNCTION TEMPERATURE (°C)
Figure 15. Power Switch RDSON vs. Junction
Temperature
12.8
12.6
12.4
12.2
12.0
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
−40
0
Minimum Operating Threshold
−20
0
20
40
60
80
100
5.25
5.00
4.75
4.50
4.25
4.00
3.75
3.50
3.25
3.00
2.75
2.50
2.25
2.00
100 200 300
120
400
500
600
700
800 900 1000
TJ, JUNCTION TEMPERATURE (°C)
FREQUENCY (kHz)
Figure 19. Supply Voltage Thresholds vs.
Junction Temperature
Figure 20. VCC Input Current at 12 V with an
18 V applied Drain voltage 255C VS Oscillator
Frequency
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NCP1032
TYPICAL OPERATING CHARACTERISTICS
4.1
3.7
3.5
3.3
3.1
2.9
2.7
2.5
8
9
10
11
12
13
14
5.0
4.5
597 kHz
4.0
3.5
320 kHz
3.0
128 kHz
2.0
−40
16
15
0
20
40
60
80
100
120
AMBIENT TEMPERATURE (°C)
Figure 21. Operating Supply Current vs.
Supply Voltage at 320 kHz
Figure 22. VCC Input Current vs. Temperature
over Frequency span VDrain = 48 V
REFERENCE VOLTAGE (V)
4.20
4.19
4.18
4.17
4.16
4.15
4.14
4.13
4.12
4.11
−40
−20
VCC, SUPPLY VOLTAGE (V)
4.23
4.22
4.21
Vc CLAMP (V)
5.5
2.5
2.3
2.1
−20
0
20
40
60
80
100
2.500
2.499
2.498
2.495
2.494
VCC = 12 V
VCC = 8 V
2.493
2.492
2.491
2.490
2.489
2.488
−40
120
VCC = 16 V
2.497
2.496
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 23. COMP Clamp Voltage vs. Junction
Temperature
Figure 24. Reference Voltage vs. Junction
Temperature
120
800
96.50
96.25
780
VCC = 16 V
96.00
SINK CURRENT (mA)
SOURCE CURRENT (mA)
1.04 MHz
6.0
INPUT CURRENT (mA)
ICC1, OPERATING SUPPLY
CURRENT (mA)
6.5
VDRAIN = 48 V
TJ = 25°C
CT = 560 pF
3.9
95.75
VCC = 12 V
95.50
95.25
95.00
VCC = 8 V
94.75
760
740
720
700
680
94.50
660
94.25
94.00
−40
640
−20
0
20
40
60
80
100
120
620
−40
−20
0
20
40
60
80
100
TJ, JUNCTION TEMPERATURE (°C)
TJ, JUNCTION TEMPERATURE (°C)
Figure 25. COMP Source Current vs. Junction
Temperature
Figure 26. COMP Sink Current vs. Junction
Temperature
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120
NCP1032
TYPICAL OPERATING CHARACTERISTICS
VCC = 16 V
1.070
1.069
OV THRESHOLD (V)
UV THRESHOLD (V)
1.072
1.071
VCC = 8 V
1.068
1.067
1.066
VCC = 12 V
1.065
1.064
1.063
1.062
−20
0
20
40
60
80
120
100
ILIM, CURRENT LIMIT THRESHOLD (mA)
110
100
UV Hysteresis
−20
0
20
40
60
80
100
0
20
40
60
80
100
120
450
400
350
300
250
200
150
100
50
120
20
40
60
80
100
120
140
160
180 200
TJ, JUNCTION TEMPERATURE (°C)
RISET (kW)
Figure 29. Under/Overvoltage Hysteresis vs.
Junction Temperature
Figure 30. Current Limit Threshold vs. RCL,
Current Slew Rate = 0.5 A/ms
340
330
25 V
72 V
120 mH
310
300
290
280
270
0
−20
Figure 28. Overvoltage Threshold vs. Junction
Temperature
140
130
120
320
VCC = 12 V
Figure 27. Undervoltage Threshold vs.
Junction Temperature
OV Hysteresis
90
80
70
60
−40
VCC = 8 V
TJ, JUNCTION TEMPERATURE (°C)
180
170
160
150
VCC = 16 V
TJ, JUNCTION TEMPERATURE (°C)
ILIM, CURRENT LIMIT THRESHOLD (mA)
ILIM, CURRENT LIMIT THRESHOLD (mA)
VUV/OV(hys), HYSTERESIS (mV)
1.061
1.060
−40
2.422
2.420
2.418
2.416
2.414
2.412
2.410
2.408
2.406
2.404
2.402
2.400
2.398
2.396
2.394
−40
100 200 300 400 500 600 700 800 900 1000
550
500
RISET = OPEN
450
400
350
300
RISET = 50 kW
250
200
150
100
50
−40
RISET = 22 kW
−20
0
20
40
60
80
100
120
CURRENT SLEW RATE (mA/mS)
TJ, JUNCTION TEMPERATURE (°C)
Figure 31. Current Limit Threshold vs. Current
Slew Rate
Figure 32. Current Limit Threshold vs. TJ,
Current Slew RISET = Open = 0.5 A/ms, RISET
= 55 kW = 0.3 A/ms, RISET = 22 kW = 0.1 A/ms
www.onsemi.com
10
NCP1032
CT Ramp
CT Charge
Signal
PWM
Comparator
Output
Current Limit
Propagation
Delay
PWM Latch
Output
Power Switch
Circuit Gate Drive
Current Limit
Threshold
Leading Edge
Blanking Output
Normal PWM Operating Range
Output Overload
Figure 33. Pulse Width Modulation Timing Diagram
VCC(on)
VCC(off)
VCC(reset)
0V
ISTART
0 mA
3.0 V
VUV
0V
2.5 V
VFB
0V
VDRAIN
0V
Startup
Mode
Dynamic
Self Supply
Normal Operation
Output Overload
Figure 34. Auxiliary Winding Operation with Output Overload Timing Diagram
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11
NCP1032
Introduction
its minimum value to its maximum value. The soft−start
time is load and RCL dependent and can be computed in the
soft−start section. The designer must evaluate the current
draw of the regulator at the desired switching frequency over
the VCC and temperature operating range shown in Figures
20 − 22. CVCC is calculated using the following equation:
The NCP1032 is a monolithic voltage−mode switching
regulator designed for isolated and non−isolated bias supply
applications. The internal startup circuit and the MOSFET
are rated at 200 V, making them ideal for 24 V through 48 V
telecom and 42 V automotive applications. In addition, the
NCP1032 can operate from an existing 12 V supply. The
regulator is optimized for operation up to 1 MHz.
The NCP1032 device incorporates all of the active power,
control logic, protection circuitry, and power switch in a
single IC. The compact design allows the designer to use
minimal external components on several switching
regulator applications, such as a secondary side bias supply
or a low power DC−DC converter.
The NCP1032 is available in the space saving WDFN8
3 x 3 mm package and is targeted for applications requiring
up to 3 W.
The NCP1032 has an extensive set of features including
programmable cycle−by−cycle current limit, internal
soft−start, input line under and over voltage detection
comparators with hysteresis, regulator output undervoltage
lockout with hysteresis and over temperature protection
providing protection during fault conditions. A description
of each of the functional blocks is given below and the
functional block diagram is shown in Figure 2.
C VCC +
ǒTSS_Delay ) TSSǓ
I CC
V CC_ON * V CC_MIN
2.95 mF +
³
(eq. 1)
ǒ0.4 ms ) 2.0 msǓ
4.0 mA
10.2 V * 6.95 V
ICC includes the NCP1032 bias current (ICC1_MAX) and
any additional current used to bias the feedback (if used).
Assuming an ICC1_MAX of 3.5 mA plus a 0.5 mA bias
current for the feedback sensing resistors (if used), and Tss
of 2 ms, CVCC is calculated at 2.95 mF and should be rounded
up to ensure design margin to 3.3 mF. Please note that if the
feedback sensing resistors are connected to the VCC pin
(isolated main output topology) and CVCC is increased to
match COUT, the transient response of the converter will
suffer. The poor transient response is due to the imbalanced
capacitance to current ratio. The auxiliary winding has a
significantly greater capacitance to current ratio than the
output winding, taking it longer for CVCC to follow COUT
during a transient condition.
After initial startup, the VCC pin should be biased above
VCC_min using an auxiliary winding. This will prevent the
startup regulator from turning on during normal operation,
reducing device power dissipation. A load should not be
directly connected to the VCC pin. A load greater than
12 mA will override the startup circuit possibly damaging
the part. The maximum voltage rating of the startup circuit
is 200 V. Power dissipation should be observed to avoid
exceeding the maximum power dissipation of the package.
Figure 35 shows the recommended configuration for a
non−isolated flyback converter.
Startup Supply Circuit and Undervoltage Lockout
The NCP1032 contains an internal 200 V startup regulator
that eliminates the need for external startup components.
The startup regulator consists of a 12 mA (typical) current
source that supplies power from the input line (VDRAIN)
pin to charge the capacitor on the VCC pin (CVCC). The act
of charging the CVCC capacitor until it reaches 10.2 V while
holding the power switch off is called Startup Mode (SM).
Once the current source charges the VCC voltage to 10.2 V
(typical) the startup circuit is disabled and if no faults are
present, the power switch circuit is enabled. The internal
control circuitry will draw its current from the energy held
by the CVCC capacitor. The startup regulator turns on again
once VCC reaches 7.55 V. The charging of the CVCC
capacitor to 10.2 V by the current source and the discharging
by the control circuitry to 7.55 V will be henceforth referred
to as Dynamic Self Supply (DSS).
If VCC falls below 7.55 V while switching, the device
enters a Restart Mode (RM). While in the RM the CVCC
capacitor is allowed to discharge to 6.95 V while the power
switch is enabled. Once the 6.95 V threshold is reached, the
power switch circuit is disabled, and the startup regulator is
enabled to charge the CVCC capacitor. The power switch is
enabled again once the VCC voltage reaches 10.2 V.
Therefore, the external CVCC capacitor must be sized such
that a voltage greater than 6.95 V is maintained on the VCC
pin while the converter output reaches regulation. The
output is delayed 0.4 ms (TSS_Delay) from the released
undervoltage lockout to the first switching pulse. The
soft−start time TSS is fixed at 2 ms to ramp the current from
VOUT
T1
VIN
Cin
D1
Lpri
COUT
Lsec
Lbias
D2
CVCC
CT
R4
GND
UV/OV
VDRAIN
R3
VCC
CL
RCL
CC
RC
R1
COMP
VFB
CP
NCP1032
CCT
Figure 35. Non−Isolated Bias Supply
Configuration
www.onsemi.com
12
R2
NCP1032
Soft−Start
and the soft−start time will be 2 ms as shown in Figure 36.
The equation below can be used to calculate the soft−start
time for all other current limit set values.
The NCP1032 features an internal soft−start which
reduces power−on stress and also contributes to the lower
output overshoot. Once the VCC_ON threshold is reached
and there are no fault conditions, the power switch is enabled
and the cycle−by−cycle current limit is ramped up slowly to
the current limit threshold set by the CL pin. If the CL pin
is open, the current limit will be set to its maximum value
TSSR +
Set Current * Min Current
Max Current * Min Current
1.07 ms +
300 mA * 57 mA
512 mA * 57 mA
T SS ³
(eq. 2)
2 ms
PWM Signal
COMP Voltage
4.2 V
3.5
Ramp
3.0 V
Set Limit
Current Limit
57 mA
Inductor Current
Correction
Time
Soft−Start Time
Figure 36. Soft−Start Time
The compensation of the converter must be manipulated
to minimize the overshoot of the output voltage during
startup, details are in the compensation section.
OV Enable
OV
Comparator
VIN
Line Under and Over Voltage Detectors
The NCP1032 incorporates Vin input line under voltage
(UV) and over voltage (OV) shutdown circuits. If the
UV/OV pin is set below 1.0 V or above 2.4 V thresholds the
power switch will stop switching and the part will use DSS
until the problem is corrected. The comparators incorporate
typical voltage hysteresis of 70 mV (UV) and 158 mV (OV)
to prevent noise from inadvertently triggering the shutdown
circuit. The UV/OV sense pin can be biased using an
external resistor divider from the input line as shown in
Figure 37. The UV/OV pin should be bypassed using a 1 nF
capacitor to prevent triggering the UV/OV circuit during
normal switching operation.
CUV
1 nF
R3
2.4 V
R4
1V
Fault
Logic
UV
Comparator
Figure 37. UV/OV Resistor Divider
from the Input Line
The resistive network impedance must not be too high to
keep good voltage accuracy and not too low to minimize
power losses. A 200 kW to 1.2 MW range is recommended
for the high side resistor R3. If the designer wanted to set the
undervoltage threshold to 32 V, the resistor divider should be
designed according to the following equation:
R4 +
V UV R3
³
V IN_UV * V UV
34.49 kW +
www.onsemi.com
13
1.067
1 MW
32 V * 1.067
(eq. 3)
[ 34.0 kW (R96 Value)
NCP1032
Oscillator, Voltage Feed Forward, and Sync Capability
The OV threshold monitored at the UV/OV pin is 2.41
times higher than the UV threshold, leading to an OV
threshold of 73.3 V for the calculated R96 value. Designers
can quickly set the OV/UV thresholds by referencing
Figure 38.
The oscillator is optimized for operation up to 1 MHz and
its frequency is set by the external timing capacitor (CT)
connected to the CT pin. The oscillator has two modes of
operation: free running and synchronized (sync). While in
free running mode, an internal current source sequentially
charges and discharges CT generating a voltage ramp
between 3.0 V and 3.5 V. Under normal operating
conditions, the charge (ICT_C) and discharge (ICT_D)
currents are typically 172 mA and 515 mA, respectively. The
charge/discharge current ratio of 1:3 discharges CT in 25%
of the total period. The power switch is disabled while CT is
discharging, guaranteeing a maximum duty cycle of 75% as
shown in Figure 39.
120
110
INPUT VOLTAGE (V)
100
Overvoltage Threshold
90
80
70
60
50
Undervoltage Threshold
40
COMP
30
CT Ramp
20
10
150
200
250
300
350
400
450
500
Power Switch
Enabled
R3 (kW)
Figure 38. UV/OV Resistor Divider Thresholds
with R4 Set to 10 k
CT Charge
Signal
The UV/OV pin can also be used to implement a remote
enable/disable function. If an external transistor pulls the
UV/OV pin below 1.0 V (or above 2.4 V) the converter will
be disabled and no switching is allowed. A device version is
available without the OV protection feature, see the ordering
information section.
Max Duty
Cycle
75%
25%
Figure 39. Auxiliary Winding Operation with
Output Overload Timing Diagram
The oscillator frequency should be set no more than 25%
below the target sync frequency to maintain an adequate
voltage ramp and provide good noise immunity. A possible
circuit to synchronize the oscillator is shown in Figure 40.
Error Amplifier
The internal error amplifier (EA) regulates the output
voltage of the bias supply. The scaled signal is fed into the
feedback pin (VFB) which is the inverting input of the error
amplifier. It compares a scaled voltage signal to an internal
trimmed 2.5 V reference connected to its non−inverting
input.
The output of the error amplifier is internally connected
to a PWM comparator and also available externally through
the COMP pin for frequency compensation. To insure
normal operation, the EA compensation should be selected
such that the EA frequency response crosses 0 dB below
80 kHz.
The error amplifier feedback bias current is less than
200 nA over the operating range. The output source and sink
currents are typically 95 mA and 700 mA, respectively.
Under load transient conditions, COMP may need to
move from the bottom to the top of the CT ramp. A large
current is required to complete the COMP swing if small
resistors or large capacitors are used to implement the
compensation network. In which case, the COMP swing will
be limited by the EA source current. Optimum transient
responses are obtained if the compensation components
allow the COMP pin to swing across its operating range in
1 cycle.
CT
CT
R1
C1
R2
Figure 40. External Frequency
Synchronization Circuit
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14
2
NCP1032
Voltage feed forward can be implemented by connecting
a resistor from the input voltage to the CT pin. RFF supplies
a current that allows the input voltage to modify the
maximum duty cycle rather than the standard 75%
maximum. If the designer wanted to implement a fixed
lower duty cycle, a resistor can be tied to a fixed voltage
source such as VAUX or a voltage reference. If voltage feed
forward is used, the frequency can shift dramatically
depending on the value of the resistor.
The PWM comparator and latch propagation delay are
less than 200 ns. If the system is designed to operate with a
minimum on time less than 200 ns (no or light load), the
converter will skip pulses. Skipping pulses is usually not a
problem, unless operating at a frequency close to the audible
range. Skipping pulses is more likely when operating at high
frequencies during high input voltage and minimum load
conditions.
A 2 kW series resistor is included for ESD protection
between the internal EA output and the COMP pin. Under
normal operation, a 220 mV offset is observed between the
CT ramp and the COMP crossing points. The series resistor
does not interact with the error amplifier transfer function.
VIN
IFF
Cin
2.2 mF
VDRAIN
RFF
Programmable Current Limit
The power switch circuit incorporates SENSEFET®
technology to monitor the drain current. A sense voltage is
generated by driving a sense element, RSENSE, with a current
proportional to the drain current. The sense voltage is
compared to an externally programmable reference voltage
on the non−inverting input of the current limit comparator.
If the sense voltage exceeds the setup reference level, the
comparator resets the PWM latch and the switching cycle is
terminated. The reference level threshold is programmable
by a resistor (RCL) connected to the CL pin shown in
Figure 42.
By limiting the peak current to the needs of the
application, the transformer sizing can be scaled
appropriately to the specific requirements which allows the
PCB footprint to be minimized. The NCP1032 maximum
drain current limit thresholds are 512 mA.
Please refer to Figure 30 for ILIM vs. RCL relationship.
Z1
4V
GND
CT
NCP
1032
CCT
Feed Forward Voltage
CT PIN Voltage
On
Off
Time
75%
On
Off
Time
66%
On
Off
Time Time
58%
On
Off
Time
Time
53%
On
Time
Off
Time
42%
On
Time
Off
Time
38%
On
Off
Time
29%
Off
Time
21%
On
Figure 41. Voltage Feed Forward
R VFF +
VIN MIN * Ramp
I CT_D * D MAX
320 kW +
ǒICT_C ) ICT_DǓ
³
(eq. 4)
32 V * 3.25 V
517 mA * 62%
3.2 mA
ǒ172 mA ) 517 mAǓ
Current Limit
Comparator
+
+
Fault Logic
−
PWM Comparator and Latch
The Pulse Width Modulator (PWM) comparator
compares the error amplifier output (COMP) to the CT ramp
and generates a proportional duty cycle. The power switch
is disabled while COMP voltage is below the CT ramp
signal. Once COMP reaches the ramp signal, the power
switch is enabled. If COMP is at the bottom of the CT ramp,
the converter operates at minimum duty cycle. While COMP
increases, the duty cycle increases until COMP reaches the
peak of the CT ramp, at which point the controller operates
at maximum duty cycle.
The CT charge signal is filtered through a one shot pulse
generator to set the PWM latch and enable switching at the
beginning of each period. Switching is allowed while the CT
ramp is below COMP and a current limit fault is not present.
The pulse width modulation technique is seen in
Figure 39.
100 ns
Leading Edge
Blanking
CL
RCL
Soft−Start Ramp
Sense
MOSFET
VDRAIN
GND
DRIVER
Figure 42. Current Limit Threshold and
Propagation Delay
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15
NCP1032
VDRAIN
The propagation delay is measured from the time an
overcurrent fault appears at power switch circuit drain, to the
start of the turn−off transition as shown in Figure 43. The
current limit propagation delay time is typ. 100 ns. The
propagation must be accounted for when designing the
power supply, as it will result in a constant power output
through the transformer when the output is shorted. The
constant power can cause the transformer to rise in
temperature permanently damaging the magnetics. This can
be mitigated by placing a 10 W resistor in series with the
output rectification diode.
VDRAIN_MAX (180 V)
VLS (leakage spike)
VCLAMP
VR
VIN
t
Figure 44. Power Switch Waveforms with Clamping
T PHL
ISW
TPHL
Cclamp
UV/OV
2
7
VCC
CL 5
COMP
VFB
1
CT
GND
t
Adaptive Leading Edge Blanking
+
Cout
−
8
U?
Figure 43. Current Limit Threshold and
Propagation Delay
D1
D_Clamp
6
Each time the power switch circuit is turned on, a narrow
voltage spike appears across RSENSE. The spike is due to the
power switch circuit gate to source capacitance, transformer
interwinding capacitance, and output rectifier recovery
time. The spike can cause a premature reset of the PWM
latch. A proprietary active Leading Edge Blanking (LEB)
circuit masks the current signal to prevent the voltage spike
from resetting the PWM latch. The active LEB masks the
current signal until the power switch turn on transition is
complete. The adaptive LEB period provides better current
limit control compared to a fixed blanking period.
VF
T1
+
Vin Cin
−
VDRAIN
VIN
LP
Rclamp
ILIM
Rcl
Cvcc
4
3
NCP1032_33
Figure 45. Passive RCD Clamp Network
The passive RCD network is the most standard circuitry
and the formula below is used to calculate RCLAMP and
CCLAMP.
R CLAMP +
C CLAMP +
Power Switch Circuit Protection
The NCP1032 monolithically integrates a 200 V power
switch with control logic circuitry. The power switch is
designed to directly drive the converter transformer. The
gate drive is tailored to control switching transitions and
help limit electromagnetic interference (EMI).
For a Flyback topology a large transient voltage spike
appears at the transformers primary side after the power
switch turns off. These spikes are a function of the
transformer leakage inductance (LLP) on either the primary
or secondary side. A circuit is needed to clamp the leakage
spike, limiting the voltage drain excursion to a safe value.
The operating VDRAIN_MAX is 200 V as depicted in
Figure 44. Two such circuits are the passive RCD network
or a zener clamp as depicted in Figure 45 and Figure 46.
www.onsemi.com
16
2
ǒVCLAMP * (VOUT ) VF)
V CLAMP
L LP
I PEAK 2
V CLAMP
V LS
F SW
R CLAMP
NǓ
F SW
(eq. 5)
NCP1032
The voltage leakage spike (VLS) is usually selected 50 to
70% above the reflected value VR = N x (VOUT + VF) and
(VIN + VCLAMP) must be below the operating VDRAIN−MAX
which is 200 V. The diode used for the clamping circuit
needs to be at minimum fast or ultrafast recovery and an
MURA110 represents a good choice. One major drawback
of the RCD network lies in its dependency upon the peak
current. The worse case occurs when IPEAK and VIN are at
the maximum.
+
Vin
−
Thermal Shutdown
VF
T1
Cin
The zener diode is probably the most expensive but offers
the best protection and a very precise clamping level. Select
the zener voltage to set VLS level between 10 to 15 V above
the reflected voltage VR so VZener = VLS + VR. The zener
diode must be able to handle the voltage rating and power
dissipation during the switch turn−off time. For the
NCP1032, a 0.5 W zener diode, like the MMSZ47T1 is
suitable.
D1
Cout
Dz_clamp
Internal thermal shutdown circuitry is provided to protect
the integrated circuit in the event that the maximum junction
temperature is exceeded. When activated at 165°C, the
power switch circuit is disabled. Once the junction
temperature falls below 145°C, the NCP1032 is allowed to
resume normal operation. This feature is provided to prevent
catastrophic failures from accidental device overheating. It
is not intended to be used as a substitute for proper heat
sinking.
+
−
D_Clamp
VDRAIN
8
U?
6
UV/OV
VCC
CL
2
GND
1
CT
COMP
VFB
7
5
Cvcc
Rcl
4
3
NCP1032_33
Figure 46. Zener Clamp Network
Application Considerations
Typical Applications
Output voltage regulation and overall efficiency are
shown in Figure 3 and Figure 4 on page 6. The resistor
divider formed by R3 and R4 sets the undervoltage lockout
threshold at about 32 V.
Application Note AND8119/D describes the design of
this bias supply system.
A 12 V / 3 W bias supply for 36 V to 75 V telecom systems,
1500 V isolation DC−DC converters. The NCP1032 is
configured in Flyback topology and operates in
Discontinuous Conduction Mode (DCM) to offer a
low−cost, high efficiency solution. The circuit schematic is
shown in Figure 47. Transformer T1 is available as a
CoilCraft B0226−EL. Capacitor CCT sets the switching
frequency at approximately 300 kHz.
L1
2.2mH
+
T1
Cin
2.2 mF
−
Lbias
8
UV/OV
R4
32.4
VCC
CL
GND
1
Cvcc
2.2 mF
5
COMP
CT
D2
NRVB0540
7
Cp
2
Cout
22 mF
Lpri
MBR1H100
VDRAIN
U1
6
+
D1
Lsec
Dclp
R3
1M
MBR140
1 nF
C1
1000 pF
Cuv
1 nF
Rclp
18 k
Cclp
VFB
68 pF
4
3
Cc
100 nF
NCP1032
Cct
560 pF
Rc
18 K
R1
19.6 K
R2
5.1 K
Figure 47. 48 V to Isolated 12 V / 3 W Bias Supply Schematic
www.onsemi.com
17
−
NCP1032
Layout Recommendations
signals and ICs. The exposed pad of the package must be
connected to the ground plane of the board which is
important for EMI and thermal management. Finally, it is
always good practice to keep sensitive traces such as
feedback connection (VFB and COMP) as far away from
switched signal connections (VDRAIN) as possible.
Figure 48 shows an example of an optimized PCB layout.
To prevent EMI problems high current copper traces
which have high frequency switching should be optimized.
Therefore, use short and wide traces for power current paths
and for power ground traces especially transformer trace
connections (primary and secondary). When power is
transferred from input to output, there is a period of time
when the power switch is on, referred to as “on time,” and
a period of time when the switch is off, referred to as “off
time.” When the power switch is on, the input voltage is
applied across the primary side of the transformer and
current increases in the primary inductance. Further, when
the power switch is on the output current is supplied from the
output capacitance. When the power switch is off, current on
the primary side conducts through the clamp or snubber
circuit. On the secondary side current is conducting through
the rectification diode, providing power to the output and
replenishing energy in the output capacitances as shown in
Figure 48. Electromagnetic radiation is minimized by
keeping VDRAIN leads, output diode, and output bypass
capacitor leads as short as possible. It is important to
minimize the area of the VDRAIN nodes and used the
ground plane under the switcher circuitry to prevent
interplane coupling and minimize cross−talk to sensitive
Thermal Considerations
Careful attention must be paid to the internal power
dissipation of the NCP1032. Power dissipation is a function
of efficiency and output power. As output power
requirements increase, proper component selection includes
adjusting RDSON, forward voltage of diodes, and enlarging
packages. For example, if a transformer’s size were
increased to lower the DCR or/and increase the inductance
efficiency will improve at heavier loads. The exposed
thermal pad is designed to be soldered to the ground plane
used as a heat sink. The ground plane size should be
maximized and connected to the internal and bottom copper
ground planes with thermal vias placed directly under the
package to spread heat generated by the NCP1032 as
depicted Figure 48.
Figure 48. Recommended PCB Layout
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18
NCP1032
Vin 32 to 75 V
+
−
Cin
2.2 mF
1 nF
MBR140SFT1G
4:1 T1
Rclp
18 k
Dclp
Cclp
Lsec D1
Lpri
Cout
22 mF
U1
R3
1M
D4
MMSZ5243BT1G
Cuv
1 nF
6
UV/OV
R4
32.4
VDRAIN
R7
18 k
8
Q1
NSS1C201LT1G MBR1H100SFT3G
GND
1
CT
2
5
Cp 68 pF
COMP
Cct
560 pF
1.0 mF
Cvcc
7
VCC
CL
+
Vout 5.0 V
600 mA
−
4
Cc
3 100 nF
VFB
NCP1032
Rc
18 K
R1
20 K
R2
20 K
Figure 49. 48 V to 5.0 V DC−DC Converter Without Auxiliary Winding
+
Vin 32 to 75 V
−
Cin
2.2 mF
3:1
T1
Rclp
18 k Lpri
Dclp
Cclp
1 nF
MBR140SFT1G
Lsec
D1
Cout
22 mF
+
Vout 12.0 V
300 mA
−
2
Cct
560 pF
GND
UV/OV
R4
32.4
CT
Cuv
1 nF
U1
6
1
R3
1M
VDRAIN 8
MBR1H100SFT3G
7
VCC
CL
5
100 nF
Cvcc
Cp 68 pF
COMP
4
Cc
3 100 nF
VFB
NCP1032
Rc
18 K
R1
20 K
R2
20 K
Figure 50. 48 V to 12.0 V DC−DC Converter Without Auxiliary Winding
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19
NCP1032
560 mF
D1
100 V
VIN
50 mA
MURA115
Cin
1 mF
VOUT
COUT
22 mF
UV/OV
R4
10 kW
VDRAIN
R3
294 kW
VCC
CL
RCL
40.2 kW
RC
CC 1.5 nF 100 kW
NCP1032
GND
CT
COMP
CP 100 pF
R1
78.7 kW
VFB
R2
2 kW
CCT
Figure 51. Typical Application Circuit Boost Circuit Configuration
ORDERING INFORMATION
OV Protection
Marking
Package
Shipping†
NCP1032AMNTXG
Enable
1032A
WDFN8 3x3
(Pb−Free)
3,000 / Tape & Reel
NCP1032BMNTXG
Disable
1032B
WDFN8 3x3
(Pb−Free)
3,000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
www.onsemi.com
20
NCP1032
PACKAGE DIMENSIONS
WDFN8 3x3, 0.65P
CASE 511BH
ISSUE O
B
A
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
L1
PIN ONE
REFERENCE
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
DETAIL A
E
ALTERNATE
CONSTRUCTIONS
ÇÇÇ
ÇÇÇ
ÉÉÉ
0.10 C
2X
0.10 C
2X
EXPOSED Cu
TOP VIEW
A
DETAIL B
0.10 C
A3
A3
ÇÇÇ
ÉÉÉ
MOLD CMPD
A1
DETAIL B
ALTERNATE
CONSTRUCTIONS
0.08 C
A1
NOTE 4
C
SIDE VIEW
D2
DETAIL A
1
8X
SEATING
PLANE
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MILLIMETERS
MIN
MAX
0.70
0.80
0.00
0.05
0.20 REF
0.25
0.35
3.00 BSC
2.20
2.40
3.00 BSC
1.40
1.60
0.65 BSC
0.45 REF
0.20
0.40
−−−
0.15
RECOMMENDED
SOLDERING FOOTPRINT*
L
8X
2.46
PACKAGE
OUTLINE
4
0.53
E2
3.30
1.66
8
5
e
8X
BOTTOM VIEW
b
0.10 C A B
0.05 C
1
NOTE 3
0.65
PITCH
8X
0.40
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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21
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NCP1032/D