NCV7382 Enhanced LIN Transceiver The NCV7382 is a physical layer device for a single wire data link capable of operating in applications where high data rate is not required and a lower data rate can achieve cost reductions in both the physical media components and in the microprocessor which uses the network. The NCV7382 is designed to work in systems developed for LIN 1.3 or LIN 2.0. The IC furthermore can be used in ISO9141 systems. Because of the very low current consumption of the NCV7382 in the sleep mode it’s suitable for ECU applications with low standby current requirements. This mode allows a shutdown of the whole application. The included wakeup function detects incoming dominant bus messages and enables the voltage regulator. • Operating Voltage VS = 7.0 to 18 V • Very Low Standby Current Consumption of Typ. 6.5 A in Sleep • • • • • • • • • • Mode LIN−Bus Transceiver: ♦ Slew Rate Control for Good EMC Behavior ♦ Fully Integrated Receiver Filter ♦ BUS Input Voltage −27 V to 40 V ♦ Integrated Termination Resistor for LIN Slave Nodes (30 k) ♦ Wakeup Via LIN Bus ♦ Baud Rate up to 20 kBaud ♦ Will Work in Systems Designed for Either LIN 1.3 or LIN 2.0 Compatible to ISO9141 Functions High EMI Immunity Bus Terminals Protect Against Short−Circuits and Transients in the Automotive Environment High Impedance Bus Pin for Loss of Ground and Undervoltage Condition Thermal Overload Protection High Signal Symmetry for use in RC−Based Slave Nodes up to 2% Clock Tolerance when Compared to the Master Node "1000 V ESD Protection, Charged Device Model Control Output for Voltage Regulator with Low On−Resistance for Switchable Master Termination NCV Prefix for Automotive and Other Applications Requiring Site and Change Control Pb−Free Packages are Available © Semiconductor Components Industries, LLC, 2007 February, 2007 − Rev. 3 MARKING DIAGRAM 8 1 V7382 ALYW G SO−8 D SUFFIX CASE 751 8 1 Features • http://onsemi.com V7382 A L Y W G 1 = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package PIN CONNECTIONS RxD 1 8 INH EN 2 7 VS VCC 3 6 BUS TxD 5 GND 4 (Top View) ORDERING INFORMATION Device Package Shipping† SO−8 95 Units/Rail NCV7382DG SO−8 (Pb−Free) 95 Units/Rail NCV7382DR2 SO−8 2500 Tape & Reel SO−8 (Pb−Free) 2500 Tape & Reel NCV7382D NCV7382DR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: NCV7382/D NCV7382 NCV7382 INH VS Internal Supply and References VCC Biasing & Bandgap Thermal Shutdown POR 30 K SLEW RATE CONTROL BUS Driver TxD EN BUS MODE CONTROL GND Wakeup Filter RxD Receive Comparator Input Filter Figure 1. Block Diagram PACKAGE PIN DESCRIPTION Pin Symbol Description 1 RXD 2 EN Enables the normal operation mode when HIGH. 3 VCC 5.0 V supply input. 4 TXD Transmit data from microprocessor to BUS, LOW in dominant state. 5 GND Ground. 6 BUS LIN bus pin, LOW in dominant state. 7 VS Battery input voltage. 8 INH Control output for voltage regulator, termination pin for master pullup. Receive data from BUS to microprocessor, LOW in dominant state. http://onsemi.com 2 NCV7382 Electrical Specification All voltages are referenced to ground (GND). Positive currents flow into the IC. The maximum ratings (in accordance with IEC 134) given in the table below are limiting values that do not lead to a permanent damage of the device but exceeding any of these limits may do so. Long term exposure to limiting values may effect the reliability of the device. OPERATING CONDITIONS Characteristic Symbol Min Max Unit VS VS 7.0 18 V VCC VCC 4.5 5.5 V TA −40 +125 °C Operating Ambient Temperature MAXIMUM RATINGS Rating Symbol VS VS Condition Min t < 1 min −0.3 Load Dump, t < 500 ms Max Unit 30 V 40 VCC VCC − −0.3 +7.0 V Transient Supply Voltage VS.tr1 ISO 7637/1 Pulse 1 (Note 1) −150 − V Transient Supply Voltage VS..tr2 ISO 7637/1 Pulses 2 (Note 1) − 100 V Transient Supply Voltage VS..tr3 ISO 7637/1 Pulses 3A, 3B −150 150 V BUS Voltage VBUS t < 500 ms , Vs = 18 V −27 t < 500 ms ,Vs = 0 V −40 40 V Transient Bus Voltage VBUS..tr1 ISO 7637/1 Pulse 1 (Note 2) −150 − V Transient Bus Voltage VBUS.tr2 ISO 7637/1 Pulses 2 (Note 2) − 100 V Transient Bus Voltage VBUS.tr3 ISO 7637/1 Pulses 3A, 3B (Note 2) −150 150 V DC Voltage on Pins TxD, RxD − −0.3 7.0 V ESD Capability, Charged Device Model VESDCDM (Note 3) −1.0 1.0 kV ESD Capability of BUS, RxD, TxD, VCC, EN Pins ESD Capability of VS Pin VESDHBM Human Body Model, equivalent to discharge 100 pF with 1.5 k (Note 3) −2.0 −1.5 2.0 1.5 kV − Maximum Latchup Free Current at Any Pin VDC −500 500 mA Maximum Power Dissipation ILATCH Ptot At TA = 125°C − 197 mW Thermal Impedance JA In Free Air − 152 °C/W Storage Temperature Tstg − −55 +150 °C Junction Temperature TJ − −40 +150 °C LEAD TEMPERATURE SOLDERING REFLOW Lead Free, 60 sec −150 sec above 217, 40 sec Max at Peak TSLD − 265 Peak °C Leaded, 60 sec −150 sec above 183, 30 sec Max at Peak TSLD − 240 Peak °C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. ISO 7637 test pulses are applied to VS via a reverse polarity diode and > 2.0 F blocking capacitor. 2. ISO 7637 test pulses are applied to BUS via a coupling capacitance of 1.0 nF. 3. This device incorporates ESD protection and is tested by the following methods: ESD HBM tested per AEC−Q100−002 (EIA/JESD22−A 114C) ESD CDM tested per EIA/JESD22−C 101C, Field Induced Model. http://onsemi.com 3 NCV7382 ELECTRICAL CHARACTERISTICS (VS = 7.0 to 18 V, VCC = 4.5 to 5.5 V and TA = −40 to 125°C unless otherwise noted.) Characteristic Symbol Condition Min Typ Max Unit 2.75 − 4.3 V GENERAL VCC Undervoltage Lockout VCC_UV Supply Current, Dominant ISd VS = 18 V, VCC = 5.5 V, TxD = L − 0.9 2.0 mA Supply Current, Dominant ICCd VS = 18 V, VCC = 5.5 V, TxD = L − 0.6 2.0 mA Supply Current, Recessive ISr VS = 18 V, VCC = 5.5 V TxD = H − 25 50 A Supply Current, Recessive ICCr VS = 18 V, VCC = 5.5 V TxD = H − 50 75 A Supply Current, Sleep Mode ISsl VS = 12 V, VCC and TxD = 0 V, TA = 25° − 6.5 − A Supply Current, Sleep Mode ISsl VS = 12 V, VCC and TxD = 0 V − 6.5 14 A EN = H, TxD = L Thermal Shutdown Tsd (Note 4) − 155 − 180 °C Thermal Recovery Thys (Note 4) − 126 − 150 °C − 120 200 mA BUS TRANSMIT Short Circuit Bus Current IBUS_LIM (Notes 5 and 6) VBUS = VS, Driver On Pullup Current Bus IBUS_PU (Notes 5 and 6) VBUS = 0, VS = 12 V, Driver Off −600 − −200 A Pullup Current Bus IBUS_PU_SLEEP VBUS = 0, VS = 12 V, Sleep Mode −100 −75 − A Bus Reverse Current, Recessive IBUS_PAS_rec (Notes 5 and 6) VBUS > VS, 8.0 V < VBUS < 18 V 7.0 V < VS < 18 V, Driver Off − − 20 A Bus Reverse Current Loss of Battery IBUS (Notes 5 and 6) VS = 0 V, 0 V < VBUS < 18 V − − 100 A Bus Current During Loss of Ground IBUS_NO_GND (Notes 5 and 6) VS = 12 V, 0 < VBUS < 18 V −1.0 − 1.0 mA Transmitter Dominant Voltage VBUSdom_DRV_2 (Note 5) VS = 7.0 V, Load = 500 − − 1.2 V Transmitter Dominant Voltage VBUSdom_DRV_3 (Note 5) VS = 18 V, Load = 500 − − 2.0 V Pulse Response via 10 k VPULSE = 12 V, VS = Open − 25 35 pF Bus Input Capacitance CBUS (Note 4) BUS RECEIVE Receiver Dominant Voltage VBUSdom (Notes 5 and 6) − 0.4 *VS − − V Receiver Recessive Voltage VBUSrec (Notes 5 and 6) − − − 0.6*VS V Center Point of Receiver Threshold VBUS_CNT (Notes 4, 5 & 6) VBUS_CNT = (VBUSdom + VBUSrec)/2 0.487 *VS 0.5*VS 0.512*VS V Receiver Hysteresis VHYS (Notes 4, 5 & 6) VBUS_CNTt = (VBUSrec − VBUSdom) − 0.16*VS − V 4. No production test, guaranteed by design and qualification. 5. In accordance to LIN physical layer specification 1.3. 6. In accordance to LIN physical layer specification 2.0. http://onsemi.com 4 NCV7382 ELECTRICAL CHARACTERISTICS (VS = 7.0 to 18 V, VCC = 4.5 to 5.5 V and TA = −40 to 125°C unless otherwise noted.) Characteristic Symbol Condition Min Typ Max Unit TXD, EN High Level Input Voltage Vih Rising Edge − − 0.7*VCC V Low Level Input Voltage Vil Falling Edge 0.3*VCC − − V TxD Pullup Resistor RIH_TXD VTxD = 0 V 10 15 25 k RIL_EN VEN = 5.0 V 20 30 50 k Vol_rxd IRxD = 2.0 mA − − 0.9 V −10 − 10 A − 20 50 −5.0 − 5.0 A Min Typ Max Unit − − 5.0 s −2.0 − 2.0 s − − 6.0 s EN Pulldown Resistor RXD Low Level Output Voltage Leakage Current Vleak_rxd VRxD = 5.5 V, Recessive Ron_INH Normal or Standby Mode, VINH = VS − 1.0 V, VS = 12 V INH On Resistance Leakage Current IINH_lk EN = L, VINH = 0 V AC CHARACTERISTICS Characteristic Symbol Condition Propagation Delay Transmitter (Notes 7 and 9) ttrans_pdf ttrans_pdr Bus Loads: 1.0 K/1.0 nF, 660 /6.8 nF, 500 /10 nF Propagation Delay Transmitter Symmetry (Notes 8 and 9) ttrans_sym Calculate ttrans_pdf − ttrans_pdr Propagation Delay Receiver (Notes 7, 9, 12, 13 and 14) trec_pdf trec_pdr CRxD = 20 pF Propagation Delay Receiver Symmetry (Notes 9, 11 and 12) trec_sym Calculate ttrans_pdf − ttrans_pdr −2.0 − 2.0 s Slew Rate Rising and Falling Edge, High Battery (Notes 8, 11 and 12) |tSR_HB| Bus Loads: VS = 18 V, 1.0 K/1.0 nF, 660 /6.8 nF, 500 /10 nF 1.0 2.0 3.0 V/s Slew Rate Rising and Falling Edge, Low Battery (Notes 8, 11 and 12) |tSR_LB| Bus Loads: VS = 7.0 V, 1.0 K/1.0 nF, 660 /6.8 nF, 500 /10 nF 0.5 2.0 3.0 V/s Slope Symmetry, High Battery (Notes 11 and 12) tssym_HB Bus Loads: VS = 18 V, 1.0 k/1.0 nF, 660 /6.8 nF, 500 /10 nF, Calculate tsdom – tsrec −5.0 − +5.0 s Bus Duty Cycle (Note 13) D1 D2 Calculate tBUS_rec(min)/100 s Calculate tBUS_rec(max)/100 s 0.396 − − − − 0.581 s/s s/s Receiver Debounce Time (Notes 8, 11 and 14) trec_deb BUS Rising and Falling Edge 1.5 − 4.0 s Sleep Mode, BUS Rising & Falling Edge 30 − 150 s Normal −> Sleep Mode Transition 10 20 40 s Wakeup Filter Time EN − Debounce Time twu ten_deb 7. Propagation delays are not relevant for LIN protocol transmission, value only information parameter. 8. No production test, guaranteed by design and qualification. 9. See Figure 2 − Input/Output Timing. 10. See Figure 8 − Slope Time Calculation. 11. See Figure 3 − Receiver Debouncing. 12. In accordance to LIN physical layer specification 1.3. 13. In accordance to LIN physical layer specification 2.0. 14. This parameter is tested by applying a square wave to the bus. The minimum slew rate for the bus rising and falling edges is 50 V/s. http://onsemi.com 5 NCV7382 TIMING DIAGRAMS TxD 50% ttrans_pdf VBUS 100% 95% BUS ttrans_pdr 50% 50% 5% 0% trec_pdf RxD trec_pdr 50% Figure 2. Input/Output Timing t < trec_deb t < trec_deb VBUS 60% 40% t VRxD 50% t Figure 3. Receiver Debouncing http://onsemi.com 6 NCV7382 VBUS t t > twu VINH twu t VCC t VEN t VRxD wakeup interrupt t Figure 4. Sleep Mode and Wakeup Procedure http://onsemi.com 7 NCV7382 TEST CIRCUITS FOR DYNAMIC AND STATIC CHARACTERISTICS NCV7382 VS VCC 100 nF RL 100 nF EN BUS CL TxD 2.7 K RxD INH GND 10 K 20 pF Figure 5. Test Circuit for Dynamic Characteristics NCV7382 2 F 500 + VS VCC 100 n EN BUS TxD GND RxD 1 nF Oscilloscope Schaffner− Generator Puls3a,3b Puls1,2,4 12 V Figure 6. Test Circuit for Automotive Transients http://onsemi.com 8 + − NCV7382 Functional Description The EN pin is used to switch the NCV7382 into different operating modes. because the transceiver and the external voltage regulator are disabled. If VCC has been switched off, a wakeup request from the bus line (remote wakeup) will cause the NCV7382 to enter the VBAT−standby mode (VCC is present again) and sets the RxD output to low until the device enters the normal operation mode (active LOW interrupt at RxD). If the INH pin is not connected to the regulator or the inhibitable external regulator is not the one that provides the VCC − supply, the normal mode is directly accessible by logic high on the EN pin. (Wakeup via mode change/local wakeup.) In order to prevent an unintended wakeup caused by disturbances in the automotive environment, incoming dominant signals from the bus have to exceed the wakeup delay time. Normal Mode Thermal Shutdown Mode Initialization After power on, the chip automatically enters the VBAT −standby mode. In this intermediate mode the INH output will become HIGH (VS) and therefore the ECU − voltage regulator will provide the VCC−supply. The transceiver will remain in the VBAT standby mode until the controller sets it to normal operation (EN = High). Bus communication is only possible in normal mode. The NCV7382 switches itself to the VBAT−standby mode if VCC is missing or below the undervoltage lockout threshold. Operating Modes All of the NCV7382 is active. Switching to normal mode can only be done with EN = high. If the junction temperature TJ is higher than 155°C, the NCV7382 could be switched into the thermal shutdown mode. Transmitter will be switched off. If TJ falls below the thermal shutdown temperature (typ. 140°C), the NCV7382 will be switched to the previous state. Sleep Mode The sleep mode (EN = LOW) can only be reached from normal mode and permits a very low power consumption Table 1. Mode Control EN VCC 0 0 0 Comment INH RxD VBAT−standby, Power On Vs 0 1 VBAT−standby, VCC On Vs X 1 1 Normal Mode Vs VCC = Recessive 0 = Dominant 0 0 Sleep Mode Floating 0 0 1 Sleep Mode Regulator not disabled Directly switch to normal mode with EN = 1 Floating VCC 0 0/1 Vs 0 − Active low wakeup interrupt Remote wakeup request LIN BUS Transceiver TxD Input The transceiver consists of a bus−driver (1.2 V @ 40 mA) with slew rate control, current limit, and a receiver with a high voltage comparator with filter circuitry. During transmission the signal on TxD will be transferred to the BUS driver for generating a BUS signal. To minimize the electromagnetic emission of the bus line, the BUS driver has integrated slew rate control and wave shaping. Transmitting will be interrupted in the following cases: • Sleep Mode • Thermal Shutdown • VBAT−standby The CMOS compatible input TxD directly controls the BUS level: TxD = low → BUS = low (dominant level) TxD = high → BUS = high (recessive level) BUS Input/Output The recessive BUS level is generated from the integrated 30 k pullup resistor in series with a diode. The diode prevents the reverse current on VBUS when VBUS > VS. No additional termination resistor is necessary to use the NCV7382 on LIN slave nodes. If this IC is used for LIN master nodes, it is necessary to terminate the bus with an external 1.0 kW resistor in series with a diode to VBAT or INH (See Section Short Circuit to Ground). http://onsemi.com 9 NCV7382 RxD Output The TxD pin has an internal pullup resistor connected to VCC. This secures that an open TxD pin generates a recessive BUS level. VS The signal on the BUS pin will be transferred continuously to the RxD pin. Short spikes on the bus signal are filtered with internal circuitry (Figure 3 and Figure 7). VBUS_CNT_max 60% BUS 50% VhHYS 40% VBUS_CNT_min t t < trec_deb t < trec_deb RxD t Figure 7. Receive Impulse Diagram v V/T v 3.0 V/s. This principle provides very good symmetry of the slope times between recessive to dominant and dominant to recessive slopes within the LIN bus load range (CBUS, Rterm). The NCV7382 guarantees data rates up to 20 kbit within the complete bus load range under worst case conditions. The constant slew rate principle holds appropriate voltage levels and can operate within the LIN Protocol Specification for RC oscillator systems with a matching tolerance up to 2%. The receive threshold values VBUS_CNT_max and VBUS_CNT_min are symmetrical to 0.5 * VS with a hysteresis of 0.16 * VS (typical). The LIN specific receive threshold is between 0.4 * VS and 0.6*VS. The received BUS signal will be output to the RxD pin: BUS < VBUS_CNT – 0.5 * VHYS → RxD = low (BUS dominant) BUS > VBUS_CNT + 0.5 * VHYS → RxD = high, floating (BUS recessive) RxD is a buffered open drain output with a typical load of: Resistance: 2.7 k Capacitance: < 20 pF Operating Under Disturbance Loss of Battery If VS and VCC are disconnected from the battery, the bus pin is in high impedance state. There is no impact to the bus traffic. EN−Pin The NCV7382 is switched into sleep mode with a falling edge and into normal mode with a rising edge of the EN pin. It will remain in normal mode as long as EN = high (See Figure 4 − Sleep Mode and Wakeup Procedure for more details). When the NCV7382 is switched to sleep mode, the voltage regulator on the INH pin is switched off. The NCV7382 can be turned off with EN = low independent of the state of the bus−transceiver. The EN input has an internal pulled down to guarantee a low level with EN floating. Loss of Ground In case of an interrupted ground connection from VS and VCC, there is no influence to the bus line. Short Circuit to Battery The transmitter output current is limited to 200 mA (max) in case of short circuit to battery. Short Circuit to Ground Negative voltages on the BUS pin are limited primarily to current through the internal 30 k resistor and series diode from VS through a switched device controlled by EN. Secondary contributions are attributed to the resistor and diode hardwired from VS to BUS. Data Rate The NCV7382 is a constant slew rate transceiver. The bus driver operates with a fixed slew rate range of 1.0 V/s http://onsemi.com 10 NCV7382 System designs can have an external resistor (1 k) in series with an external diode to the battery, but short circuit current from bus to ground can be reduced dramatically by using the INH pin as termination pin for the master pullup (See Figure 10 − Application Circuitry). With this new setup, the controller can detect a short circuit of the bus to ground (RxD timeout) and the transceiver can be set into sleep mode. The INH pin will be floating in this case, and the external master pullup resistor will be disconnected from the bus line. Additionally, the internal slave termination resistor is switched off and only a high impedance termination is applied to the bus (typ. 75 A). This will reduce the failure current of the system by at least an order of magnitude, preventing a fast discharge of the car battery. If the failure is removed, the bus level will become recessive again and will wakeup the system even if no local wakeup is present or possible. Thermal Overload The NCV7382 is protected against thermal overloads. If the chip temperature exceeds the thermal shutdown threshold, the transmitter is switched off until thermal recovery. The receiver continues to work during thermal shutdown. Undervoltage VCC The VCC undervoltage lockout feature disables the transmitter until it is above the undervoltage lockout threshold to prevent undesirable bus traffic. Application Hints LIN System Parameter Bus Loading Requirements Parameter Symbol Min Typ Max Unit VBAT 8.0 − 18 V Voltage Drop of Reverse Protection Diode VDrop_rev 0.4 0.7 1.0 V Voltage Drop at the Serial Diode in Pullup Path VSerDiode 0.4 0.7 1.0 V Battery Shift Voltage VShift_BAT 0 − 0.1 VBAT Ground Shift Voltage VShift_GND 0 − 0.1 VBAT Master Termination Resistor Rmaster 900 1000 1100 Slave Termination Resistor Rslave 20 30 60 k Number of System Nodes N 2.0 − 16 − LENBUS − − 40 m Operating Voltage Range Total Length of Bus Line Line Capacitance CLINE − 100 150 pF/m Capacitance of Master Node CMaster − 220 − pF Capacitance of Slave Node CSlave − 220 250 pF Total Capacitance of the Bus including Slave and Master Capacitance CBUS 1.0 4.0 10 nF RNetwork 537 − 863 1.0 − 5.0 s Network Total Resistance Time Constant of Overall System Recommendations for System Design of wires and connectors, and the internal capacitance of the LIN transmitter. This internal capacitance is strongly dependent on the technology of the IC manufacturer and should be in the range of 30 pF to 150 pF. If the bus lines have a total length of nearly 40 m, the total bus capacitance can exceed the LIN system limit of 10 nF. A second parameter of concern is the integrated slave termination resistor tolerance. If most of the slave nodes have a slave termination resistance at the allowed maximum of 60 k, the total network resistance is more than 700 . Even if the total network capacitance is below or equal to the maximum specified value of 10 nF, the network time constant is higher than 7.0 s. This problem can be solved only by adjusting the master termination resistor to the required maximum network time constant of 5.0 s (max). The goal of the LIN physical layer standard is to have a universal definition of the LIN system for plug and play solutions in LIN networks up to 20 kbd bus speeds. In case of small and medium LIN networks, it’s recommended to adjust the total network capacitance to at least 4.0 nF for good EMC and EMI behavior. This can be done by setting only the master node capacitance. The slave node capacitance should have a unit load of typically 220 pF for good EMC/EMI behavior. In large networks with long bus lines and the maximum number of nodes, some system parameters can exceed the defined limits and of the LIN system designer must intervene. The whole capacitance of a slave node is not only the unit load capacitor itself. Additionally, there is the capacitance http://onsemi.com 11 NCV7382 NOTE: The setting of the network time constant is necessary in large networks (primarily resistance) and also in small networks (primarily capacitance). requires the deviation of the slave node clock to the master node clock after synchronization must not differ by more than "2%. The NCV7382 meets the requirements for implementation in RC−based slave nodes. The LIN Protocol Specification MIN/MAX SLOPE TIME CALCULATION (In accordance to the LIN System Parameter Table) VBUS 100% 60% 60% 40% 40% 0% Vdom tsdom tsrec Figure 8. Slope Time and Slew Rate Calculation (In accordance to LIN physical layer specification 1.3) The slew rate of the bus voltage is measured between 40% and 60% of the output voltage swing (linear region). The output voltage swing is the difference between dominant and recessive bus voltage. The slope time of the recessive to dominant edge is directly determined by the slew rate control of the transmitter: tslope + VswingńdVńdt The dominant to recessive edge is influenced from the network time constant and the slew rate control, because it’s a passive edge. In case of low battery voltages and high bus loads the rising edge is only determined by the network. If the rising edge slew rate exceeds the value of the dominant one, the slew rate control determines the rising edge. dVńdt + 0.2 * Vswingń(t40%−t60%) The slope time is the extension of the slew rate tangent until the upper and lower voltage swing limits: tslope + 5 * (t40%−t60%) http://onsemi.com 12 NCV7382 tBit tBit TxD tdom(max) VSUP trec(min) 100% 74.4% tdom(min) 58.1% BUS 58.1% 42.2% 28.4% trec(max) GND 28.4% 0% RxD Figure 9. Duty Cycle Measurement and Calculation in Accordance to LIN Physical Layer Specification 2.0 Duty Cycle Calculation voltage levels as specified in the LIN physical layer specification 1.3. The devices within the D1/D2 duty cycle range also operates in applications with reduced bus speed of 10.4 kBit/s or below. In order to minimize EME, the slew rates of the transmitter can be reduced (by up to [ 2 times). Such devices have to fulfill the duty cycle definition D3/D4 in the LIN physical layer specification 2.0. Devices within this duty cycle range cannot operate in higher frequency 20 kBit/s applications. With the timing parameters shown in Figure 9 two duty cycles, based on trec(min) and trec(max) can be calculated as follows: D1* = trec(min)/(2 x tBit) D2* = trec(max)/(2 x tBit) For proper operation at 20 kBit/s (bit time is 50 s) the LIN driver has to fulfill the duty cycles specified in the AC characteristics for supply voltages of 7...18 V and the three defined standard loads. Due to this simple definition there is no need to measure slew rates, slope times, transmitter delays and dominant *D1 and D2 are defined in the LIN protocol specification 2.0. http://onsemi.com 13 NCV7382 Car Battery Ignition LIN BUS 2.2 F 1N4001 VBAT VIN 100 nF Voltage Regulator NCV8502 VOUT 10 k Slave ECU Reset 47 nF 10 F 100 nF VCC VS RxD BUS NCV7380* mP 220 pF TxD GND GND ECU Connector to Single Wire LIN Bus 2.7 K *The NCV7380 is a pin compatible low cost transceiver without INH control. 2.2 F 1N4001 VBAT VIN Voltage Regulator NCV8501 10 k ENABLE Master ECU 10 k Reset 10 F 47 nF 47 nF 100 nF 2.7 K VCC INH VS 1K RxD mP GND NCV7382 BUS TxD EN GND 220 pF Figure 10. Application Circuitry http://onsemi.com 14 ECU Connector to Single Wire LIN Bus VOUT 100 nF NCV7382 ESD/EMC Remarks ESD Test The NCV7382 is tested according to MIL883D (human body model). General Remarks Electronic semiconductor products are sensitive to Electro Static Discharge (ESD). Always observe Electro Static Discharge control procedures whenever handling semiconductor products. EMC The test on EMC impacts is done according to ISO 7637−1 for power supply pins and ISO 7637−3 for data and signal pins. POWER SUPPLY PIN VS Test Pulse Condition Duration 1 t1 = 5.0 s/US = −100 V/tD = 2.0 ms 5000 Pulses 2 t1 = 0.5 s/US = 100 V/tD = 0.05 ms 5000 Pulses 3a/b US = −150 V/US = 100 V Burst 100 ns/10 ms/90 ms Break 1h 5 Ri = 0.5 , tD = 400 ms tr = 0.1 ms/UP + US = 40 V 10 Pulses Every 1 Min DATA AND SIGNAL PINS EN, BUS Test Pulse Condition Duration 1 t1 = 5.0 s/US = −100 V/tD = 2.0 ms 1000 Pulses 2 t1 = 0.5 s/US = 100 V/tD = 0.05 ms 1000 Pulses 3a/b US = −150 V/US = 100 V Burst 100 ns/10 ms/90 ms Break 1000 Burst http://onsemi.com 15 NCV7382 PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE AH −X− NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07. A 8 5 S B 1 0.25 (0.010) M Y M 4 −Y− K G C N DIM A B C D G H J K M N S X 45 _ SEATING PLANE −Z− H 0.10 (0.004) D 0.25 (0.010) M Z Y S X M J S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0 _ 8 _ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0 _ 8 _ 0.010 0.020 0.228 0.244 SOLDERING FOOTPRINT* 1.52 0.060 7.0 0.275 4.0 0.155 0.6 0.024 1.270 0.050 SCALE 6:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 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