ON CAT34TS02 Digital output temperature sensor Datasheet

CAT34TS02
Digital Output Temperature
Sensor with On-board SPD
EEPROM
Description
The CAT34TS02 combines a JC42.4 compliant Temperature Sensor
(TS) with 2−Kb of Serial Presence Detect (SPD) EEPROM.
The TS measures temperature at least 10 times every second.
Temperature readings can be retrieved by the host via the serial
interface, and are compared to high, low and critical trigger limits
stored into internal registers. Over or under limit conditions can be
signaled on the open−drain EVENT pin.
The integrated 2−Kb SPD EEPROM is internally organized as 16
pages of 16 bytes each, for a total of 256 bytes. It features a page write
buffer and supports both the Standard (100 kHz) as well as Fast
(400 kHz) I2C protocol.
Write operations to the lower half memory can be inhibited via
software commands. The CAT34TS02 features Permanent, as well as
Reversible Software Write Protection, as defined for DDR3 DIMMs.
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PIN CONFIGURATION
A0
•
•
•
1
VCC
A1
EVENT
A2
SCL
VSS
SDA
(Top View)
Features
•
•
•
•
•
•
UDFN−8
HU4 SUFFIX
CASE 517AZ
TDFN−8
VP2 SUFFIX
CASE 511AK
JEDEC JC42.4 Compliant Temperature Sensor
Temperature Range: −20°C to +125°C
DDR3 DIMM Compliant SPD EEPROM
Supply Range: 3.3 V ± 10%
I2C / SMBus Interface
Schmitt Triggers and Noise Suppression Filters on SCL and SDA
Inputs
Low Power CMOS Technology
2 x 3 x 0.75 mm TDFN Package and 2 x 3 x 0.5 mm UDFN Package
These Devices are Pb−Free and are RoHS Compliant
VCC
For the location of Pin 1, please consult the
corresponding package drawing.
MARKING DIAGRAM
TDFN−8
GTX
ALL
YM
G
TSU
ALL
YM
G
GTX, TSU = Specific Device Code
A
= Assembly Location Code
LL
= Assembly Lot Number (Last Two Digits)
Y
= Production Year (Last Digit)
M
= Production Month (1 − 9, O, N, D)
G
= Pb−Free Package
SCL
PIN FUNCTIONS
Pin Name
CAT34TS02
A2, A1, A0
UDFN−8
EVENT
A0, A1, A2
SDA
Function
Device Address Input
SDA
Serial Data Input/Output
SCL
Serial Clock Input
EVENT
Open−drain Event Output
VSS
VCC
Power Supply
Figure 1. Functional Symbol
VSS
Ground
DAP
Backside Exposed DAP at VSS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 21 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
June, 2014 − Rev. 12
1
Publication Order Number:
CAT34TS02/D
CAT34TS02
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Units
Operating Temperature
−45 to +130
°C
Storage Temperature
−65 to +150
°C
Voltage on any pin (except A0) with respect to Ground (Note 1)
−0.5 to +6.5
V
Voltage on pin A0 with respect to Ground
−0.5 to +10.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. The A0 pin can be raised to a HV level for RSWP
command execution. SCL and SDA inputs can be raised to the maximum limit, irrespective of VCC.
Table 2. RELIABILITY CHARACTERISTICS
Symbol
Parameter
NEND (Note 2)
Endurance (EEPROM)
TDR
Data Retention (EEPROM)
Min
Units
1,000,000
Write Cycles
100
Years
2. Page Mode, VCC = 3.3 V, 25°C
Table 3. TEMPERATURE CHARACTERISTICS (VCC = 3.3 V ± 10%, TA = −20°C to +125°C, unless otherwise specified)
Parameter
Temperature Reading Error
Class B, JC42.4 compliant
Test Conditions/Comments
Max
Unit
+75°C ≤ TA ≤ +95°C, active range
±1.0
°C
+40°C ≤ TA ≤ +125°C, monitor range
±2.0
°C
−20°C ≤ TA ≤ +125°C, sensing range
±3.0
°C
ADC Resolution
Temperature Resolution
Conversion Time
Thermal Resistance (Note 3) qJA
Junction−to−Ambient (Still Air)
12
Bits
0.0625
°C
100
ms
92
°C/W
3. Power Dissipation is defined as PJ = (TJ − TA)/qJA, where TJ is the junction temperature and TA is the ambient temperature. The thermal
resistance value refers to the case of a package being used on a standard 2−layer PCB.
Table 4. D.C. OPERATING CHARACTERISTICS (VCC = 3.3 V ± 10%, TA = −20°C to +125°C, unless otherwise specified)
Symbol
Max
Unit
TS active, SPD and Bus idle
500
mA
SPD Write, TS shut−down
500
mA
Standby Current
TS shut−down; SPD and Bus idle
10
mA
ILKG
I/O Pin Leakage Current
Pin at GND or VCC
2
mA
ICC
ISHDN
Parameter
Supply Current
Test Conditions/Comments
Min
VIL
Input Low Voltage
−0.5
0.3 x VCC
V
VIH
Input High Voltage
0.7 x VCC
VCC + 0.5
V
VOL1
Output Low Voltage
IOL = 3 mA, VCC > 2.7 V
0.4
V
VOL2
Output Low Voltage
IOL = 1 mA, VCC < 2.7 V
0.2
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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CAT34TS02
Table 5. PIN IMPEDANCE CHARACTERISTICS (VCC = 3.3 V ± 10%, TA = −20°C to +125°C, unless otherwise specified)
Parameter
Symbol
CIN
(Note 4)
SDA, EVENT Pin Capacitance
IA
(Note 5)
Address Input Current (A0, A1, A2)
Product Rev C
Conditions
Max
Units
VIN = 0 V, f = 1 MHz
8
pF
Input Capacitance (other pins)
6
VIN < VIH
35
VIN > VIH
2
mA
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively
strong; therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.
Table 6. A.C. CHARACTERISTICS (VCC = 3.3 V ± 10%, TA = −20°C to +125°C) (Note 6)
Symbol
Min
Max
Units
Clock Frequency
10
400
kHz
tHIGH
High Period of SCL Clock
600
ns
tLOW
Low Period of SCL Clock
1300
ns
FSCL (Note 7)
tTIMEOUT (Note 7)
Parameter
SMBus SCL Clock Low Timeout
tR (Note 8)
SDA and SCL Rise Time
tF (Note 8)
SDA and SCL Fall Time
tSU:DAT (Note 9)
25
35
ms
300
ns
300
ns
Data Setup Time
100
ns
tSU:STA
START Condition Setup Time
600
ns
tHD:STA
START Condition Hold Time
600
ns
tSU:STO
STOP Condition Setup Time
600
ns
Bus Free Time Between STOP and START
1300
ns
tBUF
tHD:DAT
tDH (Note 8)
Ti
tWR
tPU (Note 10)
Input Data Hold Time
0
Output Data Hold Time
200
Noise Pulse Filtered at SCL and SDA Inputs
Write Cycle Time
Power−up Delay to Valid Temperature Recording
ns
900
ns
100
ns
5
ms
100
ms
6. Timing reference points are set at 30%, respectively 70% of VCC, as illustrated in Figure 23. Bus loading must be such as to allow meeting
the VIL, VOL as well as the various timing limits.
7. For the CAT34TS02 Rev. B, the TS interface will reset itself and will release the SDA line if the SCL line stays low beyond the tTIMEOUT limit.
The time−out count−down is activated in the interval between START and STOP when SCL is low and is reset while SCL is high. The minimum
clock frequency of 10 kHz is an SMBus recommendation; the minimum operating clock frequency for the CAT34TS02’s SPD component
is DC, while the minimum operating frequency for the TS component is limited only by the SMBus time−out. For the CAT34TS02 Rev. C,
both the TS and the SPD implement the time−out feature.
8. In a “Wired−OR” system (such as I2C or SMBus), SDA rise time is determined by bus loading. Since each bus pull−down device must be
able to sink the (external) bus pull−up current (in order to meet the VIL and/or VOL limits), it follows that SDA fall time is inherently faster than
SDA rise time. SDA rise time can exceed the standard recommended tR limit, as long as it does not exceed tLOW − tDH − tSU:DAT, where tLOW
and tDH are actual values (rather than spec limits). A shorter tDH leaves more room for a longer SDA tR, allowing for a more capacitive bus
or a larger bus pull−up resistor. At the minimum tLOW spec limit of 1300 ns, the maximum tDH of 900 ns demands a maximum SDA tR of 300 ns.
The CAT34TS02’s maximum tDH is <700 ns, thus allowing for an SDA tR of up to 500 ns at minimum tLOW.
9. The minimum tSU:DAT of 100 ns is a limit recommended by standards. The CAT34TS02 will accept a tSU:DAT of 0 ns.
10. The first valid temperature recording can be expected after tPU at nominal supply voltage.
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CAT34TS02
TYPICAL PERFORMANCE CHARACTERISTICS
300
300
250
250
200
200
ICC (mA)
ICC (mA)
(VCC = 3.3 V, TA = −20°C to +125°C, unless otherwise specified.)
150
150
100
100
50
50
0
−25
0
25
50
75
100
0
−25
125
0
25
50
75
100
TAMB (°C)
TAMB (°C)
Figure 2. TS Active Current (Rev. B)
(I2C−bus and SPD EEPROM Idle)
Figure 3. TS Active Current (Rev. C)
(I2C−bus and SPD EEPROM Idle)
125
4
7
6
3
ISHDN (mA)
ISHDN (mA)
5
4
3
2
2
1
1
−25
0
25
50
75
100
125
0
−25
150
0
25
50
75
100
125
TAMB (°C)
TAMB (°C)
Figure 4. Standby Current (Rev. B) (I2C−bus
and SPD EEPROM Idle, TS Shut−down)
Figure 5. Standby Current (Rev. C) (I2C−bus
and SPD EEPROM Idle, TS Shut−down)
500
500
400
400
ICC_WR (mA)
ICC_WR (mA)
0
−50
300
200
300
200
100
−25
0
25
50
75
100
100
−25
125
0
25
50
75
100
125
TAMB (°C)
TAMB (°C)
Figure 6. SPD EEPROM Write Current (Rev. B)
(I2C−bus Idle, TS Shut−down)
Figure 7. SPD EEPROM Write Current (Rev. C)
(I2C−bus Idle, TS Shut−down)
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CAT34TS02
TYPICAL PERFORMANCE CHARACTERISTICS
(VCC = 3.3 V, TA = −20°C to +125°C, unless otherwise specified.)
4
4
3
3
2
2
Part # 2
Part # 2
1
DT (°C)
DT (°C)
1
0
−1
0
−1
Part # 1
−2
−3
−3
0
25
50
75
100
−4
−25
125
0
25
50
75
100
125
TAMB (°C)
TAMB (°C)
Figure 8. Temperature Read−Out Error (Rev. B)
Figure 9. Temperature Read−Out Error (Rev. C)
80
70
70
60
60
TCONV (ms)
80
50
50
40
40
30
30
20
−25
0
25
50
75
100
20
−25
125
25
50
75
100
TAMB (°C)
Figure 10. A/D Conversion Time (Rev. B)
Figure 11. A/D Conversion Time (Rev. C)
5.0
3.5
4.5
3.0
4.0
2.5
3.5
1.5
2.5
1.0
0
25
50
75
100
0.5
−25
125
0
25
50
75
100
TAMB (°C)
TAMB (°C)
Figure 12. EEPROM Write Time (Rev. B)
Figure 13. EEPROM Write Time (Rev. C)
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5
125
2.0
3.0
2.0
−25
0
TAMB (°C)
tWR (ms)
TCONV (ms)
−4
−25
tWR (ms)
Part # 1
−2
125
CAT34TS02
TYPICAL PERFORMANCE CHARACTERISTICS
(VCC = 3.3 V, TA = −20°C to +125°C, unless otherwise specified.)
3.0
3.0
2.5
2.6
VTH (V)
VTH (V)
2.0
2.2
1.8
1.5
UP
1.0
DN
1.4
0.5
1.0
−25
0
25
50
75
100
0
−25
125
0
25
50
75
100
125
TAMB (°C)
TAMB (°C)
Figure 14. TS POR Threshold Voltage (Rev. B)
Figure 15. TS POR Threshold Voltage (Rev. C)
2.0
3.0
2.5
1.8
VTH (V)
VTH (V)
2.0
1.6
1.4
1.5
UP
1.0
DN
1.2
0.5
0
25
50
75
100
0
−25
125
0
25
50
75
100
125
TAMB (°C)
TAMB (°C)
Figure 16. SPD POR Threshold Voltage (Rev. B)
Figure 17. SPD POR Threshold Voltage (Rev. C)
40
40
35
35
tTIMEOUT (ms)
tTIMEOUT (ms)
1.0
−25
30
25
25
20
−25
30
0
25
50
75
100
20
−25
125
TAMB (°C)
0
25
50
75
100
TAMB (°C)
Figure 18. SMBus SCL Clock Low Timeout
(Rev. B)
Figure 19. SMBus SCL Clock Low Timeout
(Rev. C)
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125
CAT34TS02
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master (Host).
SDA: The Serial Data I/O pin receives input data and
transmits data stored in the internal registers. In transmit
mode, this pin is open drain. Data is acquired on the positive
edge, and is delivered on the negative edge of SCL.
A0, A1 and A2: The Address pins accept the device address.
These pins have on−chip pull−down resistors.
EVENT: The open−drain EVENT pin can be programmed
to signal over/under temperature limit conditions.
supply via pull−up resistors. Master and Slave devices
connect to the bus via their respective SCL and SDA pins.
The transmitting device pulls down the SDA line to
‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 20).
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake−up’ call to all Slaves. Absent a
START, a Slave will not respond to commands.
Power−On Reset (POR)
The CAT34TS02 incorporates Power−On Reset (POR)
circuitry which protects the device against powering up to
invalid state. The TS component will power up into
conversion mode after VCC exceeds the TS POR trigger
level and the SPD component will power up into standby
mode after VCC exceeds the SPD POR trigger level. Both the
TS and SPD components will power down into Reset mode
when VCC drops below their respective POR trigger levels.
This bi−directional POR behavior protects the CAT34TS02
against brown−out failure following a temporary loss of
power. The POR trigger levels are set below the minimum
operating VCC level.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP tells the Slave that no more data will be written
to or read from the Slave.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address (the
preamble) select either the Temperature Sensor (TS)
registers (0011) or the EEPROM memory contents (1010),
as shown in Figure 21. The next 3 bits, A2, A1 and A0, select
one of 8 possible Slave devices. The last bit, R/W, specifies
whether a Read (1) or Write (0) operation is being
performed.
Device Interface
The CAT34TS02 supports the Inter−Integrated Circuit
(I2C) and the System Management Bus (SMBus) data
transmission protocols. These protocols describe serial
communication between transmitters and receivers sharing
a 2−wire data bus. Data flow is controlled by a Master
device, which generates the serial clock and the START and
STOP conditions. The CAT34TS02 acts as a Slave device.
Master and Slave alternate as transmitter and receiver. Up to
8 CAT34TS02 devices may be present on the bus
simultaneously, and can be individually addressed by
matching the logic state of the address inputs A0, A1, and
A2.
Acknowledge
A matching Slave address is acknowledged (ACK) by the
Slave by pulling down the SDA line during the 9th clock
cycle (Figure 22). After that, the Slave will acknowledge all
data bytes sent to the bus by the Master. When the Slave is
the transmitter, the Master will in turn acknowledge data
bytes in the 9th clock cycle. The Slave will stop transmitting
after the Master does not respond with acknowledge
(NoACK) and then issues a STOP. Bus timing is illustrated
in Figure 23.
I2C/SMBus Protocol
The I2C/SMBus uses two ‘wires’, one for clock (SCL) and
one for data (SDA). The two wires are connected to the VCC
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CAT34TS02
SDA
SCL
START BIT
STOP BIT
Figure 20. Start/Stop Timing
EEPROM
1
0
1
0
A2
A1
A0
R/W
TEMPERATURE SENSOR
0
0
1
1
A2
A1
A0
R/W
PREAMBLE
DEVICE ADDRESS
Figure 21. Slave Address Bits
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACKNOWLEDGE
START
Figure 22. Acknowledge Timing
tF
SCL
tLOW
tHIGH
tR
70%
30%
70%
70%
30%
70%
tHD:DAT
tSU:STA
tHD:STA
SDA
70%
30%
tSU:STO
tSU:DAT
70%
30%
30%
70%
tBUF
Figure 23. Bus Timing
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70%
CAT34TS02
Write Operations
The internal EEPROM byte address counter is
automatically incremented after each data byte is loaded. If
the Master transmits more than 16 data bytes, then earlier
data will be overwritten by later data in a ‘wrap−around’
fashion within the selected page. The internal Write cycle,
using the most recently loaded data, then starts immediately
following the STOP.
EEPROM Byte and TS Register Write
To write data to a TS register, or to the on−board
EEPROM, the Master creates a START condition on the bus,
and then sends out the appropriate Slave address (with the
R/W bit set to ‘0’), followed by an address byte and data
byte(s). The matching Slave will acknowledge the Slave
address, EEPROM byte address or TS register address and
the data byte(s), one for EEPROM data (Figure 24) and two
for TS register data (Figure 25). The Master then ends the
session by creating a STOP condition on the bus. The STOP
completes the (volatile) TS register update or starts the
internal Write cycle for the (non−volatile) EEPROM data
(Figure 26).
Acknowledge Polling
Acknowledge polling can be used to determine if the
CAT34TS02 is busy writing to EEPROM, or is ready to
accept commands. Polling is executed by interrogating the
device with a ‘Selective Read’ command (see READ
OPERATIONS). The CAT34TS02 will not acknowledge
the Slave address as long as internal EEPROM Write is in
progress.
EEPROM Page Write
The on−board EEPROM contains 256 bytes of data,
arranged in 16 pages of 16 bytes each. A page is selected by
the 4 most significant bits of the address byte immediately
following the Slave address, while the 4 least significant bits
point to the byte within the page. Up to 16 bytes can be
written in one Write cycle (Figure 27).
S
T
A
R
T
BUS ACTIVITY:
MASTER
SDA LINE
SPD
SLAVE
ADDRESS
Delivery State
The CAT34TS02 is shipped ‘unprotected’, i.e. neither
Software Write Protection (SWP) flag is set. The entire
2−Kb memory is erased, i.e. all bytes are 0xFF.
BYTE
ADDRESS
S
T
O
P
DATA
P
S
A
C
K
A
C
K
SLAVE
A
C
K
Figure 24. EEPROM Byte Write
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
TS
SLAVE
ADDRESS
REGISTER
ADDRESS
DATA (MSB)
S
T
O
P
DATA (LSB)
P
S
A
C
K
A
C
K
SLAVE
A
C
K
A
C
K
Figure 25. Temperature Sensor Register Write
SCL
SDA
8th Bit
Byte n
ACK
tWR
STOP
CONDITION
Figure 26. EEPROM Write Cycle Timing
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START
CONDITION
ADDRESS
CAT34TS02
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SPD
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
S
T
O
P
DATA n+P
DATA n+1
S
P
A
C
K
SLAVE
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: In this example n = XXXX 0000(B); X = 1 or 0
Figure 27. EEPROM Page Write
Selective Read
Read Operations
The Read operation can be started at an address different
from the one stored in the respective address counters, by
preceding the Immediate Read sequence with a ‘data less’
Write operation. The Master sends out a START, Slave
address and address byte, but rather than following up with
data (as in a Write operation), the Master then issues another
START and continuous with an Immediate Read sequence
(Figures 29a, 29b).
Immediate Read
Upon power−up, the address counters for both the
Temperature Sensor (TS) and on−board EEPROM are
initialized to 00h. The TS address counter will thus point to
the Capability Register and the EEPROM address counter
will point to the first location in memory. The two address
counters may be updated by subsequent operations.
A CAT34TS02 presented with a Slave address containing
a ‘1’ in the R/W position will acknowledge the Slave address
and will then start transmitting data being pointed at by the
current EEPROM data or respectively TS register address
counter. The Master stops this transmission by responding
with NoACK, followed by a STOP (Figures 28a, 28b).
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
Sequential EEPROM Read
EEPROM data can be read out indefinitely, as long as the
Master responds with ACK (Figure 30). The internal address
count is automatically incremented after every data byte sent
to the bus. If the end of memory is reached during continuous
Read, then the address counter ‘wraps−around’ to beginning
of memory, etc. Sequential Read works with either
Immediate Read or Selective Read, the only difference
being that in the latter case the starting address is
intentionally updated.
N
OS
AT
CO
KP
SPD
SLAVE
ADDRESS
P
S
A
C
K
SLAVE
DATA
Figure 28a. EEPROM Immediate Read
BUS ACTIVITY:
MASTER
SDA LINE
SLAVE
S
T
A
R
T
TS
SLAVE
ADDRESS
N
OS
AT
CO
KP
A
C
K
P
S
A
C
K
DATA (MSB)
DATA (LSB)
Figure 28b. Temperature Sensor Immediate Read
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CAT34TS02
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
SPD
SLAVE
ADDRESS
S
T
A
R
T
BYTE
ADDRESS (n)
N
OS
AT
CO
KP
SLAVE
ADDRESS
P
S
S
A
C
K
SLAVE
A
C
K
A
C
K
DATA n
Figure 29a. EEPROM Selective Read
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
TS
SLAVE
ADDRESS
S
T
A
R
T
REGISTER
ADDRESS
N
OS
AT
CO
KP
A
C
K
SLAVE
ADDRESS
P
S
S
A
C
K
SLAVE
A
C
K
A
C
K
DATA (MSB)
DATA (LSB)
Figure 29b. Temperature Sensor Selective Read
BUS ACTIVITY:
MASTER
SPD
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
N
OS
A T
CO
KP
SDA LINE
SLAVE
P
A
C
K
DATA n
DATA n+2
DATA n+1
DATA n+x
Figure 30. EEPROM Sequential Read
Software Write Protection
The lower half of memory (first 128 bytes) can be
protected against Write requests by setting one of two
Software Write Protection (SWP) flags.
The Permanent Software Write Protection (PSWP) flag
can be set or read while all address pins are at regular CMOS
levels (GND or VCC), whereas the very high voltage VHV
must be present on address pin A0 to set, clear or read the
Reversible Software Write Protection (RSWP) flag. The
D.C. OPERATING CONDITIONS for RSWP operations
are shown in Table 7.
The SWP commands are listed in Table 8. All commands
are preceded by a START and terminated with a STOP,
following the ACK or NoACK from the CAT34TS02. All
SWP related Slave addresses use the pre−amble: 0110 (6h),
instead of the regular 1010 (Ah) used for memory access.
For PSWP commands, the three address pins can be at any
logic level, whereas for RSWP commands the address pins
must be at pre−assigned logic levels.
VHV is interpreted as logic ‘1’. The VHV condition must
be established on pin A0 before the START and
maintained just beyond the STOP. Otherwise an RSWP
request could be interpreted by the CAT34TS02 as a
PSWP request.
The SWP Slave addresses follow the standard I2C
convention, i.e. to read the state of the SWP flag, the LSB of
the Slave address must be ‘1’, and to set or clear a flag, it
must be ‘0’. For Write commands a dummy byte address and
dummy data byte must be provided (Figure 31). In contrast
to a regular memory Read, a SWP Read does not return data.
Instead the CAT34TS02 will respond with NoACK if the
flag is set and with ACK if the flag is not set. Therefore, the
Master can immediately follow up with a STOP, as there is
no meaningful data following the ACK interval (Figure 32).
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CAT34TS02
Table 7. RSWP D.C. OPERATION CONDITION
Symbol
Parameter
Test Conditions
DVHV
A0 Overdrive (VHV − VCC)
IHVD
A0 High Voltage Detector Current
VHV
A0 Very High Voltage
Min
Max
Units
4.8
V
1.7 V < VCC < 3.6 V
7
0.1
mA
10
V
Control Pin Levels
(Note 11)
Action
Set
PSWP
Set
RSWP
Clear
RSWP
Flag State
(Note 12)
Slave Address
b7 to
b4
b3
b2
b1
b0
ACK
?
X
A2
A1
A0
X
No
0
X
A2
A1
A0
0
Yes
A2
A1
A0
PSWP
RSWP
A2
A1
A0
1
A2
A1
A0
A2
A1
A0
0
X
A2
A1
A0
1
Yes
GND
GND
VHV
1
X
0
0
1
X
No
GND
GND
VHV
0
1
0
0
1
X
No
GND
GND
VHV
0
0
0
0
1
0
Yes
GND
GND
VHV
0
0
0
0
1
1
Yes
GND
VCC
VHV
1
X
0
1
1
X
No
GND
VCC
VHV
0
X
0
1
1
0
Yes
GND
VCC
VHV
0
X
0
1
1
1
Yes
Address Byte
Table 8. SWP COMMANDS
ACK
?
Data
Byte
ACK
?
Write
Cycle
X
Yes
X
Yes
Yes
X
Yes
X
Yes
Yes
X
Yes
X
Yes
Yes
0110
11. Here A2, A1 and A0 are either at VCC or GND for PSWP operations.
12. 1 stands for ‘Set’, 0 stands for ‘Not Set’, X stands for ‘don’t care’.
S
T
BUS ACTIVITY: A
R
MASTER
T
SLAVE
ADDRESS
SDA LINE S
DATA
XXXX X XXX
X XXXXXXX
A
C
K
A
C
K
SLAVE
Figure 31. Software Write Protect (Write)
MASTER
SDA LINE
S
T
A
R
T
SLAVE
ADDRESS
S
T
O
P
P
S
N
A
C or O
A
K
C
K
SLAVE
Figure 32. Software Write Protect (Read)
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P
N
A
C or O
A
K
C
K
X = Don’t Care
BUS ACTIVITY:
S
T
O
P
BYTE
ADDRESS
CAT34TS02
Registers
The CAT34TS02 contains eight 16−bit wide registers
allocated to TS functions, as shown in Table 9. Upon
power−up, the internal address counter points to the
capability register.
Temperature Sensor Operation
The TS component in the CAT34TS02 combines a
Proportional to Absolute Temperature (PTAT) sensor with
a S−D modulator, yielding a 12 bit plus sign digital
temperature representation.
The TS runs on an internal clock, and starts a new
conversion cycle at least every 100 ms. The result of the
most recent conversion is stored in the Temperature Data
Register (TDR), and remains there following a TS
Shut−Down. Reading from the TDR does not interfere with
the conversion cycle.
The value stored in the TDR is compared against limits
stored in the High Limit Register (HLR), the Low Limit
Register (LLR) and/or Critical Temperature Register
(CTR). If the measured value is outside the alarm limits or
above the critical limit, then the EVENT pin may be
asserted. The EVENT output function is programmable, via
the Configuration Register for interrupt mode, comparator
mode and polarity.
The temperature limit registers can be Read or Written by
the host, via the serial interface. At power−on, all the
(writable) internal registers default to 0x0000, and should
therefore be initialized by the host to the desired values. The
EVENT output starts out disabled (corresponding to
polarity active low); thus preventing irrelevant event bus
activity before the limit registers are initialized. While the
TS is enabled (not shut−down), event conditions are
normally generated by a change in measured temperature as
recorded in the TDR, but limit changes can also trigger
events as soon as the new limit creates an event condition,
i.e. asynchronously with the temperature sampling activity.
In order to minimize the thermal resistance between
sensor and PCB, it is recommended that the exposed
backside die attach pad (DAP) be soldered to the PCB
ground plane.
Capability Register (User Read Only)
This register lists the capabilities of the TS, as detailed in
the corresponding bit map.
Configuration Register (Read/Write)
This register controls the various operating modes of the
TS, as detailed in the corresponding bit map.
Temperature Trip Point Registers (Read/Write)
The CAT34TS02 features 3 temperature limit registers,
the HLR, LLR and CLR mentioned earlier. The
temperature value recorded in the TDR is compared to the
various limit values, and the result is used to activate the
EVENT pin. To avoid undesirable EVENT pin activity, this
pin is automatically disabled at power−up to allow the host
to initialize the limit registers and the converter to complete
the first conversion cycle under nominal supply conditions.
Data format is two’s complement with the LSB representing
0.25°C, as detailed in the corresponding bit maps.
Temperature Data Register (User Read Only)
This register stores the measured temperature, as well as
trip status information. B15, B14, and B13 are the trip status
bits, representing the relationship between measured
temperature and the 3 limit values; these bits are not affected
by EVENT status or by Configuration register settings
regarding EVENT pin. Measured temperature is
represented by bits B12 to B0. Data format is two’s
complement, where B12 represents the sign, B11 represents
128°C, etc. and B0 represents 0.0625°C.
Manufacturer ID Register (Read Only)
The manufacturer ID assigned by the PCI−SIG trade
organization to the CAT34TS02 device is fixed at 0x1B09.
Device ID and Revision Register (Read Only)
This register contains manufacturer specific device ID
and device revision information.
Table 9. THE TS REGISTERS
Register Address
Register Name
Power−On Default
Read/Write
0x00
Capability Register
0x007F
Read
0x01
Configuration Register
0x0000
Read/Write
0x02
High Limit Register
0x0000
Read/Write
0x03
Low Limit Register
0x0000
Read/Write
0x04
Critical Limit Register
0x0000
Read/Write
0x05
Temperature Data Register
Undefined
Read
0x06
Manufacturer ID Register
0x1B09
Read
0x07
Device ID/Revision Register
Rev. B
0x0813
Read
Rev. C
0x0A00
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CAT34TS02
Table 10. CAPABILITY REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
RFU
RFU
RFU
RFU
RFU
RFU
RFU
RFU
B7
B6
B5
B4
B3
B2
B1
B0
EVSD
TMOUT
RFU
RANGE
ACC
EVENT
TRES [1:0]
Bit
B15:B8
B7 (Note 13)
Description
Reserved for future use; can not be written; should be ignored; will read as 0
0:
1:
Configuration Register bit 4 is frozen upon Configuration Register bit 8 being set
(i.e. a TS shut−down freezes the EVENT output)
Configuration Register bit 4 is cleared upon Configuration Register bit 8 being set
(i.e. a TS shut−down de−asserts the EVENT output)
B6
0:
1:
The TS implements SMBus time−out within the range 10 to 60 ms
The TS implements SMBus time−out within the range 25 to 35 ms
B5
0:
1:
Pin A0 VHV compliance required for RSWP Write/Clear operations not explicitly stated
Pin A0 VHV compliance required for RSWP Write/Clear operations explicitly stated
B4:B3
00:
01:
10:
11:
LSB = 0.50°C (9 bit resolution)
LSB = 0.25°C (10 bit)
LSB = 0.125°C (11 bit)
LSB = 0.0625°C (12 bit)
B2
0:
1:
Positive Temperature Only
Positive and Negative Temperature
B1
0:
1:
±2°C over the active range and ±3°C over the operating range (Class C)
±1°C over the active range and ±2°C over the monitor range (Class B)
B0
0:
1:
Critical Temperature only
Alarm and Critical Temperature
13. Configuration Register bit 4 can be cleared (but not set) after Configuration Register bit 8 is set, by writing a “1” to Configuration Register
bit 5 (EVENT output can be de-asserted during TS shut-down periods)
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CAT34TS02
Table 11. CONFIGURATION REGISTER
B15
B14
B13
B12
B11
RFU
RFU
RFU
RFU
RFU
B7
B6
B5
B4
B3
B2
B1
B0
TCRIT_LOCK
EVENT_LOCK
CLEAR
EVENT_STS
EVENT_CTRL
TCRIT_ONLY
EVENT_POL
EVENT_MODE
Bit
B15:B11
B10
B9
B8
HYST [1:0]
SHDN
Description
Reserved for future use; can not be written; should be ignored; will read as 0
B10:B9 (Note 14)
00:
01:
10:
11:
Disable hysteresis
Set hysteresis at 1.5°C
Set hysteresis at 3°C
Set hysteresis at 6°C
B8 (Note 18)
0:
1:
Thermal Sensor is enabled; temperature readings are updated at sampling rate
Thermal Sensor is shut down; temperature reading is frozen to value recorded before SHDN
B7 (Note 17)
0:
1:
Critical trip register can be updated
Critical trip register cannot be modified; this bit can be cleared only at POR
B6 (Note 17)
0:
1:
Alarm trip registers can be updated
Alarm trip registers cannot be modified; this bit can be cleared only at POR
B5 (Note 16)
0:
1:
Always reads as 0 (self−clearing)
Writing a 1 to this position clears an event recording in interrupt mode only
B4 (Note 15)
0:
1:
EVENT output pin is not being asserted
EVENT output pin is being asserted
B3 (Note 14)
0:
1:
EVENT output disabled; polarity dependent: open−drain for B1 = 0; grounded for B1 = 1
EVENT output enabled
B2 (Note 20)
0:
1:
event condition triggered by alarm or critical temperature limit crossing
event condition triggered by critical temperature limit crossing only
B1 (Notes 14, 19)
0:
1:
EVENT output active low
EVENT output active high
B0 (Note 14)
0:
1:
Comparator mode
Interrupt mode
14. Can not be altered (set or cleared) as long as either one of the two lock bits, B6 or B7 is set.
15. This bit is a polarity independent ‘software’ copy of the EVENT pin, i.e. it is under the control of B3. This bit is read−only.
16. Writing a ‘1’ to this bit clears an event condition in Interrupt mode, but has no effect in comparator mode. When read, this bit always returns
0. Once the measured temperature exceeds the critical limit, setting this bit has no effect (see Figure 33).
17. Cleared at power-on reset (POR). Once set, this bit can only be cleared by a POR condition.
18. The TS powers up into active mode, i.e. this bit is cleared at power-on reset (POR). When the TS is shut down the ADC is disabled and the
temperature reading is frozen to the most recently recorded value. The TS can not be shut down (B8 can not be set) as long as either one
of the two lock bits, B6 or B7 is set. However, the bit can be cleared at any time.
19. The EVENT output is “open-drain” and requires an external pull-up resistor for either polarity. The “natural” polarity is “active low”, as it allows
“wired-or” operation on the EVENT bus.
20. Can not be set as long as lock bit B6 is set.
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CAT34TS02
Table 12. HIGH LIMIT REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
0
0
0
Sign
128°C
64°C
32°C
16°C
B7
B6
B5
B4
B3
B2
B1
B0
8°C
4°C
2°C
1°C
0.5°C
0.25°C
0
0
Table 13. LOW LIMIT REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
0
0
0
Sign
128°C
64°C
32°C
16°C
B7
B6
B5
B4
B3
B2
B1
B0
8°C
4°C
2°C
1°C
0.5°C
0.25°C
0
0
Table 14. TCRIT LIMIT REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
0
0
0
Sign
128°C
64°C
32°C
16°C
B7
B6
B5
B4
B3
B2
B1
B0
8°C
4°C
2°C
1°C
0.5°C
0.25°C
0
0
Table 15. TEMPERATURE DATA REGISTER
B15
B14
B13
B12
B11
B10
B9
B8
TCRIT
HIGH
LOW
Sign
128°C
64°C
32°C
16°C
B7
B6
B5
B4
B3
B2
B1
B0
8°C
4°C
2°C
1°C
0.5°C
0.25°C
(Note 21)
0.125°C
(Note 21)
0.0625°C
(Note 21)
21. When applicable (as defined by Capability bit TRES), unsupported bits will read as 0
Bit
Description
B15
0: Temperature is below the TCRIT limit
1: Temperature is equal to or above the TCRIT limit
B14
0: Temperature is equal to or below the High limit
1: Temperature is above the High limit
B13
0: Temperature is equal to or above the Low limit
1: Temperature is below the Low limit
B12
0: Positive temperature
1: Negative temperature
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CAT34TS02
Register Data Format
The values used in the temperature data register and the 3
temperature trip point registers are expressed in two’s
complement format. The measured temperature value is
expressed with 12−bit resolution, while the 3 trip
temperature limits are set with 10−bit resolution. The total
temperature range is arbitrarily defined as 256°C, thus
yielding an LSB of 0.0625°C for the measured temperature
and 0.25°C for the 3 limit values. Bit B12 in all temperature
registers represents the sign, with a ‘0’ indicating a positive,
and a ‘1’ a negative value. In two’s complement format,
negative values are obtained by complementing their
positive counterpart and adding a ‘1’, so that the sum of
opposite signed numbers, but of equal absolute value, adds
up to zero.
Note that trailing ‘0’ bits, are ‘0’ irrespective of polarity.
Therefore the don’t care bits (B1 and B0) in the 10−bit
resolution temperature limit registers, are always ‘0’.
Event Pin Functionality
The EVENT output reacts to temperature changes as
illustrated in Figure 33, and according to the operating mode
defined by the Configuration register.
In Interrupt Mode, the enabled EVENT output will be
asserted every time the temperature crosses one of the alarm
window limits, and can be de−asserted by writing a ‘1’ to the
clear event bit (B5) in the configuration register. Once the
temperature exceeds the critical limit, the EVENT remains
asserted as long as the temperature stays above the critical
limit and cannot be cleared. A clear request sent to the
CAT34TS02 while the temperature is above the critical limit
will be acknowledged, but will be executed only after the
temperature drops below the critical limit.
In Comparator Mode, the EVENT output is asserted
outside the alarm window limits, while in Critical
Temperature Mode, EVENT is asserted only above the
critical limit. Clear requests are ignored in this mode. The
exact trip limits are determined by the 3 temperature limit
settings and the hysteresis offsets, as illustrated in Figure 34.
Following a TS shut−down request, the converter is
stopped and the most recently recorded temperature value
present in the TDR is frozen; the EVENT output will continue
to reflect the state immediately preceding the shut−down
command. Therefore, if the state of the EVENT output
creates an undesirable bus condition, appropriate action must
be taken either before or after shutting down the TS. This may
require clearing the event, disabling the EVENT output or
perhaps changing the EVENT output polarity.
In normal use, events are triggered by a change in
recorded temperature, but the CAT34TS02 will also respond
to limit register changes. Whereas recorded temperature
values are updated at sampling rate frequency, limits can be
modified at any time. The enabled EVENT output will react
to limit changes as soon as the respective registers are
updated. This feature may be useful during testing.
Table 16. 12−BIT TEMPERATURE DATA FORMAT
Binary (B12 to B0)
Hex
Temperature
1 1100 1001 0000
1C90
−55°C
1 1100 1110 0000
1CE0
−50°C
1 1110 0111 0000
1E70
−25°C
1 1111 1111 1111
1FFF
−0.0625°C
0 0000 0000 0000
000
0°C
0 0000 0000 0001
001
+0.0625°C
0 0001 1001 0000
190
+25°C
0 0011 0010 0000
320
+50°C
0 0111 1101 0000
7D0
+125°C
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CAT34TS02
TEMPERATURE
CRITICAL
HYSTERESIS AFFECTS
THESE TRIP POINTS
UPPER
ALARM
WINDOW
LOWER
TIME
EVENT in “INTERRUPT” Mode
EVENT in “INTERRUPT” Mode
EVENT in “INTERRUPT” Mode
EVENT in “COMPARATOR” Mode
EVENT in “CRITICAL TEMP ONLY” Mode
Clear request executed immediately
Clear request acknowledged but execution delayed until measured temperature drops below the active Critical Temperature limit
Figure 33. Event Detail
TH
TH − HYST
TL
TL − HYST
BELOW
WINDOW BIT
ABOVE
WINDOW BIT
Figure 34. Hysteresis Detail
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18
CAT34TS02
PACKAGE DIMENSIONS
TDFN8, 2x3
CASE 511AK
ISSUE A
D
A
e
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
TOP VIEW
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A2
0.45
0.55
0.65
A3
A2
A3
0.20
0.25
0.30
D
1.90
2.00
2.10
D2
1.30
1.40
1.50
E
2.90
3.00
3.10
E2
1.20
1.30
1.40
L
BOTTOM VIEW
0.20 REF
b
e
FRONT VIEW
0.50 TYP
0.20
0.30
L
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
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CAT34TS02
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ−01
ISSUE O
D
b
A
e
L
DAP SIZE 1.8 x 1.8
E2
E
PIN #1
IDENTIFICATION
A1
PIN #1 INDEX AREA
D2
TOP VIEW
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
0.45
0.50
0.55
A1
0.00
0.02
0.05
A3
0.127 REF
b
0.20
0.25
0.30
D
1.95
2.00
2.05
D2
1.35
1.40
1.45
E
2.95
3.00
3.05
E2
1.25
1.30
1.35
e
L
BOTTOM VIEW
DETAIL A
0.065 REF
A3 A
FRONT VIEW
0.50 REF
0.25
0.30
0.35
A3
Notes:
(1) All dimensions are in millimeters.
(2) Refer JEDEC MO-236/MO-252.
0.0 - 0.05
DETAIL A
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20
0.065 REF
Copper Exposed
CAT34TS02
Example of Ordering Information
Specific
Device Marking
Package Type
Lead
Finish
CAT34TS02VP2GT4B
(Not recommended for
new designs.)
GTB
TDFN−8
NiPdAu
Tape & Reel,
4,000 Units / Reel
B
CAT34TS02VP2GT4C
GTC
TDFN−8
NiPdAu
Tape & Reel,
4,000 Units / Reel
C
CAT34TS02HU4−GT4
TSU
UDFN−8
NiPdAu
Tape & Reel,
4,000 Units / Reel
C
Device Order Number
Shipping
Device
Revision
22. All packages are RoHS−compliant (Lead−free, Halogen−free)
23. The standard lead finish is NiPdAu.
24. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
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CAT34TS02/D