IRFS11N50A, SiHFS11N50A www.vishay.com Vishay Siliconix Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Low Gate Charge Qg results in Simple Drive Requirement • Improved Gate, Avalanche and Dynamic dV/dt Available Ruggedness • Fully Characterized Capacitance and Available Avalanche Voltage and Current • Effective Coss Specified • Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 500 RDS(on) () VGS = 10 V Qg (Max.) (nC) 0.52 52 Qgs (nC) 13 Qgd (nC) 18 Configuration Single D D2PAK (TO-263) Note * This datasheet provides information about parts that are RoHS-compliant and/or parts that are non-RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information/tables in this datasheet for details. G APPLICATIONS G D • Switch Mode Power Supply (SMPS) • Uninterruptible Power Supply • High Speed Power Switching S S N-Channel MOSFET TYPICAL SMPS TOPOLOGIES • Two Transistor Forward • Half and Full Bridge • Power Factor Correction Boost ORDERING INFORMATION Package D2PAK (TO-263) D2PAK (TO-263) D2PAK (TO-263) Lead (Pb)-free and Halogen-free SiHFS11N50A-GE3 SiHFS11N50ATRR-GE3a SiHFS11N50ATRL-GE3a Lead (Pb)-free IRFS11N50APbF IRFS11N50ATRRPa IRFS11N50ATRLPa Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 500 Gate-Source Voltage VGS ± 30 Continuous Drain Current VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Currenta ID UNIT V 11 7.0 A IDM 44 1.3 W/°C Single Pulse Avalanche Energyb EAS 275 mJ Repetitive Avalanche Currenta IAR 11 A Repetitive Avalanche Energya EAR 17 mJ PD 170 W dV/dt 6.9 V/ns TJ, Tstg - 55 to + 150 Linear Derating Factor Maximum Power Dissipation Peak Diode Recovery TC = 25 °C dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature)d for 10 s 300 °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 4.5 mH, Rg = 25 , IAS = 11 A (see fig. 12). c. ISD 11 A, dI/dt 140 A/μs, VDD VDS, TJ 150 °C. d. 1.6 mm from case. S13-1927-Rev. E, 09-Sep-13 Document Number: 91286 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFS11N50A, SiHFS11N50A www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Case (Drain) RthJC - 0.75 Case-to-Sink, Flat, Greased Surface RthCS 0.50 - Maximum Junction-to-Ambient RthJA - 62 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT V V/°C Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VDS VGS = 0, ID = 250 μA 500 - - VDS/TJ Reference to 25 °C, ID = 1 mA - 0.060 - VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V Gate-Source Leakage IGSS VGS = ± 30 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 500 V, VGS = 0 V - - 25 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250 Gate-Source Threshold Voltage μA - - 0.52 gfs VDS = 50 V, ID = 6.6 A 6.1 - - S Input Capacitance Ciss VGS = 0 V, - 1423 - Output Capacitance Coss VDS = 25 V, - 208 - Reverse Transfer Capacitance Crss f = 1.0 MHz, see fig. 5 - 8.1 - VDS = 1.0 V, f = 1.0 MHz - 2000 - VDS = 400 V, f = 1.0 MHz - 55 - VDS = 0 V to 400 Vc - 97 - - - 52 - - 13 - - 18 - 14 - - 35 - - 32 - - 28 - - - 11 - - 44 - - 1.5 - 510 770 ns - 3.4 5.1 μC Drain-Source On-State Resistance Forward Transconductance RDS(on) ID = 6.6 Ab VGS = 10 V Dynamic Output Capacitance Effective Output Capacitance Total Gate Charge Coss Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-On Delay Time td(on) Rise Time Turn-Off Delay Time Fall Time VGS = 0 V Coss eff. tr td(off) VGS = 10 V ID = 11 A, VDS = 400 V see fig. 6 and 13b VDD = 250 V, ID = 11 A Rg = 9.1 , RD = 22 see fig. 10b tf pF nC ns Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 11 A, VGS = 0 Vb TJ = 25 °C, IF = 11 A, dI/dt = 100 A/μsb V Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width 300 μs; duty cycle 2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising fom 0 % VDS to 80 % VDS. S13-1927-Rev. E, 09-Sep-13 Document Number: 91286 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFS11N50A, SiHFS11N50A www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Output Characteristics S13-1927-Rev. E, 09-Sep-13 Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91286 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFS11N50A, SiHFS11N50A www.vishay.com Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage S13-1927-Rev. E, 09-Sep-13 Vishay Siliconix Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area Document Number: 91286 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFS11N50A, SiHFS11N50A www.vishay.com Vishay Siliconix RD VDS VGS D.U.T. Rg + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature td(off) tf tr Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case VDS 15 V tp L VDS Rg D.U.T. IAS 20 V tp Driver + A - VDD 0.01 Ω Fig. 12a - Unclamped Inductive Test Circuit S13-1927-Rev. E, 09-Sep-13 IAS Fig. 12b - Unclamped Inductive Waveforms Document Number: 91286 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFS11N50A, SiHFS11N50A www.vishay.com Fig. 12c - Maximum Avalanche Energy vs. Drain Current Vishay Siliconix Fig. 12d - Typical Drain-to-Source Voltage vs. Avalanche Current Current regulator Same type as D.U.T. 50 kΩ QG VGS 12 V 0.2 µF 0.3 µF + QGS QGD D.U.T. - VDS VGS VG 3 mA Charge Fig. 13a - Basic Gate Charge Waveform S13-1927-Rev. E, 09-Sep-13 IG ID Current sampling resistors Fig. 13b - Gate Charge Test Circuit Document Number: 91286 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRFS11N50A, SiHFS11N50A www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91286. S13-1927-Rev. E, 09-Sep-13 Document Number: 91286 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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