IC66LV10016AL Document Title 16M-BIT (1M-WORD BY 16-BIT) Low Power Pseudo SRAM Revision History Revision No History Draft Date Remark 0A Initial Draft February 05,2004 Preliminary The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 1 IC66LV10016AL 16M-BIT (1M-WORD BY 16-BIT) Low-Power Pseudo SRAM FEATURES DESCRIPTION • Organization : 1M x 16 The IC66LV10016AL is a family of low voltage, low power 16Mbit static RAM organized as 1M-words by 16-bit, designed with Pseudo SRAM technology, fabricated with CMOS process technology. • Power Supply Voltage : 2.7~3.3V • Three state output and TTL Compatible • Package Type : 48-FBGA-6.00x8.00 mm2 • Address Acess Time : 70ns The IC66LV10016AL is designed specifically for low-power applications such as mobile cellular phones, personal digital assistants and other battery-operated products. The operation modes are determined by a combination of the device control inputs CE , ZZ, LB , UB , WE and OE . Each mode is summarized in the function table. A write operation is executed whenever the low level WE overlaps with the low level LB and/or UB and the low level CE and the high level ZZ. The address (A0~A19) must be set up before the write cycle and must be stable during entire cycle. A read operation is executed by setting WE at a high level and OE at a low level while LB and/or UB and CE are in an active state, ZZ is in a inactive state. When setting LB at the high level and other controls are in an active stage, upper-byte is selected for read and write operations, and lower-byte is not selected. When setting UB at a high level and other pins are in an active stage, lower-byte is selected and upper-byte is not. When setting LB and UB at a high level or CE and ZZ at a high level or ZZ at a low level, the chip is in a non-select mode. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips. When OE is at a high level, the output stage is in a highimpedance state. PART NAME TABLE & KEY SPEC SUMMARY Product Family Operating Operating Voltage Speed Temperature (VCC/VCCQ) IC66LV10016AL-70B Extended (-25-85°C) 2.7-3.3V 70ns Deep powe down Standby Operating PKG Type (IZZ,Max) (ISB2,Max) (Icc2,Max) 25µA 70µA 20mA 48-TFBGA ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. 2 Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 IC66LV10016AL FUNCTIONAL BLOCK DIAGRAM Clk gen. Precharge circuit VCC VSS Row Addresses I/O1~I/O8 Row select Data Cont Memory array I/O Circuit Column select Data Cont I/O9~I/O16 Data Cont Column Addresses CE OE WE UB LB Control Logic ZZ Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 3 IC66LV10016AL PIN CONFIGURATIONS 1 (TOP VIEW) 2 3 4 5 6 Pin Function A0~A19 Address input I/O1 ~ I/O16 Data input / output A LB OE A0 A1 A2 ZZ ZZ Low power modes B I/O9 UB A3 A4 CE I/O1 CE Chip select input C I/O10 I/O11 A5 A6 I/O2 I/O3 WE Write enable input VSS I/O12 A17 A7 I/O4 VCC OE Output enable input D UB Upper Byte (I/O9 ~ 16) E VCC I/O13 NC A16 I/O5 VSS LB Lower Byte (I/O1 ~ 8) F I/O15 I/O14 A14 A15 I/O6 I/O7 VCC Power supply G I/O16 A19 A12 A13 WE I/O8 VSS Ground supply H A18 A8 A9 A10 A11 NC NC No connection 48-TFBGA FUNCTION TABLE CE ZZ OE WE LB UB I/O1-8 I/O9-16 Mode Power H H X X X (1) X High-Z High-Z Deselected Standby X(1) L X(1) X(1) X(1) X(1) High-Z High-Z Deselected L H H H X(1) X(1) High-Z High-Z Output disabled Active L H X H H H High-Z High-Z Output disabled Active L H L H L H Dout High-Z Lower byte read Active L H L H H L High-Z Dout Upper byte read Active L H L H L L Dout Dout Word read Active L H H L L H Din High-Z Lower byte write Active L H H L H L High-Z Din Upper byte write Active L H H L L L Din Din Word write Active (1) (1) (1) (1) Deep Power Down Mode Notes: 1. X means don't-care.(Must be low or hight state) 4 Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 IC66LV10016AL ABSOLUTE MAXIMUM RATINGS Symbol Parameter Ratings Unit VIN,VOUT Voltage on any pin relative to Vss -0.2 to Vcc+0.3 V Vcc Voltage on Vcc supply relative to Vss -0.2 to 3.6 V PD Power Dissipation 1.0 W TSTG Storage Temperature -65 to 150 °C Toper Operating Temperature -25 to 85 °C Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS (1) Symbol Parameter Conditions VCC VIH VIL ILI ILO Supply Voltage Input High Voltage Input Low Voltage Input Leakage current VIN=Vss to Vcc Output Leakage current VOUT=Vss to Vcc Output Disable VOL Output low Voltage IOL=0.5mA VOH Output high Voltage IOH=-0.5mA Min Max Units 2.7 Vcc-0.3 -0.3(3) -1 -1 3.3 Vcc+0.3(2) 0.3 1 1 V V V µA µA 0.3 V Vcc-0.3 V Notes: 1. Toper=-25 to 85°C, otherwise specified. 2. Overshoot : Vcc+1.0V in case of pulse width ≤ 20ns 3. Undershoot : -1.0V in case of pulse width ≤ 20ns 4. Overshoot and undershoot are sampled, not 100% tested. POWER CONSUMPTION CHARACTERISTICS Symbol Parameter Conditions ICC1 Vcc operating supply current ICC2 Vcc Dynamic operation supply current ISB1 TTL Standby Current ( TTL inputs ) CMOS Standby Current ( CMOS inputs ) Deep power down mode Cycle time=1µs,100% duty IOUT=0mA,CE≤0.2V,ZZ=VIH, VIN≤0.2V or VIN≥Vcc-0.2V Cycle time=tRCmin,100% duty IOUT=0mA,CE=VIL,ZZ=VIH, VIN=VIL or VIH CE=VIH,ZZ=VIH, Other inputs=VIL or VIH CE≥Vcc-0.2V,ZZ≥Vcc-0.2V, VIN≤0.2V or VIN≥Vcc-0.2V ZZ≤0.2V, VIN≤0.2V or VIN≥Vcc-0.2V ISB2 IZZ Min Max Units — 3 mA — 20 mA — 0.3 mA — 70 µA — 25 µA CAPACITANCE Symbol Parameter CIN CIO Input Capacitance Output Capacitance Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 Test Condition Min Max Notes VIN=0V VIO=0V - 8 10 pF pF 5 IC66LV10016AL AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Input/Output Reference) Parameter Value Input pulse level Input rise and fall time Input and output reference voltage Output loads 0.3 to Vcc-0.3V 5ns 0.5VCC CL=50pF+1TTL 1 TTL 50pF AC CHARATERISTICS READ CYCLE Symbol tRC tAA tOHA tACE tDOE tBA tASO tASC tAHC tLZCE tLZB tLZOE tHZCE tHZB tHZOE Parameter Read Cycle Time Address Access time Output Hold Time CE Access Time OE Access Time UB, LB Access Time Address set up to OE Low Address set up to CE Low Address hold time from OE High CE to Low-Z Output UB, LB to Low-Z Output OE to Low-Z Output CE to High- Z Output UB, LB to High- Z Output OE to High-Z Output -70 Min Max Units 70 — 5 — — — -5 0 0 0 0 0 — — — 32K 70 — 70 40 25 — — — — — — 15 15 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min Max Units WRITE CYCLE Symbol 6 Parameter -70 tWC tSCE tSA tAW tASC tAHC tPWE tPWB tHA tSD tHD Write Cycle Time CE to Write End Address Setup Time Address Setup Time to Write End Address set up to CE Low Address hold time from OE High WE Pulse Width LB, UB to End of Write Address Hold from Write End Data Setup to Write End Data Hold from Write End 70 60 0 60 0 0 40 60 0 30 0 32K — — — — — — — — — — ns ns ns ns ns ns ns ns ns ns ns tCP CE High Pulse width 30 — ns Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 IC66LV10016AL Power Down Cycle( Ta = -25~85 oC) Symbol Parameter Min Max Units tSSP tSHP TC2LP tHPD CE High set up time for Power Down entry CE High hold time before Power Down exit ZZ Low pulse width CE High hold time after Power Down exit 0 0 30 300 — — — — ns ns ns µs Power Up Timing Requirement( Ta = -25~85 oC) Symbol Parameter Min Max Units tSHU tHPU CE ZZ set up time after Power Up Standby hold time after Power Up 0 300 — — ns µs Min Max Units 0 — ns 300 — µs Min — Max 10 Units ns Data Retention Timing Requirement( Ta = -25~85 oC) Symbol Parameter tBAH A2 to A19 hold time during active tCSH CE hold time for A2 to A19 fix Address Skew Timing Requirement( Ta = -25~85 oC) Symbol tSKEW Parameter Maximum address skew Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 7 IC66LV10016AL Standby Mode State machines Power on CE=VIH Wait 200µs Initial State CE=VIL , ZZ=VIH Active Mode CE=VIL ZZ=VIH CE=VIL ZZ=VIH CE=VIH ZZ=VIL CE=VIH ZZ=VIH ZZ=VIL DPD Mode Standby Mode ZZ=VIH Standby Mode Characteristics Mode Memory Cell Data Standby Current(µA) Wait Time(µS) Standby DPD Mode Valid Invalid 70 25(IZZ) 0 300 8 Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 IC66LV10016AL READ CYCLE tRC Address tOHA tAA tACE CE tAHC tASC tHZCE tBA UB,LB tASO tHZB tDOE OE tLZOE tHZOE tLZB tLZCE Data Out ZZ and WE must be H level for entire read cycle WRITE CYCLE (WE Control) tWC Address tAW tSCE CE tPWB UB,LB tHA tSA tPWE WE tSD tHD Data In ZZ and OE must be H level for entire read cycle Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 9 IC66LV10016AL WRITE CYCLE (LB UB Control) tWC Address tAW tAHC tSCE CE tASC tHA tPWB tSA UB,LB tPWE WE tSD tHD Data In ZZ and OE must be H level for entire read cycle STANDBY Address tCP CE tAHC Active 10 tASC Standby Active Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 IC66LV10016AL Power Down Mode Entry / Exit CE tSHP tHPD tC2LP ZZ tSSP Power Up CE tSHU tHPU ZZ VCC VCC(min) Data Retention(1) tBAH Address (A19-A2) CE This applies for both read and write Data Retention(2) tCSH No Change Address (A19-A2) CE This applies for both read and write Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 11 IC66LV10016AL Address Skew(1) A0-A19 tSKEN tRC / tWC CE tSKEN is from first address change to last address change Address Skew(2) A0-A19 tRC / tWC tSKEN CE tSKEN is from first address change to last address change Address Skew(2) A0-A19 tSKEN CE tSKEN is from first address change to last address change 12 Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 IC66LV10016AL ORDERING INFORMATION Temperature Range: -25°C to +85°C Order Part No. Speed (ns) IC66LV10016AL-70B 70 Package 6*8mm TFBGA Integrated Circuit Solution Inc. HEADQUARTER: NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, HSIN-CHU, TAIWAN, R.O.C. TEL: 886-3-5780333 Fax: 886-3-5783000 BRANCH OFFICE: 7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD, HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. TEL: 886-2-26962140 FAX: 886-2-26962252 http://www.icsi.com.tw Integrated Circuit Solution Inc. PSR002-0A 02/05/2004 13