ON MC14536BCPG Programmable timer Datasheet

MC14536B
Programmable Timer
The MC14536B programmable timer is a 24−stage binary ripple
counter with 16 stages selectable by a binary code. Provisions for an
on−chip RC oscillator or an external clock are provided. An on−chip
monostable circuit incorporating a pulse−type output has been
included. By selecting the appropriate counter stage in conjunction
with the appropriate input clock frequency, a variety of timing can be
achieved.
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MARKING
DIAGRAMS
Features
•
•
•
•
•
•
•
•
•
•
•
•
24 Flip−Flop Stages − Will Count From 20 to 224
Last 16 Stages Selectable By Four−Bit Select Code
8−Bypass Input Allows Bypassing of First Eight Stages
Set and Reset Inputs
Clock Inhibit and Oscillator Inhibit Inputs
On−Chip RC Oscillator Provisions
On−Chip Monostable Output Provisions
Clock Conditioning Circuit Permits Operation with Very Long Rise
and Fall Times
Test Mode Allows Fast Test Sequence
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Schottky TTL Load over the Rated Temperature Range
Pb−Free Packages are Available*
MC14536BCP
AWLYYWWG
PDIP−16 1
P SUFFIX
CASE 648
1
14536B
AWLYWWG
1
SOIC−16 WB
DW SUFFIX
CASE 751G
1
MAXIMUM RATINGS (Voltages Referenced to VSS)
Rating
Symbol
Value
Unit
DC Supply Voltage Range
VDD
−0.5 to +18.0
V
Input or Output Voltage Range
(DC or Transient)
Vin,
Vout
−0.5 to VDD + 0.5
V
Iin, Iout
± 10
mA
Power Dissipation per Package (Note 1)
PD
500
mW
Ambient Temperature Range
TA
−55 to +125
°C
Storage Temperature Range
Tstg
−65 to +150
°C
Lead Temperature, (8−Second Soldering)
TL
260
°C
Input or Output Current
(DC or Transient) per Pin
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C from 65_C to 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS v (Vin or Vout) v VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
MC14536B
ALYWG
1
SOEIAJ−16
F SUFFIX
CASE 966
A
WL, L
YY, Y
WW, W
G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
April, 2006 − Rev. 9
1
Publication Order Number:
MC14536B/D
MC14536B
SET
1
16
VDD
RESET
2
15
MONO−IN
IN 1
3
14
OSC INH
OUT 1
4
13
DECODE
12
D
OUT 2
5
8−BYPASS
6
11
C
CLOCK INH
7
10
B
VSS
8
9
A
Figure 1. Pin Assignment
CLOCK INH.
7
RESET SET 8 BYPASS
2
1 6
OSC. INHIBIT14
IN1
STAGES 9 THRU 24
Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q Q
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
STAGES
1 THRU 8
3
4
OUT1
5
OUT2
A9
B10
C11
D12
VDD = PIN 16
VSS = PIN 8
DECODER
MONO−IN15
MONOSTABLE
MULTIVIBRATOR
Figure 2. Block Diagram
FUNCTION TABLE
Set
Reset
Clock
Inh
OSC
Inh
0
0
0
0
No
Change
0
0
0
0
Advance to
next state
X
1
0
0
0
0
1
1
X
0
1
0
0
0
1
0
X
0
0
1
0
−
−
No
Change
X
0
0
0
1
0
1
No
Change
0
0
0
0
X
0
1
No
Change
1
0
0
0
In1
Out 1
Out 2
Decode
Out
Advance to
next state
X = Don’t Care
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2
13
DECODE
OUT
MC14536B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
− 55_C
25_C
125_C
Min
Max
Min
Typ
(Note 2)
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
−
−
−
0.05
0.05
0.05
−
−
−
0
0
0
0.05
0.05
0.05
−
−
−
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
−
−
−
4.95
9.95
14.95
5.0
10
15
−
−
−
4.95
9.95
14.95
−
−
−
Vdc
“0” Level
VIL
5.0
10
15
−
−
−
1.5
3.0
4.0
−
−
−
2.25
4.50
6.75
1.5
3.0
4.0
−
−
−
1.5
3.0
4.0
5.0
10
15
3.5
7.0
11
−
−
−
3.5
7.0
11
2.75
5.50
8.25
−
−
−
3.5
7.0
11
−
−
−
Source
Pins 4 & 5
5.0
5.0
10
15
– 1.2
– 0.25
– 0.62
– 1.8
−
−
−
−
– 1.0
– 0.25
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
−
−
−
−
– 0.7
– 0.14
– 0.35
– 1.1
−
−
−
−
Source
Pin 13
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
−
−
−
−
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
−
−
−
−
– 1.7
– 0.36
– 0.9
– 2.4
−
−
−
−
mAdc
IOL
5.0
10
15
0.64
1.6
4.2
−
−
−
0.51
1.3
3.4
0.88
2.25
8.8
−
−
−
0.36
0.9
2.4
−
−
−
mAdc
Input Current
Iin
15
−
± 0.1
−
± 0.00001
± 0.1
−
± 1.0
mAdc
Input Capacitance
(Vin = 0)
Cin
−
−
−
−
5.0
7.5
−
−
pF
Quiescent Current (Per Package)
IDD
5.0
10
15
−
−
−
5.0
10
20
−
−
−
0.010
0.020
0.030
5.0
10
20
−
−
−
150
300
600
mAdc
IT
5.0
10
15
Characteristic
Output Voltage
Vin = VDD or 0
Symbol
Vin = 0 or VDD
Input Voltage
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
“1” Level
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
VIH
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
VDD
Vdc
Vdc
IOH
Sink
Total Supply Current (Note 3, 4)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
mAdc
IT = (1.50 mA/kHz) f + IDD
IT = (2.30 mA/kHz) f + IDD
IT = (3.55 mA/kHz) f + IDD
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.
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3
mAdc
MC14536B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise and Fall Time (Pin 13)
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
Propagation Delay Time
Clock to Q1, 8−Bypass (Pin 6) High
tPLH, tPHL = (1.7 ns/pF) CL + 1715 ns
tPLH, tPHL = (0.66 ns/pF) CL + 617 ns
tPLH, tPHL = (0.5 ns/pF) CL + 425 ns
tPLH,
tPHL
5.0
10
15
−
−
−
100
50
40
200
100
80
ns
ns
5.0
10
15
−
−
−
3.8
1.5
1.1
7.6
3.0
2.3
5.0
10
15
−
−
−
7.0
3.0
2.2
14
6.0
4.5
5.0
10
15
−
−
−
1500
600
450
3000
1200
900
tWH
5.0
10
15
600
200
170
300
100
85
−
−
−
ns
fcl
5.0
10
15
−
−
−
1.2
3.0
5.0
0.4
1.5
2.0
MHz
tTLH,
tTHL
5.0
10
15
tWH
5.0
10
15
Reset to Qn
tPHL = (1.7 ns/pF) CL + 1415 ns
tPHL = (0.66 ns/pF) CL + 567 ns
tPHL = (0.5 ns/pF) CL + 425 ns
tPHL
ms
ms
ns
−
No Limit
1000
400
300
500
200
150
−
−
−
5. The formulas given are for the typical characteristics only at 25_C.
6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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4
Unit
3600
1300
1000
tPLH,
tPHL
Reset Pulse Width
Max
1800
650
450
Clock to Q16
tPHL, tPLH = (1.7 ns/pF) CL + 6915 ns
tPHL, tPLH = (0.66 ns/pF) CL + 2967 ns
tPHL, tPLH = (0.5 ns/pF) CL + 2175 ns
Clock Rise and Fall Time
Typ (Note 6)
−
−
−
tPLH,
tPHL
Clock Pulse Frequency (50% Duty Cycle)
Min
5.0
10
15
Clock to Q1, 8−Bypass (Pin 6) Low
tPLH, tPHL = (1.7 ns/pF) CL + 3715 ns
tPLH, tPHL = (0.66 ns/pF) CL + 1467 ns
tPLH, tPHL = (0.5 ns/pF) CL + 1075 ns
Clock Pulse Width
VDD
ns
MC14536B
PIN DESCRIPTIONS
INPUTS
OSC INHIBIT (Pin 14) − A high level on this pin stops the
RC oscillator which allows for very low−power standby
operation. May also be used, in conjunction with an external
clock, with essentially the same results as the Clock Inhibit
input.
MONO−IN (Pin 15) − Used as the timing pin for the
on−chip monostable multivibrator. If the Mono−In input is
connected to VSS, the monostable circuit is disabled, and
Decode Out is directly connected to the selected Q output.
The monostable circuit is enabled if a resistor is connected
between Mono−In and VDD. This resistor and the device’s
internal capacitance will determine the minimum output
pulse widths. With the addition of an external capacitor to
VSS, the pulse width range may be extended. For reliable
operation the resistor value should be limited to the range of
5 kW to 100 kW and the capacitor value should be limited to
a maximum of 1000 pf. (See figures 5, 6, 7, and 12).
A, B, C, D (Pins 9, 10, 11, 12) − These inputs select the
flip−flop stage to be connected to Decode Out. (See the truth
tables.)
SET (Pin 1) − A high on Set asynchronously forces Decode
Out to a high level. This is accomplished by setting an output
conditioning latch to a high level while at the same time
resetting the 24 flip−flop stages. After Set goes low (inactive),
the occurrence of the first negative clock transition on IN1
causes Decode Out to go low. The counter’s flip−flop stages
begin counting on the second negative clock transition of IN1.
When Set is high, the on−chip RC oscillator is disabled. This
allows for very low−power standby operation.
RESET (Pin 2) − A high on Reset asynchronously forces
Decode Out to a low level; all 24 flip−flop stages are also reset
to a low level. Like the Set input, Reset disables the on−chip
RC oscillator for standby operation.
IN1 (Pin 3) − The device’s internal counters advance on the
negative−going edge of this input. IN1 may be used as an
external clock input or used in conjunction with OUT1 and
OUT2 to form an RC oscillator. When an external clock is
used, both OUT1 and OUT2 may be left unconnected or used
to drive 1 LSTTL or several CMOS loads.
8−BYPASS (Pin 6) − A high on this input causes the first 8
flip−flop stages to be bypassed. This device essentially
becomes a 16−stage counter with all 16 stages selectable.
Selection is accomplished by the A, B, C, and D inputs. (See
the truth tables.)
CLOCK INHIBIT (Pin 7) − A high on this input
disconnects the first counter stage from the clocking source.
This holds the present count and inhibits further counting.
However, the clocking source may continue to run.
Therefore, when Clock Inhibit is brought low, no oscillator
startup time is required. When Clock Inhibit is low, the
counter will start counting on the occurrence of the first
negative edge of the clocking source at IN1.
OUTPUTS
OUT1, OUT2 (Pin 4, 5) − Outputs used in conjunction with
IN1 to form an RC oscillator. These outputs are buffered and
may be used for 20 frequency division of an external clock.
DECODE OUT (Pin 13) − Output function depends on
configuration. When the monostable circuit is disabled, this
output is a 50% duty cycle square wave during free run.
TEST MODE
The test mode configuration divides the 24 flip−flop
stages into three 8−stage sections to facilitate a fast test
sequence. The test mode is enabled when 8−Bypass, Set and
Reset are at a high level. (See Figure 10.)
TRUTH TABLES
Input
Input
Stage Selected
for Decode Out
8−Bypass
D
C
B
A
Stage Selected
for Decode Out
8−Bypass
D
C
B
A
0
0
0
0
0
9
1
0
0
0
0
1
0
0
0
0
1
10
1
0
0
0
1
2
0
0
0
1
0
11
1
0
0
1
0
3
0
0
0
1
1
12
1
0
0
1
1
4
0
0
1
0
0
13
1
0
1
0
0
5
0
0
1
0
1
14
1
0
1
0
1
6
0
0
1
1
0
15
1
0
1
1
0
7
0
0
1
1
1
16
1
0
1
1
1
8
0
1
0
0
0
17
1
1
0
0
0
9
0
1
0
0
1
18
1
1
0
0
1
10
0
1
0
1
0
19
1
1
0
1
0
11
0
1
0
1
1
20
1
1
0
1
1
12
0
1
1
0
0
21
1
1
1
0
0
13
0
1
1
0
1
22
1
1
1
0
1
14
0
1
1
1
0
23
1
1
1
1
0
15
0
1
1
1
1
24
1
1
1
1
1
16
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5
IN1
3
SET
1
4
OUT 1
OSC INHIBIT
14
OUT 2
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6
7
CLOCK
INHIBIT
5
En R
C
S
Q
T 1
RESET
2
STAGES
2 THRU 7
8
15
MONO−IN
A9
B10
C11
D12
T 9
6
8−BYPASS
STAGES
10 THRU
15
16
DECODER
OUT
13
DECODER
VSS = PIN 8
STAGES
18 THRU
23
VDD = PIN 16
17
24
MC14536B
LOGIC DIAGRAM
MC14536B
TYPICAL RC OSCILLATOR CHARACTERISTICS
(For Circuit Diagram See Figure 13 In Application)
8.0
100
f, OSCILLATOR FREQUENCY (kHz)
FREQUENCY DEVIATION (%)
VDD = 15 V
4.0
0
10 V
−4.0
−8.0
5.0 V
−12
RTC = 56 kW,
C = 1000 pF
−16
−55
−25
*Device Only.
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C
RS = 120 kW, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)*
100
VDD = 10 V
50
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS ≈ 2RTC)
20
10
5.0
2.0
1.0
0.5
f AS A FUNCTION
OF C
(RTC = 56 kW)
(RS = 120 k)
0.2
0.1
1.0 k
125
10 k
100 k
RTC, RESISTANCE (W)
0.001
0.01
C, CAPACITANCE (mF)
0.0001
Figure 3. RC Oscillator Stability
1.0 M
0.1
Figure 4. RC Oscillator Frequency as a
Function of RTC and C
MONOSTABLE CHARACTERISTICS
(For Circuit Diagram See Figure 12 In Application)
100
10
t W, PULSE WIDTH ( μs)
FORMULA FOR CALCULATING tW IN
MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 • RX • (CX)0.85
WHERE R IS IN kW, CX IN pF.
RX = 100 kW
50 kW
1.0
10 kW
5 kW
10
1.0
FORMULA FOR CALCULATING tW IN
MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 • RX • (CX)0.85
WHERE R IS IN kW, CX IN pF.
RX = 100 kW
50 kW
10 kW
5 kW
TA = 25°C
VDD = 5 V
0.1
1.0
10
100
CX, EXTERNAL CAPACITANCE (pF)
0.1
1000
1.0
Figure 5. Typical CX versus Pulse Width
@ VDD = 5.0 V
100
t W, PULSE WIDTH ( μs)
t W, PULSE WIDTH ( μs)
100
10
TA = 25°C
VDD = 10 V
10
100
CX, EXTERNAL CAPACITANCE (pF)
Figure 6. Typical CX versus Pulse Width
@ VDD = 10 V
FORMULA FOR CALCULATING tW IN
MICROSECONDS IS AS FOLLOWS:
tW = 0.00247 • RX • (CX)0.85
WHERE R IS IN kW, CX IN pF.
RX = 100 kW
50 kW
1.0
10 kW
5 kW
0.1
1.0
TA = 25°C
VDD = 15 V
10
100
CX, EXTERNAL CAPACITANCE (pF)
Figure 7. Typical CX versus Pulse Width
@ VDD = 15 V
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7
1000
1000
MC14536B
VDD
0.01 mF
CERAMIC
ID
500 mF
SET
RESET OUT 1
8−BYPASS
IN1
C INH
MONO−IN OUT
2
OSC INH
PULSE
GENERATOR
A
B
C
D
CL
CL
DECODE
OUT
VDD
PULSE
GENERATOR
CL
20 ns
50%
IN1
tWL
SET
OUT 1
RESET
8−BYPASS
IN1
C INH
MONO−IN OUT
2
OSC INH
A
B
C
DECODE
OUT
D
VSS
20 ns
20 ns
20 ns
OUT
tPLH
tWH
90%
10%
50%
tTLH
tTHL
CL
VSS
90%
50%
10%
50%
DUTY CYCLE
Figure 8. Power Dissipation Test
Circuit and Waveform
Figure 9. Switching Time Test Circuit and Waveforms
VDD
FUNCTIONAL TEST SEQUENCE
Test function (Figure 10) has been included for the
reduction of test time required to exercise all 24 counter
stages. This test function divides the counter into three
8−stage sections and 255 counts are loaded in each of the
8−stage sections in parallel. All flip−flops are now at a “1”.
The counter is now returned to the normal 24−stages in
series configuration. One more pulse is entered into In1
which will cause the counter to ripple from an all “1” state
to an all “0” state.
PULSE
GENERATOR
SET
RESET OUT 1
8−BYPASS
IN1
C INH
MONO−IN OUT
2
OSC INH
A
B
C
D
Figure 10. Functional
Test Circuit
DECODE
OUT
VSS
FUNCTIONAL TEST SEQUENCE
Inputs
Outputs
Comments
All 24 stages are in Reset mode.
In1
Set
Reset
8−Bypass
Decade Out
Q1 thru Q24
1
0
1
1
0
1
1
1
1
0
Counter is in three 8 stage sections in parallel mode.
0
1
1
1
0
First “1” to “0” transition of clock.
1
0
−
−
−
1
1
1
0
1
1
1
1
The 255 “1” to “0” transition.
0
0
0
0
1
Counter converted back to 24 stages in series mode.
Set and Reset must be connected together and simultaneously
go from “1” to “0”.
1
0
0
0
1
In1 Switches to a “1”.
0
0
0
0
0
Counter Ripples from an all “1” state to an all “0” state.
255 “1” to “0” transitions are clocked in the counter.
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8
tPHL
MC14536B
+V
16
6
9
8−BYPASS
VDD
A
10 B
11 C
12
2
14
15
1
PULSE
GEN.
7
PULSE
GEN.
3
OUT 1
D
RESET
4
OUT 2
5
DECODE OUT
13
OSC INH
MONO−IN
SET
CLOCK INH
IN1
CLOCK
VSS
8
IN1
SET
CLOCK INH
DECODE OUT
POWERUP
NOTE: When power is first applied to the device, DECODE OUT can be either at a high or low state. On the rising edge of a SET pulse
the output goes high if initially at a low state. The output remains high if initially at a high state. Because CLOCK INH is held
high, the clock source on the input pin has no effect on the output. Once CLOCK INH is taken low, the output goes low on the
first negative clock transition. The output returns high depending on the 8−BYPASS, A, B, C, and D inputs, and the clock input
period. A 2n frequency division (where n = the number of stages selected from the truth table) is obtainable at DECODE OUT.
A 20–divided output of IN1 can be obtained at OUT1 and OUT2.
Figure 11. Time Interval Configuration Using an External Clock, Set, and Clock Inhibit Functions
(Divide−by−2 Configured)
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9
MC14536B
+V
6
RX
9
A
10 B
11 C
12
PULSE
GEN.
2
1
7
15
14
3
CLOCK
8−BYPASS
16
VDD
OUT 1
D
4
OUT 2
5
DECODE OUT
13
RESET
SET
CLOCK INH
MONO−IN
OSC INH
IN1
VSS
8
CX
IN1
RESET
*tw ≈ .00247 • RX • CX0.85
tw in msec
RX in kW
CX in pF
DECODE OUT
POWERUP
*tw
NOTE: When Power is first applied to the device with the RESET input going high, DECODE OUT initializes low. Bringing the RESET
input low enables the chip’s internal counters. After RESET goes low, the 2n/2 negative transition of the clock input causes
DECODE OUT to go high. Since the MONO−IN input is being used, the output becomes monostable. The pulse width of the
output is dependent on the external timing components. The second and all subsequent pulses occur at 2n x (the clock period)
intervals where n = the number of stages selected from the truth table.
Figure 12. Time Interval Configuration Using an External Clock, Reset, and
Output Monostable to Achieve a Pulse Output
(Divide−by−4 Configured)
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10
MC14536B
+V
RS
16
6
8−BYPASS
VDD
9
A
10 B
11 C
12
PULSE
GEN.
2
14
15
1
7
3
OUT 1
4
C
RTC
D
OUT 2
RESET
5
OSC INH
MONO−IN
SET
CLOCK INH
IN1
VSS
8
DECODE OUT 13
RESET
OUT 1
1
fosc ^
2.3 Rtc C
Rs ≥ Rtc
F = Hz
R = Ohms
C = FARADS
OUT 2
DECODE OUT
POWERUP
tw
NOTE: This circuit is designed to use the on−chip oscillation function. The oscillator frequency is determined by the external R and C
components. When power is first applied to the device, DECODE OUT initializes to a high state. Because this output is tied directly
to the OSC INH input, the oscillator is disabled. This puts the device in a low−current standby condition. The rising edge of the
RESET pulse will cause the output to go low. This in turn causes OSC INH to go low. However, while RESET is high, the oscillator
is still disabled (i.e.: standby condition). After RESET goes low, the output remains low for 2n/2 of the oscillator’s period. After the
part times out, the output again goes high.
Figure 13. Time Interval Configuration Using On−Chip RC Oscillator and
Reset Input to Initiate Time Interval (Divide−by−2 Configured)
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11
MC14536B
ORDERING INFORMATION
Device
Package
MC14536BCP
PDIP−16
MC14536BCPG
PDIP−16
(Pb−Free)
MC14536BDW
SOIC−16
MC14536BDWG
SOIC−16
(Pb−Free)
MC14536BDWR2
SOIC−16
MC14536BDWR2G
SOIC−16
(Pb−Free)
MC14536BFEL
SOEIAJ−16
MC14536BFELG
SOEIAJ−16
(Pb−Free)
Shipping †
25 Units / Rail
47 Units / Rail
1000 / Tape & Reel
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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12
MC14536B
PACKAGE DIMENSIONS
PDIP−16
CASE 648−08
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
−A−
16
9
1
8
B
F
C
L
S
−T−
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
T A
M
M
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740 0.770
0.250 0.270
0.145 0.175
0.015 0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008 0.015
0.110 0.130
0.295 0.305
0_
10 _
0.020 0.040
MILLIMETERS
MIN
MAX
18.80 19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
SOIC−16WB
CASE 751G−03
ISSUE C
A
D
9
h X 45 _
E
0.25
1
MILLIMETERS
DIM MIN
MAX
A
2.35
2.65
A1 0.10
0.25
B
0.35
0.49
C
0.23
0.32
D 10.15 10.45
E
7.40
7.60
e
1.27 BSC
H 10.05 10.55
h
0.25
0.75
L
0.50
0.90
q
0_
7_
8
16X
M
14X
e
T A
S
B
S
L
A
0.25
B
B
A1
H
8X
M
B
M
16
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN
EXCESS OF THE B DIMENSION AT MAXIMUM
MATERIAL CONDITION.
SEATING
PLANE
T
C
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13
MC14536B
PACKAGE DIMENSIONS
SOEIAJ−16
CASE 966−01
ISSUE A
16
LE
9
Q1
M_
E HE
1
8
L
DETAIL P
Z
D
e
VIEW P
A
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
A1
b
0.13 (0.005)
c
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
M
0.10 (0.004)
MILLIMETERS
MIN
MAX
−−−
2.05
0.05
0.20
0.35
0.50
0.10
0.20
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
−−−
0.78
INCHES
MIN
MAX
−−− 0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
−−− 0.031
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer
purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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Phone: 81−3−5773−3850
Email: [email protected]
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ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.
MC14536B/D