ELMOS E521.02 High efficiency 5v dc/dc buck converter Datasheet

CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Features
Applications
• High efficiency 5V DC/DC buck converter
• Body control units, gateways
• Optional DC/DC boost converter
General Description
• Wakeable HS-CAN transceiver (ISO11898-2 and -5)
• Up to four LIN transceiver LIN 2.1, SAE-J2602 conformance
• Operating range 2.5V up to 28V
• Typ. 45µA sleep current consumption
• Typ. 85µA standby current consumption with active DC/DC
buck converter
• Configurable µC watchdog (cycle time and type)
• BUS pins ESD-protected 8kV according to IEC-61000-4-2
• Package QFN44L7
with Booster
E521.12
E521.13
E521.14
Without Booster
E521.02
E521.03
E521.04
No. of LINs
2
3
4
The CAN/LIN SBC family with DC/DC voltage regulator provides beside the CAN and LIN tranceivers the main µC power supply with a high efficiency DC/DC converter. An additional linear regulator can be used independently as peripheral supply. All supplies are monitored and can signalize a
fail event by SPI interface. The main DC/DC supply monitor can generate a µC reset. System failure can activate a fail-safe output signal for limp
home support.
The CAN/LIN SBC family provides SLEEP, STOP,
ACTIVE and FAILSAFE states.
The device is capable of detecting local and
remote wake-up events which can be individually
enabled via SPI.
Typical Applications Circuit
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Functional Diagram
VS
VS
DC/DC
Buck
converter
VDD1
GND
RSTN
INTN
Watch
dog
Reset
generation
VS
Voltage
Regulator
5V
ENVDD2
SWDM
VS
CONTROL
CSN
SDI
SDO
CLK
Fail safe
lowside
FSON
VS
WK
WUCAN
CAN_EN
Wake
LIN_ENx
WULINx
RXDCAN
TXDCAN
VDD2
EN_V2
VIN
PGND
LXT
VDD1SENSE
Optional blocks
EN_BUK
DC/DC
Boost
converter
EN_BST
MDRV
ISEN
PGND2
HS-CAN
Transceiver
VDDCAN
CANH
CANL
VDD1
RXDLIN1
TXDLIN1
RXDLINx
TXDLINx
LIN
Transceiver
LIN
Transceiver
LIN1
GNDLIN
LINx
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
2 / 82
QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
35
34
36
37
38
40
39
41
42
1
33
2
32
3
31
4
30
5
29
ELA-0158
6
28
22
21
20
19
PGND
VDD1SENSE
VDDCAN
CANH
CANL
VDD1
GND
SWDM
ENVDD2
TXDCAN
RXDCAN
TXDLIN1
RXDLIN1
LIN1
LIN2
GNDLIN
LIN3
LIN4
CSN
SDI
SCK
SDO
18
23
16
24
11
17
25
10
15
26
9
14
27
8
13
7
12
FSON
RSTN
INTN
TXDLIN4
RXDLIN4
VDD1
GND
TXDLIN3
RXDLIN3
TXDLIN2
RXDLIN2
43
44
VDD2
MDRV
ISEN
PGND2
WK
VS
n.c.
VIN
VIN
n.c.
LXT
Pin Configuration
Note: Top view, not to scale
Pin Description
Pin
Name
Type
Description
1
FSON
O
Fail safe output, open drain stage, low active
2
RSTN
IO
Reset output, low active, pull up
3
INTN
IO
4
TXDLIN4
I
5
RXDLIN4
O
6
VDD1
S
Voltage Supply 1
7
GND
S
Ground
8
TXDLIN3
I
Interrupt output, low active, pull up
Setup for bit SBC.CFG
LIN4 transmit data, pull up, optional
E521.04/.14, only all other versions are not connected
LIN4 receive data
E521.04/.14 only, all other versions are not connected
LIN3 transmit data, pull up, optional
E521.03/.04/.13/.14 only, all other versions are not connected
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
3 / 82
QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Pin
Name
Type
9
RXDLIN3
O
10
TXDLIN2
I
LIN2 transmit data, pull up
11
RXDLIN2
O
LIN2 receive data
12
TXDLIN1
I
LIN1 transmit data, pull up
13
RXDLIN1
O
LIN1 receive data
14
LIN1
IO
LIN1 bus line
15
LIN2
IO
LIN2 bus line
16
GND
S
LIN ground
17
LIN3
IO
18
LIN4
IO
19
CSN
I
SPI chip select, low active, pull up
20
SDI
I
SPI serial data input
21
SCK
I
SPI clock, pull down
22
SDO
O
SPI serial data output
23
RXDCAN
O
CAN receive data
24
TXDCAN
I
CAN transmit data, pull up
25
ENVDD2
I
Enables VDD2
26
SWDM
I
27
GND
S
Ground
28
VDD1
S
Voltage Supply 1
29
CANL
IO
CANL bus Line
30
CANH
IO
CANH bus Line
31
VDDCAN
S
HS-CAN supply
32
VDD1SENSE
33
PGND
S
34
LXT
IO
IO
Description
LIN3 receive data
E521.03/.04/.13/.14 only, all other versions are not connected
LIN3 bus line,
E521.03/.04/.13/.14 only, all other versions are not connected
LIN4 bus line,
E521.04/.14 only, all other versions are not connected
Must be connected to GND in application
Enables software development function, pull down
VDD1 Sense Back to DCDC Buck Converter
DCDC Buck Converter Power Ground
DCDC Buck Converter
Integrated Highside Switch Output
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Data Sheet
4 / 82
QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Pin
Name
Type
Description
35
n.c.
36
VIN
S
DCDC Supply
37
VIN
S
DCDC Supply
38
n.c.
39
VS
S
Battery supply voltage
40
WK
I
Local wake up input, pull up or pull down
41
PGND2
S
42
ISEN
I
43
MDRV
O
44
VDD2
S
Peripheral voltage supply
-
EP
S
Exposed Pad. Connect to large copper ground plane for optimal heat dissipation. Connect to GNDA and GNDD.
Not connected
Not connected, leave open
Power ground 2 (Boost Converter),
E521.12/.13/.14 only, all other versions are not connected
Sense Input (Boost Converter),
E521.12/.13/.14 only, all other versions are not connected
Main Gate Driver Output (Boost Converter),
E521.12/.13/.14 only, all other versions are not connected
Note: S = Supply, I/O = Input/Output
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
1 Absolute Maximum Ratings
Stresses beyond these absolute maximum ratings listed below may cause permanent damage to the device. These are stress ratings only;
operation of the device at these or any other conditions beyond those listed in the operational sections of this document is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. All voltages with respect to ground.
Currents flowing into terminals are positive, those drawn out of a terminal are negative.
Description
Condition
Symbol
Min
Max
Unit
Voltage at VS 1), 2)
continuous
VVS
-0.3
40
V
Voltage at VIN 1), 2)
continuous
VVS
-0.3
40
V
Voltage at WK, FSON, ENVDD
continuous
VWK
-0.3
40
V
Voltage at LIN1..4, CANL, CANL
continuous
VCANL
-27
40
V
Voltage at LXT
continuous
VLXT
-2
VVIN + 0.3
V
Voltage at VDDCAN
continuous
VVDDCAN
-0.3
5.5
V
Voltage at SWDM
continuous
VSWDM
-0.3
5.5
V
Voltage at digital pins TXDLIN1..4,
RXDLIN1..4, TXDCAN, RXDCAN
continuous
VTXDLIN
-0.3
VVDD1+0.3
V
Voltage at VDD1
continuous
VVDD1
-0.3
5.5
V
Voltage at VDD2
continuous
VVDD2
-5
40
V
Current at WK
continuous
IWK
-15
1
mA
Current of VDD1
continuous
IVDD1
-500
Current of VDD2, internally limited
continuous
IVDD2
-200
1
mA
Current at ENVDD2
continuous
IENVDD2
-15
1
mA
10
pF
Maximum load at RXDCAN
CRXDCAN,LOAD
mA
Junction temperature
continuous
TJUNC
-40
150
°C
Storage temperature
continuous
TSTG
-55
125
°C
1)
2)
The device is implicitly protected against load dump
The device is implicitly protected against jump start
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Data Sheet
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
2 ESD Protection
Description
Condition
Symbol
Min
Max
Unit
ESD HBM protection
pins VDD2, LINx, WK, CANH and CANL
1)
VESD(HBM)
-8
+8
kV
ESD HBM protection
all other pins
1)
VESD(HBM)
-2
+2
kV
VESD(IEC)
-6
+6
kV
ESD system level protection
pins VDD2, LINx, WK, CANH and CANL
3)
ESD CDM Protection at all Pins
2)
VESD(CDM)
-500
+500
V
ESD CDM Protection at Edge Pins
2)
VESD(CDM)C
-750
+750
V
to ground
According to AEC-Q100-002 (HBM) chip level test, C=100pF, R=1.5kΩ
2)
According to AEC-Q100-011 (CDM) chip level test, R=1Ω
2)
Similar to IEC61000-4-2, C=150pF, R=330Ω
1)
3 Recommended Operating Conditions
Description
Symbol
Min
Typ
Max
Unit
Functional range E521.02..04
VVS,FUNC
5.5
-
28
V
Functional range E521.12..14
VVS,FUNC
2.5
-
28
V
Limited functional range E521.02..04
VVS,FL,LR
2.5
-
5.5
V
Limited functional range
E521.02..04, E521.12..14
VVS,FL,HR
28
-
40
V
TAMB
-40
-
125
°C
Ambient temperature
Condition
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Data Sheet
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
4 Electrical Characteristics
(VVS = 5.5V to 28V, TAMB = -40°C to +125°C, unless otherwise noted. Typical values are at VVS = 12.0V and TAMB = +25°C. Positive currents flow
into the device pins.)
4.1 Power Supply and References; pins VS, GND
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
1
Current consumption in SBC
mode SLEEP 1)
SBC mode SLEEP,
VS = VLIN = VWK =
13.5V, IVDD1= 0mA,
IVDD2= 0mA, TJ<40°C,
Booster is off
All wake up sources
enabled
IVS,SLEEP
45
110
µA
1a
Current consumption in SBC
mode SLEEP 1)
SBC mode SLEEP,
VS = VLIN = VWK =
13.5V, IVDD1= 0mA,
IVDD2= 0mA, TJ>40°C,
Booster is off
All wake up sources
enabled
IVS,SLEEP,40
65
150
µA
2
Current share for CAN wake up VS = 13.5V
capability in SBC mode SLEEP
Not production tested
IVS,CAN,SLEEP
5
10
µA
3
Current share for LIN wake up VS = 13.5V
capability in SBC mode SLEEP
Not production tested
IVS,LIN,SLEEP
2
5
µA
Table 1: DC Characteristics SLEEP
1) not production tested
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Data Sheet
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
1
Current consumption in SBC mode SBC mode STOP,
STOP without booster
VVS = VLIN = VWK =
13.5V, IVDD1= 0mA,
CAN off, LIN off,
VDD2 off, All wake
up sources
enabled, TJ>40°
IVS,STB,T<=125°C
100
170
µA
1a
Current consumption in SBC
mode STOP without booster
SBC mode STOP,
VVS = VLIN = VWK =
13.5V, IVDD1= 0mA,
CAN off, LIN off,
VDD2 off, All wake
up sources
enabled, TJ<40°
IVS,STB,T<=40°C
85
140
µA
2
Additional current if VDD2 has
load
VVS = 13.5V, IVDD2 =
-40mA
IVS,VDD2
0.1*IVDD2
mA
3
Current consumption of VDD2
voltage regulator in case of low
load of 0.2mA 1)
VVS = 13.5V,
IVDD2 = -0.2mA
IVS,VDD2,0.2mA
1
mA
4
Additional current in SBC mode
STOP Mode,
STOP if cyclic wake up enabled 1) VVS = VLIN = VWK =
13.5V,
Cyclic wake up
enabled
IVS,STB,CYCLIC
10
μA
Table 2: DC Characteristics STOP
No.
1
Description
Condition
Symbol
Typ
Max
Unit
IVS,NOM
150
400
μA
LIN dominant
IVS,LIN,ACT,DOM
1.5
3
mA
NORMAL mode current
Min
consumption
2
Current consumption in active
mode for all LINs
not production tested
3
Current consumption in active
mode for all LINs
LIN recessive
IVS,LIN,ACT,REC
0.25
0.5
mA
4
Current consumption in active
mode for CAN
CAN recessive
IVDDCAN,CAN,ACT,REC
1
3
mA
5
Current consumption in active
mode for CAN
CAN dominant
IVDDCAN,CAN,ACT,DOM
40
105
mA
not production tested
Table 3: DC Characteristics NORMAL
1) not production tested
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Data Sheet
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
1
Power on threshold according to
pin VS
VVS,PU
4
5
V
2
Power down threshold according
to pin VS
VVS,PD
2.0
2.5
V
Symbol
Min
Max
Unit
tOSC
0.875
1.125
μs
Symbol
Min
Typ
Max
Unit
tTO,INIT
230
256
290
ms
1.4
1.5
1.8
s
Table 4: DC Characteristics POR
4.1.1 Internal Time Base
No.
1
Description
Condition
Internal time base, started automatically on demand. Most times
specified are derived from this
internal time base directly or by
using prescalers.
Typ
Table 5: AC Characteristics
4.2 SBC Operating Modes
No.
Description
Condition
1
time out in SBC states INIT and
RESTART
2
time out in SBC states INIT and
RESTART for VDD1 start up
VS rises above VONin before and
OFF,VS
not fallen below
VON-OFF_f,VS
tTO,VDD1
3
duration for changes between
SBC states
detection of vaild
state change condition
tMODE_CHANGE
4
VS voltage threshold to be
exceeded in order to start timeout
tTO,VDD1 1)
VON-OFF,VS
6.3
6.6
6.9
V
5
VS voltage threshold to be underflow in order to deactivate timeout
tTO,VDD1 1)
VON-OFF_f,VS
5.75
6.05
6.35
V
8
µs
Table 6: AC Characteristics
1) Hysteresis is designed to 550mV, Not production tested
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Data Sheet
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
VDD1 current observation in STOP mode
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
2.6
3.2
ms
1
Timeout for whole system to enter SPI command for
STOP mode and therefore to
STOP mode sent
decrease current consumption
tTRAN_STOP
2.3
2
Threshold for VDD1 observation, SBC mode STOP
5V system. Upper limit ensures a
safe voltage difference to VDD1 of
50mV using production test data
for each particular IC.
k1VDD1,5V
4.625
VVDD1 50mV
V
3
Minimum time VDD1 needs to stay VDD1_CFG[7:6]=
above k1VDD1
0h
t10
4.7
6.4
ms
t11
9.7
12.4
ms
t12
19.5
24.5
ms
t13
39.5
48.6
ms
tON_REG,STOP
110
160
μs
tDEL,ON
-
25
μs
After this time DCDC is switched
on for tON_REG,STOP in order to
recharge VDD1
4
Minimum time VDD1 needs to stay VDD1_CFG[7:6]=
above k1VDD1
1h
After this time DCDC is switched
on for tON_REG,STOP P in order to
recharge VDD1
5
(default)
Minimum time VDD1 needs to stay VDD1_CFG[7:6]=
above k1VDD1
2h
After this time DCDC is switched
on for tON_REG,STOP in order to
recharge VDD1
6
Minimum time VDD1 needs to stay VDD1_CFG[7:6]=
above k1VDD1
3h
After this time DCDC is switched
on for tON_REG,STOP in order to
recharge VDD1
7
On time of DCDC during regular
recharge phase
8
Internal delay of DCDC after
switching on request
STOP mode
10
Table 7: Characteristics
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Data Sheet
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
4.2.1 Configuration for transition behaviour to states FAILSAFE or RESTART
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
RINTN,SBC_CFG.CFG,PD
80
105
150
kΩ
0.7
V
1
Pull down resistance active during SBC state INIT
determination phase for
SBC_CFG.CFG
2
Voltage level for detecting logic
level low at INTN
SBC state INIT
VINTN,SBC_CFG,L
3
Voltage level for detecting logic
level high at INTN
SBC state INIT
VINTN,SBC_CFG,H
2.6
Symbol
Min
VENABLE,SWDM
0.7
RPD,SWDM
80
120
200
kΩ
Symbol
Min
Typ
Max
Unit
V
Table 8: DC Characteristics
Software Development function; pin SWDM
No.
Description
1
Voltage to be applied to pin
SWDM in order to enable software
development function
2
Pull down resistance
Condition
Typ
Max
Unit
VDD1
Table 9: DC Characteristics
Over temperature behaviour
No.
Description
Condition
1
CAN over temperature detected
CAN enabled
TOT,CAN
150
°C
2
LIN over temperature detected.
Each LIN has its own sensor.
LIN enabled
TOT,LIN
150
°C
3
VDD1 over temperature detected 1) VDD1 enabled
TOT,VDD1
150
4
VDD1 over temperature detection VDD1 enabled
hysteresis 1)
TOT,VDD1,HYST
5
VDD2 over temperature warning
detected
VDD2 enabled
TOT,VDD2,WARN
120
°C
6
Temperature difference between
failure and warning threshold
VDD2 enabled
TOT,VDD2,FAIL to WARN
10
°C
7
VDD2 over temperature detected
VDD2 enabled
TOT,VDD2,FAIL
140
8
Over temperature for aux. internal System in state
structures detected
NORMAL
TOT,INT
140
9
Over temperature detection hys- Temperature
teresis, valid for all sensors except sensor enabled
otherwise stated 1)
TOT,HYST
165
°C
40
°C
180
°C
°C
20
°C
Table 10: OT Characteristics
1) Not production tested
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Data Sheet
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
SPI communication; pins SCK, SDI, SDO, CSN
No.
Description
Condition
Symbol
Min
0.7
Typ
Max
Unit
1
High level input voltage
VCSN,INH
2
Low level input voltage
VCSN,INL
3
High level input current
VCSN = VVDD1
ICSN,LEAK
4
Pull up resistor
VCSN = 0V
RCSN,PU
5
High level input voltage
VSCK,INH
6
Low level input voltage
VSCK,INL
7
Pull down resistor
8
High level input voltage
VSDI,INH
9
Low level input voltage
VSDI,INL
0.3
VDD1
10
Low level output voltage
ISDO = 1mA
VSDO,OUTL
0.4
V
11
High level output voltage
ISDO = -1mA
VSDO,OUTH
VSCK = VVDD1
-1
VDD1
0
0.3
VDD1
1
μA
kΩ
120
0.7
VDD1
0.3
RSCK,PD
VDD1
kΩ
120
0.7
VDD1
VVDD1 0.4
V
Table 11: DC Characteristics
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Data Sheet
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
1
Serial clock cycle (1)
SCK
tSCYC
125
ns
2
SCK "H" pulse width (1)
SCK
tSHW
50
ns
3
SCK "L" pulse width (1)
SCK
tSLW
50
ns
4
data setup time (WR) (1)
SDI
tSDS
50
ns
5
data hold time (1)
SDI
tSDH
50
ns
6
access time (1)
SDO
tACC
50
ns
7
output enable time (1)
SDO
tOE
50
ns
8
output disable time (1)
SDO
tOD
50
ns
9
SCK-CSN (1)
CSN
tSCC
50
ns
10
CSN "H" pulse (1)
CSN
tCHW
5
us
Minimum time between two consecutive SPI accesses
11
CSN-SCK time (1)
CSN
tCSS
125
ns
12
output disable time (1)
CSN
tCSH
120
ns
Symbol
Min
0.85
Table 12: AC Characteristics
(1) not production tested
4.3 Watchdog; pin RSTN
No.
Description
Condition
1
Minimum watchdog time base
important for safe trigger area
tWD,PER,MIN
2
Maximum watchdog time base
important for safe trigger area
tWD,PER,MAX
3
First open window
4
Watchdog reset time
open window after
RSTN is released
Typ
Max
Unit
tWD,PER
1.15
tWD,PER
tWD,FOW
230
290
ms
tWD,RSTN
450
650
μs
Table 13: AC Characteristics
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
14 / 82
QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
4.3.1 External Reset / Reset clamping
No.
1
Description
output low level
Condition
Symbol
IRSTN= 1mA
Min
Typ
VRSTN,OUTL
Max
Unit
0.4
V
42
kΩ
0.7
V
VVDD1 > 3V
2
internal pull up resistor
VRSTN = 0V
RRSTN,PU
22
3
Voltage level for detecting low at
RSTN
VRSTN,INL
4
Voltage level for detecting high at
RSTN
VRSTN,INH
2.6
Symbol
Min
32
V
Table 14: DC Characteristics
No.
Description
1
debounce time for external applied
reset
2
time out for short detection to
VDD1
3
time out for short detection to
GND, can only be detected after
tWD,RSTN or tVDD1,RSTN
Condition
Typ
Max
Unit
tRSTN,DEB
4
ms
tRSTN,TO,VDD
16
ms
tWDRSTN,TO,GND
16
ms
Table 15: AC Characteristics
4.4 Local wake up; pin WK
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
1
Threshold of local wake up, VWK
rising
VWK rising
VWK,TH,LH
0.6
0.8
VS
2
Threshold of local wake up, VWK
falling
VWK falling
VWK,TH,HL
0.5
0.7
VS
3
Pull up current
VWK > VWK,TH,LH_max
VS - VWK > 1V
IWK,PU
-100
-10
µA
4
Pull down current
VWK < VWK,TH,HL_min
VWK > 1V
IWK_PD
10
100
µA
5
Leakage current
VS = 12V,
VWK = 0V or
VWK = VVS
IWK_LEAK
-2
+2
µA
Condition
Symbol
Min
Max
Unit
Threshold crossing
transition detected
tWK,DEB
20
30
µs
Table 16: DC Characteristics
No.
1
Description
Local wake up debounce time
Typ
Table 17: AC Characteristics
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
15 / 82
QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
4.5 LIN Transceiver; pins LIN1 to LIN4, TXDLIN1 to TXDLIN4, RXDLIN1 to RXDLIN4, GNDLIN
4.5.1 Characteristics
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
VLIN,VS
7
-
18
V
1
functional range LIN transceiver
2
recessive output voltage
TXDLINx = 1
VLIN,REC
VVS -1V
-
VVS
-
3
dominant output voltage
TXD = 0, VVS =
7.0V, RLIN = 0.5kΩ
to VVS
VLIN,DOM
-
-
1.2
V
4
dominant output voltage
TXDLINx = 0, VVS =
18V, RLIN = 0.5kΩ to
VVS
VLIN,DOM1
-
-
2.0
V
5
receiver dominant level
VLIN,THDOM
-
-
0.4
VS
6
receiver recessive level
VLIN,THREC
0.6
-
-
VS
7
LIN bus center voltage
VLINx,BUSCNT =
(VLINx,THDOM +
VLINx,THREC) / 2
VLIN,BUSCNT
0.475
-
0.525
VS
8
receiver hysteresis
VLINx,THREC - VLIN,THDOM
VLIN,HYS
0.02
-
0.175
VS
9
output current limitation
VLINx = VVS,MAX = 18V
ILIN,LIM
40
-
200
mA
10
pull up resistance
RLIN,SLAVE
20
33
60
kΩ
11
leakage current flowing into pin
LIN
transmitter passive,
7V < VVS < 18V, 7V
< VLINx < 18V, VLINx
> VVS
ILIN,BUSREC
-
-
20
μA
12
pull up current flowing out of pin
LIN
transmitter passive,
7V < VVS < 18V,
VLINx = 0V
ILIN,BUSDOM
-1
-
-
mA
13
leakage current, ground disconnected (GND device = VS)
VVS = 13.5V,
0V < VLINx < 18V
ILIN,NOGND
-1
-
0.1
mA
14
leakage current, supply disconnec- VVS = 0V,
ted
0V < VLINx < 18V
ILIN
-
-
20
μA
15
leakage current, supply disconnec- VVS = 0V,
ted, TJ = 85°C,
0V < VLINx < 18V
ILIN,85
-
-
15
μA
VLIN,CLAMP
40
-
V
not production tested
16
clamping voltage, not production
tested
VVS = 0V, ILINx =
1mA
Table 18: DC Characteristics
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
16 / 82
QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
CLIN,PIN
-
-
30
pF
tRXD,PDR ,tRXD,PDF
-
-
6
μs
tRXD,PDR,FLASH ,
tRXD,PDF,FLASH
-
-
2.5
µs
-
2
μs
150
µs
1
input capacitance, not production
tested!
7V < VVS < 18V
2a
receive propagation delay
2b
receive propagation delay in
FLASH mode1)
3
receive propagation delay symmetry
tRXD,SYM
-2
4
wake up debounce time
tLIN,WU
70
5
Duty cycle 1 1)
VLIN,THREC(max) =
0.744*VVS,
VLIN,THDOM(max) =
0.581*VVS, VVS = 718V, tBIT = 50us,
DLIN,1 = tBUSREC(min)/
(2*tBIT)
DLIN,1
0.396
-
-
-
6
Duty cycle 2 1)
VLIN,THREC(min) =
0.422*VVS,
VLIN,THDOM(min) =
0.284*VVS, VVS = 718V, tBIT = 50us,
DLIN,2 = tBUSREC(max)/(2*tBIT)
DLIN,2
-
-
0.581
-
7
Duty cycle 3 1)
V,LIN,THREC(max) =
0.778*VVS,
VLIN,THDOM(max) =
0.616*VVS, VVS = 718V, tBIT = 96us,
DLIN,3 = tBUSREC(min)/
(2*tBIT)
DLIN,3
0.417
-
-
-
8
Duty cycle 4 1)
VLIN,THREC(min) =
0.389*VVS,
VLIN,THDOM(min) =
0.251*VVS, VVS = 718V, tBIT = 96us,
DLIN,4 = tBUSREC(max)/(2*tBIT)
DLIN,4
-
-
0.590
-
9
receive data baud rate 2)
flash mode,
VVS = 13V
BLIN,RXD
250
kBd/s
10
transmit data baud rate 2)
flash mode,CLIN =
200PF, RLIN =
0.5kΩ
VVS = 13V
BLIN,TXD
125
kBd/s
Table 19: AC Characteristics
1) Bus load conditions (CLIN,RLIN): 1nF, 1kΩ or 6.8nF, 660Ω or 10nF, 500Ω
2) Not production tested
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
17 / 82
QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
4.5.2 LIN TXD/RXD
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
1
output low level range
IRXD,LINx = 1mA
VRXD,LINx,OUTL
-
-
0.4
V
2
output high level range
IRXD,LINx = -1mA
VRXD,LINx,OUTH
VVDD10.4
-
-
V
3
input low voltage range
VTXD,LINx,INL
-
-
0.3
VDD1
4
input high voltage range
VTXD,LINx,INH
0.7
-
-
VDD1
5
Internal TXD pull up resistor
RTXD,LINx,PU
80
110
150
kΩ
Symbol
Min
Typ
Max
Unit
VTXD,LINx = 0V
Table 20: DC Characteristics
4.5.3 LIN Failure detection and recovery
No.
Description
Condition
1
time out for txd dominant clamping
failure
tLIN,TXD,DOM
8.5
12.5
ms
2
time out for LIN dominant clamping failure
tLIN,BUS,DOM
8.5
12.5
ms
Table 21: AC Characteristics
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
18 / 82
QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
HS-CAN Transceiver; pins CANH, CANL, RXDCAN, TXDCAN, VDDCAN
(VVS = 5.5V to 28V, TAMB = -40°C to +125°C, VCAN=-12V to +12V unless otherwise noted. Typical values are at VVS = 12.0V and TAMB = +25°C.
Positive currents flow into the device pins.)
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
1
CANH dominant output voltage
VTXDCAN = 0V
RL = 50Ω to 65Ω
VDOM_OUT_H
3.0
4.5
V
2
CANL dominant output voltage
VTXDCAN = 0V
RL = 50Ω to 65Ω
VDOM_OUT_L
0.5
2.0
V
3
Matching of dominant output
VTXDCAN = 0V
voltages (VVDDCAN - (VCANH + VCANL)) RL = 50Ω to 65Ω
VDOM_OUT_MATCH
-400
400
mV
4
Differential bus dominant output
voltages (VCANH-VCANL)
VTXDCAN = 0V
RL = 50Ω to 65Ω
VDIFF_OUT_DOM
1.5
3.0
V
5
Recessive output voltage on
CANH and CANL
VTXDCAN = VVDD1
CAN NORMAL and
LISTEN mode
VREC_OUT
2.0
VVDDCAN/
2
3.0
V
6
Differential receiver threshold
voltage
CAN NORMAL and
LISTEN mode
VDIFF_TH
500
700
900
mV
7
Differential receiver threshold
voltage, CAN off and wake up
detection capability enabled
CAN off, wakeable
VDIFF_TH_OFF
400
1150
mV
8
Differential receiver hysteresis
voltage
CAN NORMAL and
LISTEN mode
VDIFF_HYST
9
Differential bus recessive output
voltages (VCANH - VCANL)
CAN recessive,
no load
9a
Recessive output voltage at CANH CAN recessive,
and CANL, low power mode
no load
10
Short circuit output current on
CANL
11
60
mV
VREC_OUT_OFF
-100
50
mV
VREC,LP
-100
100
mV
VTXDCAN = 0V
VCANL = 40V
ISC_OUT_CANL
40
100
mA
Short circuit output current on
CANH
VTXDCAN = 0V
VCANH = -5V
ISC_OUT_CANH
-100
-40
mA
12
Recessive bus current
VTXDCAN = VVDD1
-27V < VCANH/L <
32V
IREC_OUT
-5
5
mA
13
Input leakage current on CANL
and CANH
VDD connected to
GND with R = 0Ω
and R = 47kΩ
VCANH = VCANL = 5V
ILEAK_IN
-10
10
μA
14
Common mode input resistance
RI_COM
15
35
kΩ
15
Differential input resistance
RI_DIF
30
70
kΩ
15a Common mode input capacitance VTXDCAN = VDD1
not production tested
CI_COM
20
pF
15b Differential input capacitance
not production tested
CI_DIF
10
pF
VTXDCAN = VDD1
15c Internal Rin resistor matching of
CANH and CANL
Rin_matching
-3
3
%
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
19 / 82
QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
No.
Description
Condition
Symbol
Min
VDIFF_OUT_REC_LOAD
16
Differential bus recessive output
voltages (VCANH - VCANL)
VTXDCAN = VDD1
17
VDDCAN monitor threshold
HS-CAN enabled
VVDDCAN,UV
18
VDDCAN monitor threshold hysteresis
HS-CAN enabled
VVDDCAN,UV,HYST
19
CANH / CANL common mode
voltage range
Typ
Max
Unit
-5
5
mV
4.2
4.6
V
100
VCAN
-12
Symbol
Min
DRCAN
mV
12
V
Max
Unit
40
1000
kBit/s
Table 22: DC Characteristics
No.
Description
Condition
Typ
1
Data rate range to be transmitted
and received
CAN NORMAL or
LISTEN mode
2
Delay TXDCAN to bus dominant
CAN NORMAL
mode
tCAN,D_TXD_BUS(dom)
25
110
ns
CAN NORMAL
mode
tCAN,D_TXD_BUS(rec)
10
95
ns
CAN NORMAL or
LISTEN mode
tCAN,D_BUS_RXD(dom)
15
115
ns
CAN NORMAL or
LISTEN mode
tCAN,D_BUS_RXD(rec)
35
160
ns
tCAN,PD_TXD_RXD
40
255
ns
tCAN,WAKE_BUS_DOM
0.75
5
μs
tCAN,WAKE_BUS_REC
0.75
5
μs
0.5
2
ms
50
µs
not production tested
3
Delay TXDCAN to bus recessive
not production tested
4
Delay bus to RXDCAN dominant
not production tested
5
Delay bus to RXDCAN recessive
not production tested
6
Propagation delay TXDCAN to
RXDCAN
CAN NORMAL
mode
7
Dominant time for wake up via bus CAN off,
wake up capability
enabled,
VS = 12V
8
Recessive time for wake up via
bus
CAN off,
wake up capability
enabled,
VS = 12V
9
wake up time out
CAN_CFG.RC = 0,
CAN_CFG.WU = 1
tCAN,WAKE2
10
CAN activation time
CAN_CFG.RC = 1
tCAN,ACTIVE
Table 23: AC Characteristics
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
20 / 82
QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
4.5.4 TXDCAN and RXDCAN
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
1
output low level range
IRXDCAN = 1mA
VRXD,CAN,OUTL
-
-
0.4
V
2
output high level range
IRXDCAN = -1mA
VRXD,CAN,OUTH
VVDD10.4
-
-
V
3
input low voltage range
VTXD,CAN,INL
-
-
0.3
VDD1
4
input high voltage range
VTXD,CAN,INH
0.7
-
-
VDD1
5
Internal TXDCAN pull up resistor
RTXD,CAN,PU
80
110
150
kΩ
Symbol
Min
Typ
Max
Unit
VTXDCAN = 0V
Table 24: DC Characteristics
4.5.5 CAN Failure detection and recovery
No.
Description
Condition
1
time out for TXD dominant clamping failure
tCAN,TXD,DOM
1.4
1.9
ms
2
time out for BUS dominant clamping failure
tCAN,BUS,DOM
1.4
1.9
ms
3
duration of bus dominant or
recessive time for CAN bus failure
detection
tBUS,FAIL
6
µs
Table 25: AC Characteristics
4.6 Limp Home support; pin FSON
No.
1
Description
output low level
Condition
Symbol
IFSON = 1mA
Min
Typ
VFSON,OUTL
Max
Unit
0.4
V
Max
Unit
0.4
V
VVS > VVS,PD
Table 26: DC characteristics
4.7 Interrupt; pin INTN
No.
1
Description
output low level
Condition
Symbol
IINTN = 1mA
Min
Typ
VINTN,OUTL
VVDD1 > 3V
2
pull up resistor
VINTN = 0V
RINTN,PU
80
105
150
kΩ
Symbol
Min
Typ
Max
Unit
Table 27: DC Characteristics
No.
1
Description
Calculation time for interrupt
related state change condition
detected
Condition
Interrupt state
change condition
detected
tINTN,SETUP
8
tOSC
Table 28: AC Characteristics
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
21 / 82
QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
4.8 DCDC Buck converter; pins VIN, VDD1, VDD1SENSE, LXT, PGND
No.
1)
Description
Condition
Symbol
Min
IVDD1 = -500mA,
CVDD1 > 22μF, ESR
< 120mΩ, VVIN >
5.5V
VVDD1,5V
4.9
Typ
1
VDD1 output voltage if enabled,
E521.02..04, E521.12..14
2
Quiescent current consumption of VVIN = 13.5V
DCDC buck converter in case of
DCDC off
switched off, e.g. in SBC mode
SLEEP
IVIN,DCDC_OFF
9
3
Quiescent current consumption of VVIN = 13.5V
DCDC buck converter in case of
DCDC on
switched on, e.g. in SBC mode
NORMAL
Duty cycle = 0%
IVIN,DCDC_ON
160
4
reset threshold 1 for VDD1
E521.02..04, E521.12..14 1)
5
VDD1_CFG.THR_
1:THR_0 = 0h,
VDD1 falling
VTH1,VDD1,RSTN
Max
Unit
5.1
V
20
μA
μA
4.4
4.6
V
reset release threshold 1 for VDD1 VDD1_CFG.THR_ VTH1,VDD1_r,RSTN
E521.02..04, E521.12..14 1)
1:THR_0 = 0h,
VDD1 rising
4.6
4.9
V
6
reset threshold 2 for VDD1
E521.02..04, E521.12..14 1)
VDD1_CFG.THR_
1:THR_0 = 1h,
VDD1 falling
VTH2,VDD1,RSTN
3.8
4
V
7
reset release threshold 2 for VDD1 VDD1_CFG.THR_
E521.02..04, E521.12..14 1)
1:THR_0 = 1h,
VDD1 rising
VTH2,VDD1_r,RSTN
4.0
4.25
V
8
reset threshold 3 for VDD1
E521.02..04, E521.12..14 1)
VDD1_CFG.THR_
1:THR_0 = 2h,
VDD1 falling
VTH3,VDD1,RSTN
3.4
3.6
V
9
reset release threshold 3 for VDD1 VDD1_CFG.THR_
E521.02..04, E521.12..14 1)
1:THR_0 = 2h,
VDD1 rising
VTH3,VDD1_r,RSTN
3.6
3.85
V
10
reset threshold 4 for VDD1
E521.02..04, E521.12..14 1)
VDD1_CFG.THR_
1:THR_0 = 3h,
VDD1 falling,
default selection
VTH4,VDD1,RSTN
3
3.2
V
11
reset release threshold 4 for VDD1 VDD1_CFG.THR_
E521.02..04, E521.12..14 1)
1:THR_0 = 3h,
VDD1 rising
VTH4,VDD1_r,RSTN
3.2
3.45
V
12
LXT internal over current protection limit
ILXT
650
1100
mA
VVIN > 5.5V
800
Hysteresis of reset thresholds is designed to > 150mV in 5V system
Table 29: DC Characteristics
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
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Data Sheet
22 / 82
QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
No.
Description
Condition
Symbol
Min
4.5
Typ
Max
Unit
6.5
ms
1
reset delay time after release of
VDD1 reset
tRSTN,VDD1
2
VDD1 under voltage debounce
time
tDEB,VDD1
10
50
μs
3
reset reaction time in case of
under voltage condition
tRR,VDD1,RSTN
14
20
μs
Typ
Max
Unit
Table 30: AC Characteristics
4.8.1 Pulse Frequency Modulated (PFM) Converter
PFM Control Logic
No.
Description
Condition
Symbol
Min
1
Switch Minimum ON Time
No over current
detected
TON,MIN
260
ns
2
Minimum ON Time
Over current detected
TON,OC
100
ns
3
Minimum OFF time without over
current
TOFF,MIN,NOM
520
ns
4
Nominal minimum OFF time after
over current detection
TOFF,OC,NOM
1330
ns
5
Extended minimum OFF time after
over currrent detection
TOFF,OC,EXT
2450
ns
6
Operation frequency
7
Peak Operation Frequency
depending on ratio
VVIN/VDD1 and load
conditions
FOP
0
FOP,MAX
0.9
1.3
1.7
MHz
1.7
MHz
Table 31: AC characteristics
ELMOS Semiconductor AG reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.
Elmos Semiconductor AG
Data Sheet
23 / 82
QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Low drop regulator; pins VDD2, ENVDD2
No.
Description
Condition
Symbol
Min
Typ
Max
Unit
5.0
5.1
V
-110
mA
RDSVDD2,VS=5.5V
12
Ω
RDSVDD2,VS=5.0V
13
Ω
RDSVDD2,VS=4.5V
15
Ω
RDSVDD2,VS=4.0V
17
Ω
RDSVDD2,VS=3.5V
21
Ω
4.8
V
1
Parameter removed
2
output voltage range
VDD2 enabled,
6V < VVS < 28V,
IVDD2 > -100mA
VVDD2,100mA
4.9
3
output current limitation
VVDD2 = 0V, VVS =
28V
IVDD2,LIM
-220
4
information only, RDS of regulator VDD2 enabled,
for VVS = 5.5V
Determined for
VVS = 5.5V
Not production
tested
5
information only, RDS of regulator VDD2 enabled,
for VVS = 5.0V
Determined for
VVS = 5.0V
Not production
tested
6
information only, RDS of regulator VDD2 enabled,
Determined for
for VVS = 4.5V
VVS = 4.5V
Not production
tested
7
information only, RDS of regulator VDD2 enabled,
for VVS = 4.0V
Determined for
VVS = 4.0V
Not production
tested
8
information only, RDS of regulator VDD2 enabled,
Determined for
for VVS = 3.5V
VVS = 3.5V
Not production
tested
9
under voltage threshold falling
VDD2 enabled
VUV,THR
4.5
10
under voltage hysteresis
VDD2 enabled
VUV,HYS
11
threshold of ENVDD2 rising
VENVDD2 rising
VENVDD2,LH
0.6
0.8
VS
12
threshold of ENVDD2 falling
VENVDD2 falling
VENVDD2,HL
0.5
0.7
VS
100
mV
Table 32: DC Characteristics
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Data Sheet
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
No.
1
Description
Condition
Symbol
Min
Max
Unit
tDEB,UV
150
280
μs
Symbol
Min
Typ
Max
Unit
VBOOST
6.0
6.5
7.0
V
VISEN
85
100
110
mV
IISEN
-1
1
µA
VBooster_input_min
3.25
V
VBooster_input_min_2
2.5
V
under voltage debounce time
Typ
Table 33: AC Characteristics
4.9 DCDC Boost converter; pins MDRV, ISEN, PGND2
No.
Description
Condition
1
VS activation and output voltage
E521.12, .13, .14 only
VVDD1 > tbd.
2
Current sense threshold
E521.12, .13, .14 only
3
Current sense input current
E521.12, .13, .14 only
4
Minimum Booster input voltage to Iload_VS < 600mA
guarantee defined booster output
voltage
E521.12, .13, .14 only
5
Minimum Booster input voltage to Iload_VS < tbd.
guarantee defined booster output
voltage, current limited to lower
value of than defined for VBAT_min
E521.12, .13, .14 only
6
Internal parasitic Resistance of the
Booster-inductance
E521.12, .13, .14 only
7
Pullup current at ISENSE-Pin dur- Booster enabled
ing booster is on
E521.12, .13, .14 only
Booster disabled
30
mΩ
2
5
μA
Typ
Max
Unit
RDC_LBOOST
RISENSE
Table 34: DC Characteristics
No.
Description
Condition
Symbol
Min
1
Minimum switch off-time
TOFFMIN4
0.47
µs
2
Maximum switch on-time
TONMAX4
8.4
µs
3
Minimum switch on-time
TONMIN4
150
ns
Table 35: AC Characteristics
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
5 Functional Description
5.1 Power Supply and References; pins VS, GND
Fig. 1: Operating Range Limitations
5.1.1 Internal Time Base
Most times specified are derived from internal 1μs time base e.g. directly or by using prescalers based on this time
base.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
5.2 SBC Operating Modes
The device provides the following states:
•
OFF
•
INIT
•
NORMAL
•
STOP
•
SLEEP
•
RESTART
•
FAILSAFE
Transition between states is performed at the latest tSTATE_CHANGE after valid condition detected.
Fig. 2: SBC State Diagram
*) Watchdog and cyclic wake up use one timer. It is possible to use one at the same time only. A change between
cyclic wake up and watchdog does not reset timer.
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register Name
Address
Description
SBC_CFG
0x01
SBC configuration register.
WU_SRC
0x04
Wake up source register. Wake up source is cleared if register is read via SPI.
SPI_FAIL
0x05
SPI programming failure register. Register is cleared by reading via SPI.
VDD_STAT
0x1A
VDD1, VDD2 and VDDCAN status information.
Table 36: RegisterTable
Register SBC_CFG (0x01)
MSB
LSB
Content
CLAMP
-
BOOST
FSON
CFG
STATE2
STATE1
STATE0
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R/W
R
R/W
R/W
R/W
R/W
Bit Description
CLAMP :
1.. External reset shorter than tWDRSTN,TO,GND will not lead to FSON set
0.. External reset leads to FSON set immediately
Info: Bit can be written in register FSON_CFGx.
BOOST :
1.. Enable booster for low voltage at pin VS
0.. Do not enable booster for low voltage at pin VS
FSON :
1.. FSON is active
0.. FSON is not active
CFG : SBC state transition in case of watchdog failure
0.. FAILSAFE
1.. RESTART
STATE2 ... STATE0
000.. OFF
001.. INIT (cannot be set by SPI)
010.. NORMAL
011.. STOP
100.. RESTART
101.. FAILSAFE
110.. SLEEP
111.. reserved
Table 37: SBC configuration register.
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register WU_SRC (0x04)
MSB
LSB
Content
LIN4
LIN3
LIN2
LIN1
CAN
VDD1
WD
WK
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit Description
LIN4 : 1... wake up from LIN4 detected
LIN3 : 1... wake up from LIN3 detected
LIN2 : 1... wake up from LIN2 detected
LIN1 : 1... wake up from LIN1 detected
CAN : 1... wake up from CAN detected
VDD1 : 1... wake up in STOP mode due to VDD1 current limitation exceeded
WD : 1... cyclic wake up in STOP mode
WK : 1... wake up from local wake up pin WK detected
Table 38: Wake up source register. Wake up source is cleared if register is read.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register SPI_FAIL (0x05)
MSB
LSB
Content
LIN4
LIN3
LIN2
LIN1
CAN
-
WD
FSM
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit Description
Register is cleared by reading via SPI
LIN4 :
1.. LIN4 is reason for interrupt, e.g. configuration of LIN4 in case of not beeing in SBC state
NORMAL
0.. LIN4 is not reason for interrupt
LIN3 :
1.. LIN3 is reason for interrupt, e.g. configuration of LIN3 in case of not beeing in SBC state
NORMAL
0.. LIN3 is not reason for interrupt
LIN2 :
1.. LIN2 is reason for interrupt, e.g. configuration of LIN2 in case of not beeing in SBC state
NORMAL
0.. LIN2 is not reason for interrupt
LIN1 :
1.. LIN1 is reason for interrupt, e.g. configuration of LIN1 in case of not beeing in SBC state
NORMAL
0.. LIN1 is not reason for interrupt
CAN :
1.. CAN is reason for interrupt, e.g. configuration of CAN in case of not beeing in SBC state
NORMAL
0.. CAN is not reason for interrupt
WD :
1.. Watchdog is reason for interrupt, e.g. configuration of WD in case of not beeing in SBC state
NORMAL
0.. Watchdog is not reason for interrupt
FSM :
1.. State machine is reason for interrupt, e.g. trying to change into SBC state SLEEP with
pending wake up
0.. State machine is not reason for interrupt
Table 39: SPI programming failure register.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register VDD_STAT (0x1A)
MSB
LSB
Content
VDD2 ON VDD2_EN VDD2OC
PIN
VDD2 UV
-
VDDCAN
UV
VDD1 UV
-
Reset value
0
0
0
0
0
0
Access
R
R
R
R
VDD2 ON :
1.. Linear voltage regulator VDD2 enabled
0.. Linear voltage regulator VDD2 disabled
R
R
R
R
Bit Description
0
0
VDD2_EN PIN :
1.. ENVDD2 set to logic level 1
0.. ENVDD2 set to logic level 0
VDD2OC :
1.. VDD2 over current detected
0.. VDD2 over current not detected
VDD2 UV :
1.. VDD2 under voltage detected
0.. VDD2 under voltage not detected
VDDCAN UV :
1.. VDDCAN under voltage detected
0.. VDDCAN under voltage not detected
VDD1 UV :
1.. VDD1 under voltage detected
0.. VDD1 under voltage not detected
Table 40: VDD1, VDD2 and VDDCAN status information.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
5.2.1 OFF state
The OFF mode is the unsupplied state. This mode is left automatically if VVS > VS,PU.
It is entered automatically if VVS < VS,PD.
5.2.2 INIT state
The SBC is set to state INIT after VVS,PU is exceeded. The DCDC buck converter VDD1 is switched on. The default
reset threshold VTH4,VDD1,RSTN is active. Pin RSTN is set to L. After reaching reset threshold reset delay time tRSTN,VDD1
is applied. Then pin RSTN is set to H.
In case of VDD1 does not start up beyond its reset level state transition to state FAILSAFE is performed after
tTO,VDD1. This function helps to prevent higher or even short currents to VDD1 for longer times.
Transition from SBC state INIT to SBC state NORMAL must be initiated by SPI within tTO,INIT. tTO,INIT starts with rising
edge of RSTN.
The reset output pin RSTN is bidirectional and can be overwritten by the external µC. In case of an internal reset
extended by an external reset the timeout tWDRSTN,TO,GND becomes active at the end of the internal reset duration. If
the timeout is exceeded SBC changes to state FAILSAFE and FSON is set.
5.2.3 NORMAL state
State NORMAL is expected to be the main state. All configuration registers are accessable and watchdog is running.
Watchdog, CAN, VDD2, WK, FSON and LINs can be configured.
Low power state STOP and very low power state SLEEP can be entered via SPI.
If a watchdog trigger failure occurs or RSTN is overwritten externally or VDD1 drops below the configurable reset
threshold state is changed to FAILSAFE or RESTART depending on configuration of bit SBC_CFG.CFG.
5.2.4 STOP state
LIN and CAN transceivers are off but can be wakeable.
Watchdog cyclic wake up timer can be active. Configuration must be performed in state NORMAL in registers
WD_CFG1 and WD_CFG2 prior entering state STOP as described for watchdog configuration change. Occurence
of cyclic wake up generates an interrupt.
VDD2 regulator can be active depending on pin ENVDD2 or bit VDD2_CFG.ON.
If RSTN is overwritten externally the state changed to FAILSAFE or RESTART mode depending on configuration of
bit SBC_CFG.CFG. Hence the regulator is enabled every t1n an external reset is detectable only after that time only.
5.2.5 VDD1 current observation in SBC state STOP
A low current consumption is expected in SBC state STOP. To save current DCDC is switched off after an initial
time tTRAN,STOP. DCDC is enabled periodically for regular recharge phase tON_REG,STOP every reload time t1n.
Reload time can be configured in register VDD1_CFG. The undervoltage detection remains active.
In case of current consumption is too high voltage drops below undervoltage threshold k1VDD1 and regulator is
enabled for tTRAN,STOP. If this happens more than once within t1n state is changed to SBC state NORMAL and an
interrupt is generated. Otherwise SBC remains in state STOP.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
System behaviour concerning VVDD1 strongly depends on value of external capacitor. It is recommended to calculate
value of external capacitor with knowledge of overall system STOP state current consumption and adding a safety
margin in order to ensure SBC state STOP can be reached and kept.
Accessing register VDD1_CFG is not allowed in SBC state FAILSAFE.
Fig. 3: Transition to and from SBC state STOP with current observation on VDD1
5.2.6 SLEEP state
LIN and CAN transceivers are off but can be wakeable. VDD1 voltage regulator is off and reset signal at RSTN is
generated.
VDD2 regulator can be active depending on pin ENVDD2 or bit VDD2_CFG.ON.
A transition to state SLEEP with all wake up sources disabled is prohibited. The transistion is ignored, SPI failure bit
is set and an interrupt is generated.
Wake up event causes a transition to state RESTART.
Watchdog can be configured to wake up device in state SLEEP.
5.2.7 RESTART state
State RESTART is an intermediate state being reached in case of failure conditions or wake up from states SLEEP
or FAILSAFE.
State can be left to NORMAL using SPI command within limited amount of time tTO,INIT. Otherwise state FAILSAFE is
entered automatically.
5.2.8 FAILSAFE state
State FAILSAFE is entered in case of failure condition present only. Pin FSON is activated automatically. VDD1 regulator is switched off. Pin RSTN is set to low.
VDD2 regulator can be active depending on pin ENVDD2.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
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PRODUCTION DATA – Mar 7, 2016
With entering state FAILSAFE all wake up capabilities are enabled. In case of a wake up condition state RESTART
is entered.
In case of an overtemperature failure state RESTART is entered when overtemperature condition vanishes.
5.2.9 Configuration for transition behaviour to modes FAILSAFE or RESTART
Transition behaviour in case of failure either to SBC state FAILSAFE or to SBC state RESTART can be setup using
external circuitry connected to pin INTN.
Setup of behaviour is performed in state INIT at the end of SBC active RSTN time tRSTN,VDD1. At this particular point
voltage at INTN is sensed back. Desired behaviour is stored in register SBC_CFG.CFG.
For setup purposes during time of determination neither internal normal pull up resistor nor internal low side driver
are active in INTN stage. Instead of an internal pull down resistor is active. There are two possible cases:
1. External pull up present: Detect logic level high
2. No external pull up present: Detect logic level low
Diagram Fig. 4 shows principal implementation of INTN stage. T1N and T1P are used for normal operation. For
setup phase both T1N and T1P are switched off and pull down controlled by T2N is enabled.
Recommendation for selection of external pull up resistance towards VDD1
System with VVDD1=5V: Select value of ≦ 85kΩ , e.g. 68kΩ
Fig. 4: INTN internal structure with support for setup SBC_CFG.CFG
Implementation of INTN stage for normal operation and setup of SBC_CFG.CFG.
An alternative way to change RESTART/FAILSAFE behaviour in case of a failure is setting bit SBC_CFG.CFG via
SPI. But there are some limitations:
1. Bit SBC_CFG.CFG can not be set to L via SPI if an external pull up exists at pin INTN.
2. Bit SBC_CFG.CFG can be written in states STOP and NORMAL only.
3. Bit SBC_CFG.CFG is cleared in states RESTART and FAILSAFE.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
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PRODUCTION DATA – Mar 7, 2016
5.2.10 Software Development function; pin SWDM
High active pin SWDM determines activation of software development function. The only way to enable software
development function is a high level of pin SWDM with internal release of pin RSTN in SBC states INIT or
RESTART.
In final application pin SWDM must be connected to electrical ground.
With software development function enabled following changes apply to system behaviour:
1. no watchdog related reset at pin RSTN is generated
2. automatic watchdog related transitions to states FAILSAFE or RESTART are not performed
3. external events at RSTN are ignored
4. exceeding of timeout tTO,INIT is ignored
All failures are signaled as usual in SPI status register. All other functional blocks behave as described.
Setting pin SWDM to low logic level disables software development function.
5.2.11 Over temperature behaviour
IC implements 8 independent temperature sensors:
1. LIN1
2. LIN2
3. LIN3
4. LIN4
5. HS-CAN
6. VDD2 voltage regulator
7. VDD1 DCDC buck converter
8. Internal aux. structures
In case of over temperature detected in LIN or CAN transceivers corresponding interface is switched off and an
interrupt is set.
VDD2 voltage regulator features both warning and over temperature shutdown functionality including interrupt generation.
VDD1 over temperature detection results in an external reset at RSTN.
In case of internal auxiliary structures report an over temperature situation system changes to SBC state
FAILSAFE. If overtemperature vanishes device will enter SBC state RESTART.
Register Name
OT_STAT
Address
0x1F
Description
Over temperature detection status register.
Table 41: RegisterTable
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CAN/LIN SBC Family with DC/DC Voltage Regulator
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PRODUCTION DATA – Mar 7, 2016
Register OT_STAT (0x1F)
MSB
LSB
Content
LIN4
LIN3
LIN2
LIN1
CAN
VDD2
VDD1
AUX
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit Description
LIN4 :
1.. LIN4 over temperature detected
0.. LIN4 over temperature not detected
LIN3 :
1.. LIN3 over temperature detected
0.. LIN3 over temperature not detected
LIN2 :
1.. LIN2 over temperature detected
0.. LIN2 over temperature not detected
LIN1 :
1.. LIN1 over temperature detected
0.. LIN1 over temperature not detected
CAN :
1.. CAN over temperature detected
0.. CAN over temperature not detected
VDD2 :
1.. VDD2 over temperature detected
0.. VDD2 over temperature not detected
VDD1 :
1.. VDD1 over temperature detected
0.. VDD1 over temperature not detected
AUX :
1.. Over temperature in other internal aux. structures detected
0.. Over temperature in other internal aux. structures not detected
Table 42: Over temperature detection status register.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
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PRODUCTION DATA – Mar 7, 2016
5.3 SPI communication; pins SCK, SDI, SDO, CSN
The SPI interface is used for:
•
storing-/and reading CAN data-/timing and system configurations
•
reading diagnosis register
By setting CSN to low level, the communication can be achieved and by setting to high level leads to disabling the
communication (in this case, pin SDO is high impedance). During the transmission data shifts are controlled by the
serial clock signal (SCK) according to the following rules:
•
data is shifted MSB first, LSB last
•
data is shifted out on the rising edge of SCK and is sampled on the falling edge of SCK
•
data transmission length is always 16 Bit
SPI write is performed setting MSB Bit A7 of address value to 1. During read Bit A7 needs to be 0.
Fig. 5: SPI access
Bit RW
•
1: write access
•
0: read access
Fig. 6: SPI Timing diagram
SPI timing diagram. For configuration of write and read access check corresponding diagrams.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
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5.4 Watchdog; pin RSTN
Design implements watchdog functionality that can be used in window or timeout mode. Watchdog mode depends
on system state.
5.4.1 Time out mode
The time out mode is an easier and less secure type of the watchdog modes. A closed window does not exist. The
watchdog trigger can be applied at any time within the watchdog cycle. A watchdog trigger is detected as a write
access to the register WD_TRIG. The bit TRIG_BIT must toggle. A correct watchdog trigger starts a new window
period.
The period can be configured in registers WD_CFG1 and WD_CFG2 in the range from 4ms up to 1024ms using
formula 4ms*(1+PER[7:0]).
In case of an incorrect watchdog trigger the SBC will enter states RESTART or FAILSAFE depending on configuration in SBC_CFG. A watchdog failure generates a reset setting the pin RSTN to L for tWD,RSTN.
The first period always starts with 256ms. The first TRIG_BIT must be H.
Fig. 7: watchdog time out mode
Fig. 8: watchdog time out mode without trigger
5.4.2 Window mode
The window mode is the secure type of the watchdog modes. It consists of a closed and an open window. A closed
window is 50% of the configured watchdog period.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
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A triggering of the watchdog is only allowed in the open window. A watchdog trigger is detected as a write access to
register WD_TRIG. The bit TRIG_BIT must toggle. A correct watchdog trigger starts a new window period.
The period can be configured in registers WD_CFG1 and WD_CFG2 in the range from 4ms up to 1024ms using
formula 4ms*(1+PER[7:0]).
In case of an incorrect watchdog trigger the SBC will enter SBC state RESTART or FAILSAFE depending on configuration in register SBC_CFG. A watchdog generates a reset setting the pin RSTN to low for tWD,RSTN .
The first period always starts with 256ms. The first TRIG_BIT must be high.
Fig. 9: watchdog window mode
Fig. 10: watchdog window mode no trigger in FOW
Behaviour of watchdog in case of missing trigger in open window.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
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PRODUCTION DATA – Mar 7, 2016
Fig. 11: watchdog window mode trigger in closed window
Behaviour of watchdog in case of trigger in closed window.
Fig. 12: watchdog window mode no trigger in open window
Behaviour of watchdog in case of missing trigger in open window.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
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Fig. 13: safe trigger area
5.4.3 Configuration
The configuration of watchdog is allowed in SBC state NORMAL only. Registers WD_CFG1 and WD_CFG2 must
be written within one watchdog cycle. The corresponding bits of WD_CFG1 and WD_CFG2 as well as WD_PER1
and WD_PER2 must be equal. Only in this case the configuration is valid. The configuration currently used can be
read in registers WD_CFG and WD_PER.
Register Name
Address
Description
WD_CFG
0x08
Current watchdog configuration. Change of configuration has to be performed
using WD_CFG1 and WD_CFG2 including correct watchdog trigger afterwards
within one watchdog cycle in SBC state NORMAL
WD_CFG1
0x09
Watchdog configuration register 1
WD_CFG2
0x0A
Watchdog configuration register 2
WD_STAT
0x0B
Watchdog status register
WD_PER
0x0C
Current watchdog period. Change of period has to be performed using
WD_PER1 and WD_PER2 including correct watchdog trigger afterwards within
one watchdog cycle.
WD_TRIG
0x0D
Watchdog trigger register
WD_PER1
0x0E
Watchdog period register 1
WD_PER2
0x0F
Watchdog period register 2
Table 43: Watchdog RegisterTable
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register WD_CFG (0x08)
MSB
LSB
Content
TBASE
WD
CWK1
CWK0
MODE
-
-
-
Reset value
0
0
0
0
1
0
0
0
Access
R
R
R
R
R
R
R
R
Bit Description
TBASE : In SBC state NORMAL:
1.. Output time base at RXDLIN1 on
0.. Output time base at RXDLIN1 off
WD : In SBC state STOP, overwrites CWK1:
1.. Watchdog on
0.. Watchdog off
CWK1 : In SBC states STOP:
1.. Cyclic wake up on
0.. Cyclic wake up off
CWK0 : In SBC state SLEEP:
1.. Cyclic wake up on
0.. Cyclic wake up off
MODE :
1.. Time out mode
0.. Window mode
Table 44: Current watchdog configuration. Change of configuration has to be performed using WD_CFG1 and
WD_CFG2 including correct watchdog trigger afterwards within one watchdog cycle in SBC mode NORMAL
Register WD_CFG1 (0x09)
MSB
LSB
Content
TBASE
WD
CWK1
CWK0
MODE
-
-
-
Reset value
0
0
0
0
1
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R
R
R
Bit Description
TBASE : In SBC state NORMAL:
1.. Output time base at RXDLIN1 on
0.. Output time base at RXDLIN1 off
WD : In SBC state STOP, overwrites CWK1:
1.. Watchdog on,
0.. Watchdog off
CWK1 : In SBC states STOP:
1.. Cyclic wake up on
0.. Cyclic wake up off
CWK0 : In SBC state SLEEP:
1.. Cyclic wake up on
0.. Cyclic wake up off
MODE :
1.. Time out mode
0.. Window mode
Table 45: Watchdog configuration register 1
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register WD_CFG2 (0x0A)
MSB
LSB
Content
-
-
-
MODE
CWK0
CWK1
WD
TBASE
Reset value
0
0
0
1
0
0
0
0
Access
R
R
R
R/W
R/W
R/W
R/W
R/W
Bit Description
MODE :
1.. Time out mode
0.. Window mode
CWK0 : In SBC state SLEEP:
1.. Cyclic wake up on
0.. Cyclic wake up off
CWK1 : In SBC states STOP:
1.. Cyclic wake up on
0.. Cyclic wake up off
WD : In SBC state STOP, overwrites CWK1:
1.. Watchdog on
0.. Watchdog off
TBASE : In SBC state NORMAL:
1.. Output time base at RXDLIN1 on
0.. Output time base at RXDLIN1 off
Table 46: Watchdog configuration register 2
Register WD_STAT (0x0B)
MSB
LSB
Content
-
-
-
-
-
-
SWDM
WDRSTN
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit Description
SWDM :
1.. Software development function enabled
0.. Software development function disabled
WDRSTN :
1.. Watchdog failure event occurred
0.. No watchdog failure event occured
Table 47: watchdog status register
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register WD_TRIG (0x0D)
MSB
LSB
Content
-
-
-
-
-
-
-
TRIG
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
W
Bit Description
TRIG : Watchdog trigger, expects alternating content
After watchdog enable first bit TRIG must be 1
Table 48: watchdog trigger register
Register WD_PER (0x0C)
MSB
LSB
Content
PER[7]
PER[6]
PER[5]
PER[4]
PER[3]
PER[2]
PER[1]
PER[0]
Reset value
0
0
1
1
1
1
1
1
Access
R
R
R
R
R
R
R
R
Bit Description
PER[7] : Current watchdog period setup
PER[6] : Current watchdog period setup
PER[5] : Current watchdog period setup
PER[4] : Current watchdog period setup
PER[3] : Current watchdog period setup
PER[2] : Current watchdog period setup
PER[1] : Current watchdog period setup
PER[0] : Current watchdog period setup
Table 49: Current watchdog period. Change of period has to be performed using WD_PER1 and WD_PER2 including correct watchdog trigger afterwards within one watchdog cycle.
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register WD_PER1 (0x0E)
MSB
LSB
Content
PER[7]
PER[6]
PER[5]
PER[4]
PER[3]
PER[2]
PER[1]
PER[0]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
PER[7] : Watchdog period setup
PER[6] : Watchdog period setup
PER[5] : Watchdog period setup
PER[4] : Watchdog period setup
PER[3] : Watchdog period setup
PER[2] : Watchdog period setup
PER[1] : Watchdog period setup
PER[0] : Watchdog period setup
Table 50: Watchdog period register 1
Register WD_PER2 (0x0F)
MSB
LSB
Content
PER[0]
PER[1]
PER[2]
PER[3]
PER[4]
PER[5]
PER[6]
PER[7]
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
PER[0] : Watchdog period setup
PER[1] : Watchdog period setup
PER[2] : Watchdog period setup
PER[3] : Watchdog period setup
PER[4] : Watchdog period setup
PER[5] : Watchdog period setup
PER[6] : Watchdog period setup
PER[7] : Watchdog period setup
Table 51: Watchdog period register 2.
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
5.4.4 Watchdog timing adjustment
For very exact watchdog trigger requirements an internal time base with target frequency of 7.8125 kHz can be connected to pin RXDLIN1.
This function can be enabled accessing register WD_CFG.TBASE with correct access valid for watchdog configuration. Function needs to disabled via SPI again in order to receive messages using LIN1 again.
period
4096 us * (WD_PER + 1)
minimum period
(period - 256 us) /1.1
maximum period
(period + 256 us) /0.88
Table 52: Watchdog period and accuracy
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
5.4.5 External Reset / Reset clamping
If RSTN is overwritten externally seven cases have to be distinguished. Please also check figure Fig. 14 for details.
1. The SBC wants to give a reset and an external source pulls the RSTN line down. After the time the SBC want to
release the RSTN a timeout tWDRSTN,TO,GND starts. If no timeout occurs (first section in figure Fig. 14) SBC state and
FSON remain unchanged.
2. If the timeout occurs and the SBC detects a RSTN clamp to GND the SBC switches to either state FAILSAFE or
to state RESTART depending on configuration of bit SBC_CFG.CFG and the FSON pin is set (second section in
figure Fig. 14).
3. The SBC wants to give a reset and an external source pulls the RSTN line up dominantly. At the time SBC usually releases the reset a clamp to VDD1 is detected. So SBC holds down the reset and starts timeout
tWDRSTN,TO,VDD1. If the dominant pull up releases while the timeout runs the SBC gives a regular reset and FSON
remains unchanged (third section in figure Fig. 14).
4. If the dominant pull up does not release while the timeout runs SBC switches to either state FAILSAFE or to
state RESTART depending on configuration of bit SBC_CFG.CFG and FSON is set (fourth section in figure Fig.
14).
5. The SBC does not want to give a reset and an external source pulls down pin RSTN. There are two configurations. Configuration one is SBC_CFG.CLAMP is set to one. This causes timeout tWDRSTN,TO,GND starting. If no
timeout occurs (fifth section in figure Fig. 14) the state is changed to RESTART and FSON is unchanged.
6. If the timeout occurs and the SBC detects a RSTN clamp to GND the SBC switches either to mode FAILSAFE
or to mode RESTART depending on configuration of bit SBC_CFG.CFG and pin FSON is set (Sixth section in
figure Fig. 14).
7. Configuration two is SBC_CFG.CLAMP is set to zero. No timeout starts and the SBC detects a RSTN clamp to
GND as soon as an external clamp to GND occurs. In case of this the SBC switches to either mode FAILSAFE
or to mode RESTART depending on configuration of bit SBC_CFG.CFG and pin FSON is set (Seventh section
in figure Fig. 14).
Fig. 14: Different RSTN behaviour
Behaviour of RSTN and configuration options
5.5 Local wake up; pin WK
The device can be woken up from states SLEEP and FAILSAFE via pin WK with either a rising or a falling edge.
The edge sensitivity can be configured in register WK_CFG. To suppress glitches the input pin is debounced with
tWK,DEB.
The wake up event is signaled at pin INTN if it is configured in register WK_CFG.
If the local wake up is not used in application, the pin WK has to be connected to pin VS.
A transition into state SLEEP is prohibited with a pending wake up request. The request must be cleared via SPI
reading register WU_SRC.
Register Name
WK_CFG
Address
0x10
Description
configuration register of pin WK. Register is writeable in SBC state NORMAL
only. In SBC states INIT, RESTART or FAILSAFE all bits are set to H.
Table 53: WK RegisterTable
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register WK_CFG (0x10)
MSB
LSB
Content
-
-
-
-
-
-
FALL
RISE
Reset value
0
0
0
0
0
0
1
1
Access
R
R
R
R
R
R
R/W
R/W
Bit Description
FALL : A falling edge at pin WK leads to a wake up event.
1)
RISE : A rising edge at pin WK leads to a wake up event. 1)
Table 54: configuration register of pin WK
1) In SBC states INIT, RESTART or FAILSAFE all bits are set to H.
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
5.6 LIN Transceiver; pins LIN1 to LIN4, TXDLIN1 to TXDLIN4, RXDLIN1 to RXDLIN4, GNDLIN
5.6.1 Characteristics
The LIN BUS physical interface is implemented as a LIN 2.1 standard high-voltage single wire interface (ISO 9141)
for baud rates from 2.4kBds to 20.4kBds. The LIN bus has two logical values; the dominant state (BUS voltage near
GND) represents logical LOW level and the recessive state (BUS voltage near VS) represents logical HIGH level. In
the recessive state the BUS is pulled high by an internal pull-up resistor (typ. 30 kΩ) and a diode in series, so no
external pull-up components are required for slave applications. Master applications require an additional external
pull-up resistor and a series diode. The LIN protocol output data stream on the TXD signal is converted into the LIN
bus signal through a current limited, wave-shaping low-side driver with control as outlined by the LIN Physical Layer
Specification Revision 2.1. The receiver converts the data stream from the bus and outputs it to RXD.
Fig. 15: LIN transceiver physical layer timing
The LIN transceiver can handle a bus voltage swing from +40V down to ground and survives -27V. The device also
prevents back feed current through the LIN pin to the supply pin in case of a ground shift / loss or supply voltage
disconnection.
In sleep mode the LIN block requires a very low quiescent current by using a special wake up comparator allowing
the remote wakeup via the LIN bus. The sleep mode can be activated during recessive or dominant level of LIN bus
line.
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
5.6.2 LIN Flash Mode
A Flash mode allows an increasing of the transmit baud rate up to 115kBds and the receiver baud rate up to
250kBds. The feature is configured in register LINx_CFG.
5.6.3 LIN Wake Up
The device can be woken up remotely using corresponding pin LINx. The wake up capability can be switched on in
corresponding register LINx_CFG. In state FAILSAFE this feature is enabled regardless of configuration.
When a wake up is recognized, the corresponding flag in register WU_SRC is set.
The device supports two different behaviours.
1. A falling edge at pin LIN followed by a dominant bus level VLIN,DOM maintained for a time period tLIN,WU results in a
remote wake up request.
2. A falling edge at pin LIN followed by a dominant bus level VLIN,DOM maintained for a time period tLIN,WU, followed by
a rising edge results in a remote wake up request.
Fig. 16: LIN wake up in mode SLEEP
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Fig. 17: LIN wake up in mode INIT
Fig. 18: LIN wake up at rising edge in mode SLEEP
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Fig. 19: LIN wake up at rising edge in mode INIT
5.6.4 LIN Failure detection and recovery
All local or bus failures are signaled in register LINx_STAT.
There are two possibilities to recover the normal operation after a failure:
•
Sending two SPI commands for LIN Normal Mode, first disable receiver, second enable receiver
•
If RXD is dominant while TXD is recessive since LIN receives dominant bus levels again without driving the bus
dominant by itself
TXD Dominant clamping failure
This failure can only be detected if the LINx transmitter is enabled, e.g. if bit TR in register LINx_CFG is set to high.
If TXDx is clamped dominant for longer than tLIN,TXD,DOM the transmitter is disabled and a failure flag is set.
RXD dominant clamping failure
This failure can be detected if the receiver is enabled, e.g. if bit TR in register LINx_CFG is set. If RXDx is clamped
to dominant level for 4 consecutive LINx cycles the transmitter is disabled and a failure flag is set.
RXD recessive clamping failure
This failure can be detected if the receiver is enabled, e.g. bit TR in register LINx_CFG is set. If RXDx is clamped to
recessive level for 4 consecutive LINx cycles the transmitter is disabled and a failure flag is set.
BUS dominant clamping failure
This failure can be detected if the receiver is enabled, e.g. if bit TR in register LINx_CFG is set. If LINx is clamped
to low for longer than tLIN,BUS,DOM a failure flag is set. The transmitter is not disabled.
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
OT failure
If OT occurs transmitter is disabled and a failure flag is set. The transmitter is enabled if the temperature falls below
its threshold and if the conditions for the failure recovery are present.
TXD to RXD clamping failure
This failure can only be detected if the transmitter is enabled. Pin TXDLINx is set to low that LINx becomes dominant. Afterwards pin RXDLINx is set to low too controlled by the receiver. In case of error c52ondition present pin
TXDLINx can not be released to high because the driver of RXDLINx is much stronger. If TXDLINx is clamped
dominant for longer than tLIN,TXD,DOM the transmitter is disabled and a failure flag is set.
5.6.5 LIN Configuration
All configuration registers are writeable in state NORMAL only .
Register Name
Address
Description
LIN_CFG
0x06
Shortcut to LIN1-4 TR and RC configuration bits
LIN1_CFG
0x20
Configuration register for LIN1
LIN_INT
0x21
LIN interrupt register
LIN1_STAT
0x22
Status register for LIN1
LIN2_CFG
0x24
Configuration register for LIN2
LIN2_STAT
0x26
Status register for LIN2
LIN3_CFG
0x28
Configuration register for LIN3
LIN3_STAT
0x2A
Status register for LIN3
LIN4_CFG
0x2C
Configuration register for LIN4
LIN4_STAT
0x2E
Status register for LIN4
Table 55: LIN RegisterTable
Register LIN_INT (0x21)
MSB
LSB
Content
LIN4
LIN3
LIN2
LIN1
-
-
-
-
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit Description
LIN4 : 1.. LIN4 is reason for interrupt
0.. LIN4 is not reason for interrupt
LIN3 : 1.. LIN3 is reason for interrupt
0.. LIN3 is not reason for interrupt
LIN2 : 1.. LIN2 is reason for interrupt
0.. LIN2 is not reason for interrupt
LIN1 : 1.. LIN1 is reason for interrupt
0.. LIN1 is not reason for interrupt
Table 56: LIN interrupt register
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register LIN1_CFG (0x20)
MSB
LSB
Content
-
FAILINT
FLASH
WUINT
WUCFG
WU
TR
RC
Reset value
0
0
0
0
1
1
0
0
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
FAILINT :
1...Interrupt enabled for LIN failures, could only be set if RC is set. This is locked by hardware.
0...Interrupt disabled for LIN failures
FLASH : The FLASH mode deactivates filtering and provides a baud rate of up to 125kBaud for
transmitting and 250kBaud for receiving.
1...Flash mode enabled
0...Flash mode disabled
WUINT :
1...Interrupt enabled if WU is detected
0...Interrupt disabled if WU is detected
WUCFG :
1... Wake up is performed with next rising edge after LIN wake up debounce time
0.. Wake up is performed after LIN wake up debounce time
WU :
1...Wake up capability enabled, could only be set if RC and TR are not set. This is locked by
hardware.
0...Wake up capability disabled
TR :
1...Transmitter enabled, RC is enabled automatically, WU is cleared
0...Transmitter disabled
RC :
1...receiver enabled, read bus only, WU is cleared
0...receiver disabled
Table 57: Configuration register for LIN1
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register LIN1_STAT (0x22)
MSB
LSB
Content
-
Bus short
TXDDOM BUSDOM RXDREC
RXDDOM -
-
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit Description
Bus short :
1...LIN short circuit detected
0...LIN short circuit not detected
TXDDOM :
1...TXD permanent dominant clamping timeout exceeded
0...TXD permanent dominant clamping timeout not exceeded
BUSDOM :
1...LIN permanent dominant clamping timeout exceeded
0...LIN permanent dominant clamping timeout not exceeded
RXDREC :
1...RXD permanent recessive clamping timeout exceeded
0...RXD permanent recessive clamping timeout not exceeded
RXDDOM :
1...RXD permanent dominant clamping timeout exceeded
0...RXD permanent dominant clamping timeout not exceeded
Table 58: Status register for LIN1
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register LIN2_CFG (0x24)
MSB
LSB
Content
-
FAILINT
FLASH
WUINT
WUCFG
WU
TR
RC
Reset value
0
0
0
0
1
1
0
0
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
FAILINT :
1...Interrupt enabled for LIN failures, could only be set if RC is set. This is locked by hardware.
0...Interrupt disabled for LIN failures
FLASH : The FLASH mode deactivates filtering and provides a baud rate of up to 125kBaud for
transmitting and 250kBaud for receiving.
1...Flash mode enabled
0...Flash mode disabled
WUINT :
1...Interrupt enabled if WU is detected
0...Interrupt disabled if WU is detected
WUCFG :
1... Wake up is performed with next rising edge after LIN wake up debounce time
0.. Wake up is performed after LIN wake up debounce time
WU :
1...Wake up capability enabled, could only be set if RC and TR are not set. This is locked by
hardware.
0...Wake up capability disabled
TR :
1...Transmitter enabled, RC is enabled automatically, WU is cleared
0...Transmitter disabled
RC :
1...receiver enabled, read bus only, WU is cleared
0...receiver disabled
Table 59: Configuration register for LIN2
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register LIN2_STAT (0x26)
MSB
LSB
Content
-
Bus short
TXDDOM BUSDOM RXDREC
RXDDOM -
-
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit Description
Bus short :
1...LIN short circuit detected
0...LIN short circuit not detected
TXDDOM :
1...TXD permanent dominant clamping timeout exceeded
0...TXD permanent dominant clamping timeout not exceeded
BUSDOM :
1...LIN permanent dominant clamping timeout exceeded
0...LIN permanent dominant clamping timeout not exceeded
RXDREC :
1...RXD permanent recessive clamping timeout exceeded
0...RXD permanent recessive clamping timeout not exceeded
RXDDOM :
1...RXD permanent dominant clamping timeout exceeded
0...RXD permanent dominant clamping timeout not exceeded
Table 60: Status register for LIN2
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register LIN3_CFG (0x28) - should not be used with E521.02 and E521.12
MSB
LSB
Content
-
FAILINT
FLASH
WUINT
WUCFG
WU
TR
RC
Reset value
0
0
0
0
1
1
0
0
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
FAILINT :
1...Interrupt enabled for LIN failures, could only be set if RC is set. This is locked by hardware.
0...Interrupt disabled for LIN failures
FLASH : The FLASH mode deactivates filtering and provides a baud rate of up to 125kBaud for
transmitting and 250kBaud for receiving.
1...Flash mode enabled
0...Flash mode disabled
WUINT :
1...Interrupt enabled if WU is detected
0...Interrupt disabled if WU is detected
WUCFG :
1... Wake up is performed with next rising edge after LIN wake up debounce time
0.. Wake up is performed after LIN wake up debounce time
WU :
1...Wake up capability enabled, could only be set if RC and TR are not set. This is locked by
hardware.
0...Wake up capability disabled
TR :
1...Transmitter enabled, RC is enabled automatically, WU is cleared
0...Transmitter disabled
RC :
1...receiver enabled, read bus only, WU is cleared
0...receiver disabled
Table 61: Configuration register for LIN3
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register LIN3_STAT (0x2A) - should not be used with E521.02 and E521.12
MSB
LSB
Content
-
Bus short
TXDDOM BUSDOM RXDREC
RXDDOM -
-
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit Description
Bus short :
1...LIN short circuit detected
0...LIN short circuit not detected
TXDDOM :
1...TXD permanent dominant clamping timeout exceeded
0...TXD permanent dominant clamping timeout not exceeded
BUSDOM :
1...LIN permanent dominant clamping timeout exceeded
0...LIN permanent dominant clamping timeout not exceeded
RXDREC :
1...RXD permanent recessive clamping timeout exceeded
0...RXD permanent recessive clamping timeout not exceeded
RXDDOM :
1...RXD permanent dominant clamping timeout exceeded
0...RXD permanent dominant clamping timeout not exceeded
Table 62: Status register for LIN3
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register LIN4_CFG (0x2C) - should not be used with E521.02, E521.03, E521.12 and E521.13
MSB
LSB
Content
-
FAILINT
FLASH
WUINT
WUCFG
WU
TR
RC
Reset value
0
0
0
0
1
1
0
0
Access
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
FAILINT :
1...Interrupt enabled for LIN failures, could only be set if RC is set. This is locked by hardware.
0...Interrupt disabled for LIN failures
FLASH : The FLASH mode deactivates filtering and provides a baud rate of up to 125kBaud for
transmitting and 250kBaud for receiving.
1...Flash mode enabled
0...Flash mode disabled
WUINT :
1...Interrupt enabled if WU is detected
0...Interrupt disabled if WU is detected
WUCFG :
1... Wake up is performed with next rising edge after LIN wake up debounce time
0.. Wake up is performed after LIN wake up debounce time
WU :
1...Wake up capability enabled, could only be set if RC and TR are not set. This is locked by
hardware.
0...Wake up capability disabled
TR :
1...Transmitter enabled, RC is enabled automatically, WU is cleared
0...Transmitter disabled
RC :
1...receiver enabled, read bus only, WU is cleared
0...receiver disabled
Table 63: Configuration register for LIN4
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Register LIN4_STAT (0x2E) - should not be used with E521.02, E521.03, E521.12 and E521.13
MSB
LSB
Content
-
Bus short
TXDDOM BUSDOM RXDREC
RXDDOM -
-
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit Description
Bus short :
1...LIN short circuit detected
0...LIN short circuit not detected
TXDDOM :
1...TXD permanent dominant clamping timeout exceeded
0...TXD permanent dominant clamping timeout not exceeded
BUSDOM :
1...LIN permanent dominant clamping timeout exceeded
0...LIN permanent dominant clamping timeout not exceeded
RXDREC :
1...RXD permanent recessive clamping timeout exceeded
0...RXD permanent recessive clamping timeout not exceeded
RXDDOM :
1...RXD permanent dominant clamping timeout exceeded
0...RXD permanent dominant clamping timeout not exceeded
Table 64: Status register for LIN4
Register LIN_CFG (0x06)
MSB
LSB
Content
TR4
RC4
TR3
RC3
TR2
RC2
TR1
RC1
Reset value
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Description
TR4 : Same as LIN4_CFG.TR. Should set to 0 with E521.02, E521.03, E521.12 and E521.13
RC4 : Same as LIN4_CFG.RC. Should set to 0 with E521.02, E521.03, E521.12 and E521.13
TR3 : Same as LIN3_CFG.TR. Should set to 0 with E521.02 and E521.12
RC3 : Same as LIN3_CFG.RC. Should set to 0 with E521.02 and E521.12
TR2 : Same as LIN2_CFG.TR
RC2 : Same as LIN2_CFG.RC
TR1 : Same as LIN1_CFG.TR
RC1 : Same as LIN1_CFG.RC
Table 65: Shortcut to LIN1-4 TR and RC configuration bits
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
5.7 HS-CAN Transceiver; pins CANH, CANL, RXDCAN, TXDCAN, VDDCAN
The HS-CAN transceiver is compatible to ISO 11898-5.
CANH and CANL interface the CAN protocol controller to HS-CAN physical layer wires. Data rate can be selected
up to 1MegBaud.
Fig. 20: HS-CAN Bus timing
5.7.1 CAN Wake up
The device is capable detecting wake up pattern at the CAN bus if configured. A wake up pattern ideally consists of
four consecutive symbols dominant, recessive, dominant and recessive. The dominant bus states have to be longer
than tCAN,WAKE_BUS_DOM and the recessive bus states have to be longer than tCAN,WAKE_BUS_REC. The pattern must be
applied within tWAKE2.
When the wake up pattern is recognized, the corresponding flag in register WU_SRC is set.Pin INTN is set low if bit
CAN_CFG.WUINT was set high. Pin RXDCAN is set to low until bit CAN_CFG.RC is set high or register WU_SRC
is read.
Fig. 21: Remote Wakeup Pattern
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CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
5.7.2 CAN Failure detection and recovery
All CAN related local or bus failures are signaled in register CAN_STAT.
There are two possibilities to recover the normal operation after a failure:
•
Sending the SPI command for CAN Normal Operation Mode
•
If RXD is dominant while TXD is recessive
TXD Dominant clamping failure
This failure can only be detected if the transmitter is enabled, e.g. bit TR in register CAN_CFG is set to high. If TXDCAN is clamped dominant for longer than tCAN,TXD,DOM the transmitter is disabled and a failure flag is set.
RXD dominant clamping failure
This failure can be detected if the receiver is enabled, e.g. bit RC or TR in register CAN_CFG is set. If RXDCAN is
clamped low for 4 consecutive CAN cycles the transmitter is disabled and a failure flag is set.
RXD recessive clamping failure
This failure can be detected if the receiver is enabled, e.g. bit RC or TR in register CAN_CFG is set. If RXDCAN is
clamped recessive level for 4 consecutive CAN cycles the transmitter is disabled and a failure flag is set.
BUS dominant clamping failure
This failure can be detected if the receiver is enabled, e.g. bit RC or TR in register CAN_CFG is set. If CAN is
clamped dominant for longer than tCAN,BUS,DOM a failure flag is set. The transmitter is not disabled.
TXD to RXD clamping failure
This failure can only be detected if the transmitter is enabled. Pin TXDCAN is set to low that CAN becomes dominant. Afterwards pin RXDCAN is set to low too controlled by the receiver. In case of error condition present pin TXDCAN can not be released to high because the driver of RXDCAN is much stronger. If TXDCAN is clamped dominant for longer than tCAN,TXD,DOM the transmitter is disabled and a failure flag is set.
OT failure
If OT occurs the transmitter is disabled and a failure flag is set. The transmitter is enabled again if the temperature
falls below its threshold and the conditions for the failure recovery are present.
CANH to GND clamping failure
This failure can be detected if the transmitter is enabled, e.g. bit TR in register CAN_CFG is set. If the short is
present for 4 consecutive CAN cycles of at least tBUS,FAIL a failure flag is set. The transmitter is not disabled. The failure is cleared if CANH is not clamped to GND anymore.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
CANL to GND clamping failure
This failure can be detected if the transmitter is enabled, e.g. bit TR in register CAN_CFG is set. If the short is
present for 4 consecutive CAN cycles of at least tBUS,FAIL a failure flag is set. The transmitter is not disabled. The failure is cleared if CANH is not clamped to GND anymore.
CANH to VDDCAN/VS clamping failure
This failure can be detected if the transmitter is enabled, e.g. bit TR in register CAN_CFG is set. If the short is
present for 4 consecutive CAN cycles of at least tBUS,FAIL a failure flag is set. The transmitter is not disabled. The failure is cleared if CANH is not clamped to VDDCAN/VS anymore.
CANL to VCC/VS clamping failure
This failure can be detected if the transmitter is enabled, e.g. bit RC or TR in register CAN_CFG is set. If the short
is present for 4 consecutive CAN cycles of at least tBUS,FAIL a failure flag is set. The transmitter is not disabled. The
failure is cleared if CANH is not clamped to VDDCAN/VS anymore.
5.7.3 CAN Configuration
Register Name
Address
Description
CAN_CFG
0x30
Configuration register for CAN
CAN_STAT
0x32
Status register for CAN
Table 66: CAN RegisterTable
Register CAN_CFG (0x30)
MSB
LSB
Content
-
FAILINT
-
WUINT
BF
WU
TR
RC
Reset value
0
0
0
1
0
1
0
0
Access
R
R/W
R
R/W
R/W
R/W
R/W
R/W
Bit Description
FAILINTEN : 1...interrupt enabled for CAN failures
0...interrupt disabled for CAN failures
WUINT : 1...interrupt enabled if WU is detected
0...interrupt disabled if WU is detected
BF : 1.. CAN bus short failure detection enabled 0.. CAN bus short failure detection disabled
WU : 1...wake up capability enabled, only valid if RC and TR are 0
0...wake up capability disabled
TR : 1...transmitter enabled, RC is enabled automatically, WU is masked
0...transmitter disabled
RC : 1...receiver enabled, listen only, WU is masked
0...receiver disabled
Table 67: Configuration register for CAN
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CAN/LIN SBC Family with DC/DC Voltage Regulator
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PRODUCTION DATA – Mar 7, 2016
Register CAN_STAT (0x32)
MSB
LSB
Content
CHVCC
CHGND
CLVCC
CLGND
RXDREC
RXDDOM BUSDOM TXDDOM
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit Description
CHVCC : 1.. CANH to VCC or VS clamping detected
0.. CANH to VCC or VS clamping not detected
CHGND : 1.. CANH to GND clamping detected
0.. CANH to GND clamping not detected
CLVCC : 1.. CANL to VCC or VS clamping detected
0.. CANL to VCC or VS clamping not detected
CLGND : 1.. CANL to GND clamping detected
0.. CANL to GND clamping not detected
RXDREC : 1.. RXD permanent recessive clamping timeout exceeded
0.. RXD permanent recessive clamping timeout not exceeded
RXDDOM : 1.. RXD permanent dominant clamping timeout exceeded
0.. RXD permanent dominant clamping timeout not exceeded
BUSDOM : 1.. CAN permanent dominant clamping timeout exceeded
0.. CAN permanent dominant clamping timeout not exceeded
TXDDOM : 1.. TXD permanent dominant clamping timeout exceeded
0.. TXD permanent dominant clamping timeout not exceeded
Table 68: Status register for CAN
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CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
5.8 Limp Home support; pin FSON
SBC features limp home support using pin FSON.
Activation of FSON is not linked to SBC mode FAILSAFE only. Please check sections 5.8.1 and 5.2 for details.
In order to activate output pin FSON using SPI command. Both registers FSON_CFG1 and FSON_CFG2 need to
be accessed within one watchdog period for system safety reasons. If contents of registers is equal pin FSON is
activated when watchdog is triggered. Otherwise no change is made.
Register Name
Address
Description
FSON_STAT
0x02
FSON status register.
FSON_CFG1
0x1B
FSON configuration register 1
FSON_CFG2
0x1C
FSON configuration register 2
Table 69: FSON RegisterTable
Register FSON_CFG1 (0x1B)
MSB
LSB
Content
CLAMP
-
-
SPI
-
-
-
-
Reset value
1
0
0
0
0
0
0
0
Access
R/W
R
R
R/W
R
R
R
R
Bit Description
CLAMP : 1.. External reset shorter than tWDRSTN,TO,GND will not lead to FSON set
0.. External reset leads to FSON set immediately
SPI : 1.. Activate FSON
0.. Deactivate FSON
Table 70: FSON configuration register 1
Register FSON_CFG2 (0x1C)
MSB
LSB
Content
-
-
-
-
SPI
-
-
CLAMP
Reset value
0
0
0
0
0
0
0
1
Access
R
R
R
R
R/W
R
R
R/W
Bit Description
SPI : 1.. Activate FSON
0.. Deactivate FSON
CLAMP : 1.. External reset shorter than tWDRSTN,TO,GND will not lead to FSON set
0.. External reset leads to FSON set immediately
Table 71: FSON configuration register 2
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CAN/LIN SBC Family with DC/DC Voltage Regulator
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PRODUCTION DATA – Mar 7, 2016
Register FSON_STAT (0x02)
MSB
LSB
Content
-
VDD1UV
WD
OT
INITTO
RSTNSC
FSON_SPI FSON_INT
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit Description
VDD1UV : 1..VDD1 under voltage detected
0..VDD1 under voltage not detected
WD : 1..Watchdog trigger failure detected
0..Watchdog trigger failure not detected
OT : 1..Over temperature detected
0..Over temperature not detected
INITTO : 1..Timeout in mode INIT detected
0..Timeout in mode INIT not detected
RSTNSC : 1..RSTN clamped low externally
0..RSTN not clamped low externally
FSON_SPI : 1..FSON activated via SPI
0..FSON not activated via SPI
FSON_INT : 1..FSON activated due to FAILSAFE condition detected
0..FSON not activated due to no FAILSAFE condition detected
Table 72: FSON status register.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
5.8.1 Activation of FSON
FSON is activated in following cases:
1. SBC init mode not left within time tTO,INIT
2. VDD1 time out tTO,VDD1
3. Activated by SPI command accessing FSON_CFG1.FSON_SPI and FSON_CFG2.FSON_SPI within one watchdog cycle
4. Permanent clamping of RSTN to GND
5. Permanent clamping of RSTN to VDD1
6. External Reset on RSTN (partly configurable withSBC_CFG.CLAMP)
7. Over temperature
8. Watchdog failure
Fig. 22: Activation of FSON
Activation sources for limp home output FSON
5.8.2 Deactivation of FSON
FSON is deactivated in following cases:
1. µC sent deactivation command via SPI AND SBC is in state NORMAL AND µC sent correct watchdog trigger
2. VS falls below VSVS,PD
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Fig. 23: Deactivation of FSON
Deactivation sources for limp home output FSON
5.9 Interrupt; pin INTN
The interrupt pin is driven low if the following interrupt sources/conditions occur:
•
wake up event at CAN, LIN or WK, cyclic wake up
•
over temperature warning
•
over temperature shut down
•
under voltage at VDD1 or VDD2
•
communication failures at CAN or LIN
Interrupts can be enabled in configuration registers of the corresponding modules.
For over temperature and under voltage the appearance and disappearance is signaled via an interrupt. Therefore
after SPI reading of interrupt source pin INTN is not blocked if the interrupt condition is still active.
In order to evaluate detailed reason for interrupt read corresponding status registers.
Register Name
Address
Description
INT
0x03
Interrupt status register
VDD_STAT
0x1A
VDD1, VDD2 and VDDCAN status information.
Table 73: INTN RegisterTable
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CAN/LIN SBC Family with DC/DC Voltage Regulator
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PRODUCTION DATA – Mar 7, 2016
Register INT (0x03)
MSB
LSB
Content
CAN
LIN
WAKE
VDDx
OTWARN OT
FSM/SPI
-
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit Description
CAN : 1... HS-CAN interface is reason for interrupt
LIN : 1... At least one of the LIN interfaces is reason for interrupt
WAKE : 1... Wake up event is reason for interrupt
VDDx : 1... Under voltage condition is reason for interrupt
OTWARN : 1... Over temperature warning level crossing is reason for interrupt
OT : 1... Over temperature shutdown level crossing is reason for interrupt
FSM/SPI : 1... FSM or SPI are reasons for interrupt
Table 74: Interrupt status register
Register VDD_STAT (0x1A)
MSB
LSB
Content
VDD2 ON VDD2 ENA VDD2OC
PAD
VDD2 UV
-
VDDCAN
UV
VDD1 UV
-
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Bit Description
VDD2 ON : 1..Linear voltage regulator VDD2 enabled
0..Linear voltage regulator VDD2 disabled
VDD2 ENA PAD : 1..ENVDD2 set to logic level 1
0..ENVDD2 set to logic level 0
VDD2OC : 1..VDD2 over current detected
0..VDD2 over current not detected
VDD2 UV : 1.. VDD2 under voltage detected
0.. VDD2 under voltage not detected
VDDCAN UV : 1.. VDDCAN under voltage detected. If CAN is not activated, this bit is high
without generating a interrupt in this case.
0.. VDDCAN under voltage not detected
VDD1 UV : 1.. VDD1 under voltage detected
0.. VDD1 under voltage not detected
Table 75: VDD1, VDD2 and VDDCAN status information.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
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Fig. 24: Interrupt and status register dependency
In case of interrupt detailed information can be read from device in order to evaluate reason for interrupt.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
5.10 DCDC Buck converter; pins VIN, VDD1, VDD1SENSE, LXT, PGND
Register Name
Address
VDD1_CFG
0x14
Description
VDD1 configuration register
Writing register in SBC state FAILSAFE is not allowed
Table 76: VDD1 RegisterTable
Register VDD1_CFG (0x14)
MSB
LSB
Content
t1_1
t1_0
IDLE
-
-
STOP
THR_1
THR_0
Reset value
0
1
1
0
0
0
0
0
Access
R/W
R/W
R/W
R
R
R
R/W
R/W
Bit Description
t1_1 : configuration of time t1 for SBC mode STOP observation
t1_0 : configuration of time t1 for SBC mode STOP observation
00...5ms
01...10ms
10...20ms
11...40ms
IDLE :
1.. activate IDLE prevention
0.. deactivate IDLE prevention
IDLE detected:
• DCDC on
• DCDC reports IDLE
• V(VDD1) < typ. 0.98*VDD1nom
STOP : selection of behaviour in state stop
1..in case of high current consumption state remains in STOP
0..in case of high current consumption state is changed to NORMAL
THR_1 : selection of reset threshold
THR_0 : selection of reset threshold
00...VTH1,VDD1,RSTN
01...VTH2,VDD1,RSTN
10...VTH3,VDD1,RSTN
11...VTH4,VDD1,RSTN
Table 77: VDD1 configuration register
Remark: Register Writing register in SBC state FAILSAFE is not allowed
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CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
5.10.1 General Description
The DCDC buck converter is a fixed output voltage step-down converter intended for automotive and general battery driven applications, featuring open loop stability and short current limitation for the integrated driver transistor.
The device is offered in a 5V output voltage version providing up to 500mA output current.
The modulation scheme is based on Pulse Frequency Modulation. For operation a clock signal is not needed,
providing minimum ON/OFF time regulation for the internal switch. Internal current measurement allows to reduce
the ON time below the given nominal ON time to prevent excessive current flow in the inductor.
5.10.2 Pulse Frequency Modulated Converter
The following sub chapters provide descriptions of the blocks implemented to control the output voltage. The regulation principle provides an adaptive operation frequency of typ. up to 1.3MHz, depending on VVIN / VVDD1 voltage
ratio and load conditions.
PFM Control Logic
PFM control logic generates the timings necessary to control the converter based on a combination of output
voltage, temperature and measured switch current. It provides adaptive frequency, depending on input voltage to
output voltage ratio in the range of 0Hz up to typ. >1.3MHz.
Internal Power Switch
The internal highside power switch connects VIN and LXT controlled by PFM control logic.
The highside power switch current is limited providing saturation protection to the inductor and to prevent over current damage to the application. It allows startup of the converter without soft-start measures.
5.10.3 Application / Implementation Hints
Output voltage ripple is strongly dependent on peripheral elements chosen (LLXT and CVDD1SENSE) and their parasitic
behavior. ESR of output capacitance CVDD1SENSE must be suitable to ensure a small ripple for proper regulation (see
recommended operating conditions). The ripple voltage can be calculated by
VRIPPLE,VDD1SENSE = RESR,COUT * IRIPPLE,L_LXT
The DC resistance of LLXT reduces the efficiency but does not affect the output voltage ripple. (Though a high resistance can generate a significant thermal power within the inductor). Furthermore higher DC resistance will also
increase the minimum input voltage requirements for nominal output voltage.
The free-wheeling diode must have a low forward voltage as well as a low reverse recovery time. Parasitic capacitance of this diode decreases the overall efficiency and causes current spikes when the driver turns on (consider this
behaviour for EMI).
For low power requirements on VDD1 consider the leakage of the freewheeling diode at nominal converter output
voltage. Leakage current will contribute to the overall output current of the converter.
A reverse polarity diode for VIN is recommended. In EMC sensitive environments additional decoupling measures
at VIN are recommended.
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CAN/LIN SBC Family with DC/DC Voltage Regulator
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5.10.4 VDD1 under-voltage monitor
If VDD1 < VTHx,VDD1_f,RSTN a reset is generated and pin RSTN is set to L. SBC enters state RESTART or FAILSAFE
depending on SBC_CFG.CFG. If VDD1 > VTHx,VDD1,RSTN reset will be enlarged and RSTN will be held L for tRSTN,VDD1.
After that RSTN is set to H.
To prevent high or short current events VDD1 is monitored. If VDD1 < VTHx,VDD1,RSTN timeout tTO,VDD1 is started. If
timeout exceeds SBC is set to state FAILSAFE and regulator is switched off.
If VDD1 > VTHx,VDD1,RSTN timeout is reset.
Timeout is enabled only if VS > VON-OFF,VS. Otherwise VDD1 will not reach its output value.
5.11 Low drop regulator; pins VDD2, ENVDD2
The on chip low drop voltage regulator (LDO) provides a voltage of typically 5.0V at pin VDD2. LDO can be active in
SBC operating states NORMAL, STOP, SLEEP, RESTART or FAILSAFE. It can be activated via SPI or via pin
ENVDD2. VS related pin ENVDD2 has higher priority. In order to save system current ENVDD2 does not implement
pull down functionality.
If the external pin ENVDD2 is low the SPI register determines status of LDO. Otherwise if the pin ENVDD2 is high
the LDO is activated independently of the contents of the register VDD2_CFG.ON. In case of external deactivation
of VDD2 using pin ENVDD2 LDO is switched off as well as SPI register is reset to off state. Register VDD2_CFG
can be written in state NORMAL only. It is cleared in state FAILSAFE. The LDO is limited in output current. Current
limitation is always activated. Over voltage protection against VS and reverse polarity protection are implemented.
An over temperature protection using both warning and shutdown levels is implemented. In case of over temperature detection an interrupt is generated. Voltage supervision including interrupt generation is implemented.
Register Name
Address
VDD2_CFG
0x18
Description
VDD2 configuration register
Table 78: VDD2 RegisterTable
Register VDD2_CFG (0x18)
MSB
LSB
Content
-
-
-
-
-
-
-
ON
Reset value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R/W
Bit Description
ON : 1... enables regulator
Table 79: VDD2 configuration register
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
5.12 DCDC Boost converter; pins MDRV, ISEN, PGND2
For applications relevant during startup, an optional input voltage boost converter can be added. The boost converter activates if the supply voltage at pin VS falls below the VBOOST level. Then the gate driver sets active level on
pin MDRV driving the gate of external power-MOS-switch for either maximum ON-time TONMAX4 or till the current
reaches the threshold VISEN sensing on shunt at pin ISEN. After switching off at pin MDRV the next switch on will be
only after expiration minimum OFF-time TOFFMIN4. Each switch on event holds the pin MDRV active at least for the
minimum ON-time TONMIN4 regardless of current sense level at pin ISEN. So the boost converter is self oscillating. It
can also be deactivated if pin ISEN is not connected to external Rsense and externally pulled up between 2V and
VDD1 level.
Booster activation is controlled using SBC_CFG.BOOST. In default setup booster set to off.
Option1 to
D1
Lsup
suppress distortions
caused by supply parasitics
Rsup
D2
LBOOST
VS
VBOOST
SUPPLY
PARASITICS
CBOOST_IN
C BOOST_OUT
Option2
D1
BOOSTER
VDD1
(nominal 5V)
VDD
(nominal 3.3V)
VREF2
G
A
T
E
+
COMP1
ON
If VDD1 > 4.5V
& No POR
VREF1
+
COMP2
-
P
F
M
LEVELSHIFTER C
T
R
L
HSD
EXTERN
FET
LSD
ISENSE
VISEN
R
S
E
N
S
E
Fig. 25: Functional diagram Booster
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
6 Register Table
Register Name
Address
Description
SBC_CFG
FSON_STAT
INT
WU_SRC
SPI_FAIL
LIN_CFG
WD_CFG
0x01
0x02
0x03
0x04
0x05
0x06
0x08
SBC configuration register.
FSON status register.
Interrupt status register
Wake up source register. Wake up source is cleared if register is read.
SPI programming failure register. Register is cleared by reading via SPI.
Shortcut to LIN1-4 TR and RC configuration bits
Current watchdog configuration. Change of configuration has to be performed
using WD_CFG1 and WD_CFG2 including correct watchdog trigger afterwards
within one watchdog cycle in SBC mode NORMAL
WD_CFG1
WD_CFG2
WD_STAT
WD_PER
0x09
0x0A
0x0B
0x0C
Watchdog configuration register 1
Watchdog configuration register 2
watchdog status register
Current watchdog period. Change of period has to be performed using
WD_PER1 and WD_PER2 including correct watchdog trigger afterwards within
one watchdog cycle.
WD_TRIG
WD_PER1
WD_PER2
WK_CFG
0x0D
0x0E
0x0F
0x10
watchdog trigger register
Watchdog period register 1
Watchdog period register 2.
configuration register of pin WK. Register is writeable in SBC state NORMAL
only. In SBC states INIT, RESTART or FAILSAFE all bits are set to H.
VDD1_CFG
0x14
VDD1 configuration register. Writing register in SBC state FAILSAFE is not
allowed
VDD2_CFG
VDD_STAT
SPI_STAT
OT_STAT
LIN1_CFG
LIN_INT
LIN1_STAT
LIN2_CFG
LIN2_STAT
LIN3_CFG
LIN3_STAT
LIN4_CFG
LIN4_STAT
CAN_CFG
CAN_STAT
0x18
0x1A
0x1B
0x1F
0x20
0x21
0x22
0x24
0x26
0x28
0x2A
0x2C
0x2E
0x30
0x32
VDD2 configuration register
VDD1, VDD2 and VDDCAN status information.
Status register with respect to FSM.
Over temperature detection status register.
Configuration register for LIN1
LIN interrupt register
Status register for LIN1
Configuration register for LIN2
Status register for LIN2
Configuration register for LIN3
Status register for LIN3
Configuration register for LIN4
Status register for LIN4
Configuration register for CAN
Status register for CAN
Table 80: Register Table
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
7 Applications Information
7.1 Overview
The device E521.02 .. E521.04 is used in application without pre-booster, while E521.12 .. E521.14 supports preboost functionality. The following chapters show typical operating circuits of these two use cases.
7.2 Typical Operating Circuit with booster
Table 81. External Components
Description
Condition
Symbol
Min
Typ
Max
Unit
Battery supply input pins
Battery filter capacitor to ground
C1
100
nF
Battery buffer capacitor to ground
C2
47
µF
L1
2.2
µH
EMC filter inductor
Saturation current
relative to maximum
application current
IVDD1
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CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Description
Condition
Symbol
Min
Typ
Max
Unit
10
22
-
μF
VS, VIN buffer capacitance to ground
Effective ESR of
C3, C4 shall be
< 300mΩ
C3
VS, VIN filter capacitance to ground
Effective ESR of
C3, C4 shall be
< 300mΩ
C4
100
nF
Optional LP filter capacitance for WK
CWK
22
nF
LP filter resistor for pin WK
RWK
1
3.3
10
kΩ
18
33
82
μH
0.1
0.6
Ω
WK
VDD1
Inductance at LXT to output voltage
IVDD1 < 500mA
L2
Serial Resistance of LXT Inductance
IVDD1 < 500mA
RL2
Relative Saturation Current of LXT
Inductor
Saturation current
relative to maximum
application current
IVDD1
Freewheeling Diode Forward Voltage
e.g. MBR
Forward current
1.3 x I(VDD1)
TAMB = 25°C
VD2
0.6
1
V
Reverse Recovery Time of Freewheel- Forward current
ing Diode
1.3 x I(VDD1)
TAMB = 25°C
tD2,rec
10
25
ns
100
mV
140
mΩ
Peak to peak voltage ripple at
VDD1SENSE for regulation,
regulation ripple included in 2% tolerance window for VDD1
IL2,SAT
VVDD1SENSE,RIPP
130
%
10
LE
VDD1SENSE Decoupling resistor
RSER
50
60
VDD1_1 external buffer capacitor
Effective ESR of
C5, C6, C7, C8 shall
be < 10mΩ
C5
10
μF
VDD1_1 external filter capacitor
Effective ESR of
C5, C6, C7, C8 shall
be < 10mΩ
C6
33
nF
VDD1_2 external buffer capacitor
Effective ESR of
C5, C6, C7, C8 shall
be < 10mΩ
C7
10
μF
VDD1_2 external filter capacitor
Effective ESR of
C5, C6, C7, C8 shall
be < 10mΩ
C8
33
nF
VDDCAN external buffer capacitor
ESR < TBD
C9
10
μF
VDDCAN external filter capacitor
ESR < TBD
C10
33
nF
VDDCAN
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CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
Description
Condition
Symbol
Min
2.2
Typ
Max
Unit
22
μF
VDD2
External buffer capacitor for VDD2
ESR > 200mΩ
C11
External filter capacitor
close to pin VDD2
C12
100
nF
External filter capacitor
close to external
connector if used as
external sensor supply (global pin)
C13
4.7
nF
Isat depends on Rsense
selection
L1
2.2
μH
Booster (optional)
Booster inductance
Booster diode, e.g. SS24
D2
Booster input buffer capacitance
C2
Booster input filter capacitance
C1
Booster output buffer capacitance
ILOAD_VS < 600mA
C3
50
100
-
TBD
50
μF
nF
-
μF
ESR < 50mΩ
Booster output filter capacitance
C4
TBD
nF
Current sense resistance
Isat_Lboost > 1.8A
R1_60
60
mΩ
Current sense resistance
Isat_Lboost > 3.6A
R1_30
30
mΩ
RDSon of the external FET
VVDD1 > 4.5V
RDSON,T1
30
mΩ
Total gate charge of the external FET VDS = 5V
VGS = 5V
ID = 3.6A
Vth < 3V
QbBOOST_ext_FET
10
nC
Maximal forward current of the
external Booster diode D1, D2
IAV(SKD_BOOST)
Maximal forward voltage of the
external Booster diode D1, D2 @ 3.6A
VF(SKD_BOOST)
3.6
A
500
mV
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CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
8 Package Information
The E521.14 device family is available in a Pb free, RoHs compliant, QFN44L7 plastic package according to
JEDEC MO-220 K.01 VKKD-3.
The package is classified to Moisture Sensitivity Level 3 (MSL 3) according to JEDEC J-STD-020C with a soldering
peak temperature of (260+5)°C.
Note:
Thermal resistance junction to ambient Rth,ja is typ. 24 °C/W, based on JEDEC standard JESD-51-2, JESD51-5 and JESD-51-7.
Description
Symbol
mm
typ
min
max
min
inch
typ
max
Package height
A
0.80
0.90
1.00
0.031
0.035
0.039
Stand off
A1
0.00
0.02
0.05
0.000
0.00079
0.002
Thickness of terminal leads, including lead finish
A3
--
0.20 REF
--
--
0.0079 REF
--
Width of terminal leads
b
0.18
0.25
0.30
0.007
0.010
0.012
Package length / width
D/E
--
7.00 BSC
--
--
0.276 BSC
--
D2 / E2
5.50
5.65
5.80
0.217
0.223
0.229
e
--
0.5 BSC
--
--
0.020 BSC
--
Length of terminal for soldering to substrate
L
0.35
0.40
0.45
0.014
0.016
0.018
Number of terminal positions
N
Length / width of exposed pad
Lead pitch
44
44
Note: the mm values are valid, the inch values contains rounding errors
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QM-No.: 25DS0093E.01
CAN/LIN SBC Family with DC/DC Voltage Regulator
E521.02/03/04/12/13/14
PRODUCTION DATA – Mar 7, 2016
WARNING – Life Support Applications Policy
Elmos Semiconductor AG is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in
general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing Elmos Semiconductor AG products, to observe standards of safety, and to avoid situations in which malfunction or failure of an
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ensure that Elmos Semiconductor AG products are used within specified operating ranges as set forth in the most recent product specifications.
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Semiconductor AG for its use, nor for any infringements of patents or other rights of third parties, which may result from its use. No license is
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to make changes to this document or the products contained therein without prior notice, to improve performance, reliability, or manufacturability .
Application Disclaimer
Circuit diagrams may contain components not manufactured by Elmos Semiconductor AG, which are included as means of illustrating typical
applications. Consequently, complete information sufficient for construction purposes is not necessarily given. The information in the application examples has been carefully checked and is believed to be entirely reliable. However, no responsibility is assumed for inaccuracies. Furthermore, such information does not convey to the purchaser of the semiconductor devices described any license under the patent rights of
Elmos Semiconductor AG or others.
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PRODUCTION DATA – Mar 7, 2016
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© Elmos Semiconductor AG, 2016. Reproduction, in part or whole, without the prior written consent of Elmos Semiconductor AG, is prohibited.
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