TI CDCLVP1212 12 lvpecl output, high-performance clock buffer Datasheet

CDCLVP1212
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SCAS886A – AUGUST 2009 – REVISED MAY 2010
12 LVPECL Output, High-Performance Clock Buffer
Check for Samples: CDCLVP1212
FEATURES
DESCRIPTION
•
•
•
The CDCLVP1212 is a highly versatile, low additive
jitter buffer that can generate 12 copies of LVPECL
clock outputs from one of two selectable LVPECL,
LVDS, or LVCMOS inputs for a variety of
communication applications. It has a maximum clock
frequency up to 2 GHz. The CDCLVP1212 features
an on-chip multiplexer (MUX) for selecting one of two
inputs that can be easily configured solely through a
control pin. The overall additive jitter performance is
less than 0.1 ps, RMS from 10 kHz to 20 MHz, and
overall output skew is as low as 25 ps, making the
device a perfect choice for use in demanding
applications.
1
2
•
•
•
•
•
•
•
•
•
•
•
2:12 Differential Buffer
Selectable Clock Inputs Through Control Pin
Universal Inputs Accept LVPECL, LVDS, and
LVCMOS/LVTTL
12 LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 88 mA
Very Low Additive Jitter: <100 fs,rms in 10-kHz
to 20-MHz Offset Range
2.375-V to 3.6-V Device Power Supply
Maximum Propagation Delay: 550 ps
Maximum Output Skew: 25 ps
LVPECL Reference Voltage, VAC_REF, Available
for Capacitive-Coupled Inputs
Industrial Temperature Range: –40°C to +85°C
ESD Protection Exceeds 2 kV (HBM)
Available in 6-mm × 6-mm QFN-40 (RHA)
Package
The CDCLVP1212 clock buffer distributes one of two
selectable clock inputs (IN0, IN1) to 12 pairs of
differential LVPECL clock outputs (OUT0, OUT11)
with minimum skew for clock distribution. The
CDCLVP1212 can accept two clock sources into an
input multiplexer. The inputs can be LVPECL, LVDS,
or LVCMOS/LVTTL.
The CDCLVP1212 is specifically designed for driving
50-Ω transmission lines. When driving the inputs in
single-ended mode, the LVPECL bias voltage
(VAC_REF) should be applied to the unused negative
input pin. However, for high-speed performance up to
2 GHz, differential mode is strongly recommended.
APPLICATIONS
•
•
•
•
Wireless Communications
Telecommunications/Networking
Medical Imaging
Test and Measurement Equipment
The CDCLVP1212 is packaged in a small 40-pin,
6-mm x 6-mm QFN package and is characterized for
operation from –40°C to +85°C.
VCC
VCC
VCC
VCC
VCC
VCC
INP0
INP1
IN_MUX
INN0
LVPECL
12
12
OUTP[11...0]
OUTN[11...0]
INN1
IN_SEL
VAC_REF
Reference
Generator
GND
GND
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
CDCLVP1212
SCAS886A – AUGUST 2009 – REVISED MAY 2010
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
AVAILABLE OPTIONS (1)
TA
PACKAGED DEVICES
FEATURES
CDCLVP1212RHAT
40-pin QFN (RHA) package, small tape and reel
CDCLVP1212RHAR
40-pin QFN (RHA) package, tape and reel
–40°C to +85°C
(1)
For the most current specifications and package information, see the Package Option Addendum located at the end of this data sheet or
refer to our web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
Over operating free-air temperature range (unless otherwise noted).
VCC
Supply voltage range (2)
VIN
Input voltage range
(3)
(3)
CDCLVP1212
UNIT
–0.5 to 4.6
V
–0.5 to VCC +0.5
V
VOUT
Output voltage range
–0.5 to VCC+0.5
V
IIN
Input current
20
mA
IOUT
Output current
50
mA
TA
Specified free-air temperature range (no airflow)
–40 to +85
°C
TSTG
Storage temperature range
–65 to +150
°C
TJ
Maximum junction temperature
+125
°C
ESD
Electrostatic discharge (HBM)
2
kV
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
All supply voltages must be supplied simultaneously.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Over operating free-air temperature range (unless otherwise noted).
CDCLVP1212
PARAMETER
VCC
Supply voltage
TA
Ambient temperature
MIN
TYP
MAX
2.375
2.50/3.30
3.60
V
+85
°C
–40
PACKAGE DISSIPATION RATINGS (1)
UNIT
(2)
VALUE
PARAMETER
Thermal resistance, junction-to-ambient
qJA
qJP
(1)
(2)
(3)
2
(3)
TEST
CONDITIONS
4 × 4 VIAS
ON PAD
UNIT
0 LFM
36.1
°C/W
150 LFM
30.2
°C/W
400 LFM
28.2
°C/W
3.58
°C/W
Thermal resistance, junction-to-pad
The package thermal resistance is calculated in accordance with JESD 51 and JEDEC 2S2P (high-K board).
Connected to GND with 16 thermal vias (0.3-mm diameter).
qJP (junction-to-pad) is used for the QFN package, because the primary heat flow is from the junction to the GND pad of the QFN
package.
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ELECTRICAL CHARACTERISTICS: LVCMOS Input (1)
At VCC = 2.375 V to 3.6 V and TA = –40°C to +85°C (unless otherwise noted).
CDCLVP1212
PARAMETER
fIN
TEST CONDITIONS
TYP
MAX
UNIT
200
MHz
1.1
1.8
V
Vth + 0.1
VCC
V
0
Vth – 0.1
V
40
mA
Input frequency
External threshold voltage applied to
complementary input
Vth
Input threshold voltage
VIH
Input high voltage
VIL
Input high voltage
IIH
Input high current
VCC = 3.6 V, VIH = 3.6 V
IIL
Input low current
VCC = 3.6 V, VIL = 0 V
ΔV/ΔT
Input edge rate
ICAP
Input capacitance
(1)
MIN
20% to 80%
–40
1.5
mA
V/ns
5
pF
Figure 3 and Figure 4 show dc test setup.
ELECTRICAL CHARACTERISTICS: Differential Input (1)
At VCC = 2.375 V to 3.6 V and TA = –40°C to +85°C (unless otherwise noted).
CDCLVP1212
PARAMETER
fIN
Input frequency
TEST CONDITIONS
TYP
Clock input
fIN ≤ 1.5 GHz
0.1
1.5 GHz ≤ fIN ≤ 2 GHz
VIN, DIFF, PP
Differential input peak-peak voltage
VICM
Input common-mode level
IIH
Input high current
VCC = 3.6 V, VIH = 3.6 V
IIL
Input low current
VCC = 3.6 V, VIL = 0 V
ΔV/ΔT
Input edge rate
ICAP
Input capacitance
(1)
MIN
20% to 80%
MAX
UNIT
2000
MHz
1.5
V
0.2
1.5
V
1.0
VCC – 0.3
V
40
mA
–40
1.5
mA
V/ns
5
pF
Figure 5 and Figure 6 show dc test setup. Figure 7 shows ac test setup.
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ELECTRICAL CHARACTERISTICS: LVPECL Output (1)
At VCC = 2.375 V to 2.625 V and TA = –40°C to +85°C (unless otherwise noted).
CDCLVP1212
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
Output high voltage
VCC – 1.26
VCC – 0.9
V
VOL
Output low voltage
VCC – 1.7
VCC – 1.3
V
VOUT, DIFF, PP
Differential output peak-peak voltage
0.5
1.35
V
VAC_REF
Input bias voltage
VCC – 1.6
tPD
Propagation delay
tSK,PP
Part-to-part skew
tSK,O
Output skew
tSK,P
tRJIT
Output rise/fall time
Supply internal current
ICC
Output and internal supply current
VCC – 1.1
V
VIN, DIFF, PP = 0.1V
550
ps
VIN, DIFF, PP = 0.3V
550
ps
150
ps
25
ps
50
ps
Crossing-point-to-crossing-point distortion,
fOUT = 100 MHz
Random additive jitter (with 50% duty
cycle input)
IEE
4
IAC_REF = 2 mA
Pulse skew (with 50% duty cycle input)
tR/tF
(1)
fIN ≤ 2 GHz
–50
fOUT = 100 MHz, VIN,SE = VCC, Vth = 1.25 V,
10 kHz to 20 MHz
0.11
ps, RMS
fOUT = 100 MHz, VIN,SE = 0.9 V,
Vth = 1.1 V, 10 kHz to 20 MHz
0.128
ps, RMS
fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V,
VICM = 1 V, 10 kHz to 20 MHz
0.053
ps, RMS
fOUT = 100 MHz, VIN,DIFF,PP = 0.15 V,
VICM = 1 V, 10 kHz to 20 MHz
0.093
ps, RMS
fOUT = 100 MHz, VIN,DIFF,PP = 1 V,
VICM = 1 V, 10 kHz to 20 MHz
0.092
ps, RMS
20% to 80%
200
ps
Outputs unterminated
88
mA
All outputs terminated, 50 Ω to VCC – 2
468
mA
Figure 8 and Figure 9 show dc and ac test setup.
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ELECTRICAL CHARACTERISTICS: LVPECL Output (1)
At VCC = 3.0 V to 3.6 V and TA = –40°C to +85°C (unless otherwise noted).
CDCLVP1212
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
Output high voltage
VCC – 1.26
VCC – 0.9
V
VOL
Output low voltage
VCC – 1.7
VCC – 1.3
V
VOUT, DIFF, PP
Differential output peak-peak voltage
0.65
1.35
V
VAC_REF
Input bias voltage
VCC – 1.6
tPD
Propagation delay
tSK,PP
Part-to-part skew
tSK,O
Output skew
tSK,P
tRJIT
IAC_REF = 2 mA
Random additive jitter (with 50% duty
cycle input)
Output rise/fall time
IEE
Supply internal current
ICC
Output and internal supply current
VCC – 1.1
V
VIN, DIFF, PP = 0.1V
550
ps
VIN, DIFF, PP = 0.3V
550
ps
150
ps
25
ps
50
ps
Crossing-point-to-crossing-point distortion,
fOUT = 100 MHz
Pulse skew (with 50% duty cycle input)
tR/tF
(1)
fIN ≤ 2 GHz
–50
fOUT = 100 MHz, VIN,SE = VCC, Vth = 1.65 V,
10 kHz to 20 MHz
0.101
ps, RMS
fOUT = 100 MHz, VIN,SE = 0.9 V,
Vth = 1.1 V, 10 kHz to 20 MHz
0.130
ps, RMS
fOUT = 2 GHz, VIN,DIFF,PP = 0.2 V,
VICM = 1 V, 10 kHz to 20 MHz
0.069
ps, RMS
fOUT = 100 MHz, VIN,DIFF,PP = 0.15 V,
VICM = 1 V, 10 kHz to 20 MHz
0.094
ps, RMS
fOUT = 100 MHz, VIN,DIFF,PP = 1 V,
VICM = 1 V, 10 kHz to 20 MHz
0.094
ps, RMS
20% to 80%
200
ps
Outputs unterminated
88
mA
All outputs terminated, 50 Ω to VCC – 2
468
mA
Figure 8 and Figure 9 show dc and ac test setup.
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PIN CONFIGURATION
OUTN7
OUTP7
OUTN6
OUTP6
OUTN5
OUTP5
OUTN4
OUTP4
GND
29
28
27
26
25
24
23
22
21
31
20
VCC
OUTP8
32
19
OUTN3
OUTN8
33
18
OUTP3
17
OUTN2
OUTP2
CDCLVP1212
34
OUTN9
35
16
OUTP10
36
15
OUTN1
OUTN10
37
14
OUTP1
13
OUTN0
Thermal Pad
(1)
4
5
6
7
8
9
10
VCC
VCC
VAC_REF
INN0
INP0
NC
VCC
NC
40
3
OUTP0
11
INN1
12
2
39
INP1
OUTN11
1
38
IN_SEL
OUTP11
VCC
6
GND
VCC
OUTP9
(1)
30
RHA PACKAGE
QFN-40
(TOP VIEW)
Thermal pad must be soldered to ground.
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PIN DESCRIPTIONS
CDCLVP1212 Pin Descriptions
TERMINAL
NAME
TERMINAL
NO.
TYPE
PULL-UP/
PULLDOWN
VCC
5, 6, 11, 20,
31, 40
Power
—
2.5-V/3.3-V supplies for the device
GND
21, 30
Ground
—
Device grounds
INP0, INN0
9, 8
Input
—
Differential input pair or single-ended input. Unused input pair can be left floating.
INP1, INN1
2, 3
Input
—
Redundant differential input pair or single-ended input. Unused input pair can be
left floating.
OUTP11,
OUTN11
38, 39
Output
—
Differential LVPECL output pair no. 11. Unused output pair can be left floating.
OUTP10,
OUTN10
36, 37
Output
—
Differential LVPECL output pair no. 10. Unused output pair can be left floating.
OUTP9,
OUTN9
34, 35
Output
—
Differential LVPECL output pair no. 9. Unused output pair can be left floating.
OUTP8,
OUTN8
32, 33
Output
—
Differential LVPECL output pair no. 8. Unused output pair can be left floating.
OUTP7,
OUTN7
28, 29
Output
—
Differential LVPECL output pair no. 7. Unused output pair can be left floating.
OUTP6,
OUTN6
26, 27
Output
—
Differential LVPECL output pair no. 6. Unused output pair can be left floating.
OUTP5,
OUTN5
24, 25
Output
—
Differential LVPECL output pair no. 5. Unused output pair can be left floating.
OUTP4,
OUTN4
22, 23
Output
—
Differential LVPECL output pair no. 4. Unused output pair can be left floating.
OUTP3,
OUTN3
18, 19
Output
—
Differential LVPECL output pair no. 3. Unused output pair can be left floating.
OUTP2,
OUTN2
16, 17
Output
—
Differential LVPECL output pair no. 2. Unused output pair can be left floating.
OUTP1,
OUTN1
14, 15
Output
—
Differential LVPECL output pair no. 1. Unused output pair can be left floating.
OUTP0
OUTN0
12, 13
Output
—
Differential LVPECL output pair no. 0. Unused output pair can be left floating.
IN_SEL
1
Input
VAC_REF
7
Output
—
Bias voltage output for capacitive coupled inputs. If used, it is recommended to
use a 0.1-mF capacitor to GND on this pin. The output current is limited to 2 mA.
NC
4, 10
—
—
Do not connect
DESCRIPTION
Pulldown
MUX select input for input choice (see Table 2)
(see Table 1)
Table 1. Pin Characteristics
PARAMETER
RPULLDOWN
MIN
TYP
Input pulldown resistor
150
MAX
UNITS
kΩ
Table 2. Input Selection Table
IN_SEL
ACTIVE CLOCK INPUT
0
INP0, INN0
1
INP1, INN1
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TYPICAL CHARACTERISTICS
At TA = –40°C to +85°C (unless otherwise noted).
Differential Output Peak-to-Peak Voltage (V)
DIFFERENTIAL OUTPUT PEAK-TO-PEAK VOLTAGE
vs FREQUENCY
1.0
VCC = 2.375 V
TA = -40°C to +85°C
VICM = 1 V
VIN,DIFF,PP = Min
0.9
0.8
0.7
0.6
0.5
0.4
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Frequency (GHz)
Figure 1.
Differential Output Peak-to-Peak Voltage (V)
DIFFERENTIAL OUTPUT PEAK-TO-PEAK VOLTAGE
vs FREQUENCY
1.1
1.2
1.3
1.0
0.9
0.8
0.7
VCC = 3.0 V
TA = -40°C to +85°C
VICM = 1 V
VIN,DIFF,PP = Min
0.6
0.5
0.4
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Frequency (GHz)
Figure 2.
8
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TEST CONFIGURATIONS
This section describes the function of each block for the CDCLVP1212. Figure 3 through Figure 9 illustrate how
the device should be set up for a variety of test configurations.
IN
VIH
Vth
VIL
IN
Vth
Figure 3. DC-Coupled LVCMOS Input During Device Test
VCC
VIHmax
Vthmax
VILmax
VIH
Vth
Vth
VIL
VIHmin
Vthmin
VILmin
GND
Figure 4. Vth Variation over LVCMOS Levels
VCC
VCC
130 W
130 W
CDCLVP1212
LVPECL
82 W
82 W
Figure 5. DC-Coupled LVPECL Input During Device Test
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100 W
LVDS
CDCLVP1212
Figure 6. DC-Coupled LVDS Input During Device Test
VCC
VCC
82 W
82 W
CDCLVP1212
Differential
130 W
130 W
Figure 7. AC-Coupled Differential Input to Device
Oscilloscope
LVPECL
50 W
50 W
VCC - 2 V
Figure 8. LVPECL Output DC Configuration During Device Test
Phase Noise
Analyzer
LVPECL
150 W
150 W
50 W
Figure 9. LVPECL Output AC Configuration During Device Test
10
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Figure 10 shows the output voltage and rise/fall time. Output and part-to-part skew are shown in Figure 11.
VOH
OUTNx
VOD
VOL
OUTPx
80%
VOUT,DIFF,PP (= 2 ´ VOD)
20%
0V
tR
tF
Figure 10. Output Voltage and Rise/Fall Time
INNx
INPx
tPLH0
tPLH0
tPLH1
tPLH1
OUTN0
OUTP0
OUTN1
OUTP1
tPLH2
tPLH2
OUTN2
OUTP2
tPLH11
tPLH11
OUTN11
OUTP11
(1)
Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn
(n = 0, 1, 2....11), or as the difference between the fastest and the slowest tPHLn (n = 0, 1, 2....11).
(2)
Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest
tPLHn (n = 0, 1, 2....11) across multiple devices, or the difference between the fastest and the slowest tPHLn (n = 0, 1,
2....11) across multiple devices.
Figure 11. Output and Part-to-Part Skew
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APPLICATION INFORMATION
Thermal Management
Power consumption of the CDCLVP1212 can be high enough to require attention to thermal management. For
reliability and performance reasons, the die temperature should be limited to a maximum of +125°C. That is, as
an estimate, ambient temperature (TA) plus device power consumption times qJA should not exceed +125°C.
The device package has an exposed pad that provides the primary heat removal path to the printed circuit board
(PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a
ground plane must be incorporated into the PCB within the footprint of the package. The exposed pad must be
soldered down to ensure adequate heat conduction out of the package. Figure 12 shows a recommended land
and via pattern.
4,0 mm (min)
0,33 mm (typ)
1,0 mm (typ)
Figure 12. Recommended PCB Layout
Power-Supply Filtering
High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the
additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when
jitter/phase noise is very critical to applications.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system
against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required
by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors,
they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It
is recommended to add as many high-frequency (for example, 0.1-mF) bypass capacitors as there are supply
pins in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply
and the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these
beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with
very low dc resistance because it is imperative to provide adequate isolation between the board supply and the
chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required
for proper operation.
12
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Figure 13 illustrates this recommended power-supply decoupling method.
VCC
Board
Supply
Chip
Supply
Ferrite Bead
C
10 mF
C
1 mF
C
0.1 mF (x6)
Figure 13. Power-Supply Decoupling
LVPECL Output Termination
The CDCLVP1212 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination are
required to ensure correct operation of the device and to minimize signal integrity. The proper termination for
LVPECL outputs is a 50 Ω to (VCC –2) V, but this dc voltage is not readily available on PCB. Therefore, a
Thevenin equivalent circuit is worked out for the LVPECL termination in both direct-coupled (dc) and ac-coupled
configurations. These configurations are shown in Figure 14a and b for VCC = 2.5 V and Figure 15a and b for VCC
= 3.3 V, respectively. It is recommended to place all resistive components close to either the driver end or the
receiver end. If the supply voltage for the driver and receiver is different, ac coupling is required.
VCC
VCC
105 W
105 W
CDCLVP1212
LVPECL
96 W
96 W
(a) Output DC Termination
VBB
CDCLVP1212
LVPECL
86 W
86 W
50 W
50 W
(b) Output AC Termination
Figure 14. LVPECL Output DC and AC Termination for VCC = 2.5 V
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VCC
VCC
130 W
130 W
CDCLVP1212
LVPECL
82 W
82 W
(a) Output DC Termination
VBB
CDCLVP1212
150 W
LVPECL
150 W
50 W
50 W
(b) Output AC Termination
Figure 15. LVPECL Output DC and AC Termination for VCC = 3.3 V
Input Termination
The CDCLVP1212 inputs can be interfaced with LVPECL, LVDS, or LVCMOS drivers. Figure 16 illustrates how
to dc couple an LVCMOS input to the CDCLVP1212. The series resistance (RS) should be placed close to the
LVCMOS driver; its value is calculated as the difference between the transmission line impedance and the driver
output impedance.
VIH
Vth
VIL
RS
LVCMOS
CDCLVP1212
Vth =
VIH + VIL
2
Figure 16. DC-Coupled LVCMOS Input to CDCLVP1212
14
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Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCLVP1212
CDCLVP1212
www.ti.com
SCAS886A – AUGUST 2009 – REVISED MAY 2010
Figure 17 shows how to dc couple LVDS inputs to the CDCLVP1212. Figure 18 and Figure 19 describe the
method of dc coupling LVPECL inputs to the CDCLVP1212 for VCC = 2.5 V and VCC = 3.3 V, respectively.
100 W
LVDS
CDCLVP1212
Figure 17. DC-Coupled LVDS Inputs to CDCLVP1212
VCC
VCC
105 W
105 W
CDCLVP1212
LVPECL
96 W
96 W
Figure 18. DC-Coupled LVPECL Inputs to CDCLVP1212 (VCC = 2.5 V)
VCC
VCC
130 W
130 W
CDCLVP1212
LVPECL
82 W
82 W
Figure 19. DC-Coupled LVPECL Inputs to CDCLVP1212 (VCC = 3.3 V)
Submit Documentation Feedback
Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCLVP1212
15
CDCLVP1212
SCAS886A – AUGUST 2009 – REVISED MAY 2010
www.ti.com
Figure 20 and Figure 21 show the technique of ac coupling differential inputs to the CDCLVP1212 for VCC =
2.5–V and VCC = 3.3 V, respectively. It is recommended to place all resistive components close to either the
driver end or the receiver end. If the supply voltages of the driver and receiver are different, ac coupling is
required.
VCC
VCC
96 W
96 W
CDCLVP1212
Differential
105 W
105 W
Figure 20. AC-Coupled Differential Inputs to CDCLVP1212 (VCC = 2.5 V)
VCC
VCC
82 W
82 W
CDCLVP1212
Differential
130 W
130 W
Figure 21. AC-Coupled Differential Inputs to CDCLVP1212 (VCC = 3.3 V)
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (August, 2009) to Revision A
Page
•
Corrected package designators in orderable device names in Available Options table ...................................................... 2
•
Changed description of INP1, INP0 and INN1, INN0 pins in Pin Descriptions table ............................................................ 7
•
Changed descriptions of all output pins in Pin Descriptions table ........................................................................................ 7
16
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Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): CDCLVP1212
PACKAGE OPTION ADDENDUM
www.ti.com
19-May-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CDCLVP1212RHAR
ACTIVE
VQFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
CDCLVP1212RHAT
ACTIVE
VQFN
RHA
40
250
CU NIPDAU
Level-3-260C-168 HR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-May-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CDCLVP1212RHAR
VQFN
RHA
40
2500
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
CDCLVP1212RHAT
VQFN
RHA
40
250
330.0
16.4
6.3
6.3
1.5
12.0
16.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-May-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CDCLVP1212RHAR
VQFN
RHA
40
2500
333.2
345.9
28.6
CDCLVP1212RHAT
VQFN
RHA
40
250
333.2
345.9
28.6
Pack Materials-Page 2
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