TI MSP430F23X0 Mixed signal microcontroller Datasheet

MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
D Low Supply-Voltage Range, 1.8 V to 3.6 V
D Ultralow-Power Consumption:
D
D
D
D
D
D
D
-- Active Mode: 270 μA at 1 MHz, 2.2 V
-- Standby Mode: 0.7 μA
-- Off Mode (RAM Retention): 0.1 μA
Ultrafast Wake-Up From Standby Mode in
Less Than 1 μs
16-Bit RISC Architecture,
62.5 ns Instruction Cycle Time
Hardware Multiplier
Basic Clock Module Configurations:
-- Internal Frequencies up to 16MHz With
Four Calibrated Frequencies to ±1%
-- Internal Very Low Power LF Oscillator
-- 32-kHz Crystal
-- High-Frequency Crystal up to 16 MHz
-- Resonator
-- External Digital Clock Source
-- External Resistor
16-Bit Timer_A With Three
Capture/Compare Registers
16-Bit Timer_B With Three
Capture/Compare Registers
On-Chip Comparator for Analog Signal
Compare Function or Slope A/D
Conversion
D Universal Serial Communication Interface
D
D
D
D
D
D
D
-- Enhanced UART Supporting Auto
Baudrate Detection (LIN)
-- IrDA Encoder and Decoder
-- Synchronous SPI
-- I2Ct
Brownout Detector
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by
Security Fuse
Bootstrap Loader in Flash Devices
On-Chip Emulation Module
Family Members Include:
MSP430F2330
8KB + 256B Flash Memory
1KB RAM
MSP430F2350
16KB + 256B Flash Memory
2KB RAM
MSP430F2370
32KB + 256B Flash Memory
2KB RAM
Available in 40-pin QFN Package
For Complete Module Descriptions, See the
MSP430x2xx Family User’s Guide
description
The Texas Instruments MSP430 family of ultralow-power microcontrollers consists of several devices featuring
different sets of peripherals targeted for various applications. The architecture, combined with five low-power
modes is optimized to achieve extended battery life in portable measurement applications. The devices feature
a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code
efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less
than 1 μs.
The MSP430F23x0 series is an ultralow-power microcontroller with two built-in 16-bit timers, one universal
serial communication interface (USCI), a versatile analog comparator, and 32 I/O pins.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range
from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage
because very small parametric changes could cause the device not to meet its published specifications. These devices have limited
built-in ESD protection.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2007, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
PLASTIC 40-PIN QFN
(RHA)
--40°C to 85°C
--40°C to 105°C
MSP430F2330IRHA
MSP430F2350IRHA
MSP430F2370IRHA
MSP430F2330TRHA
MSP430F2350TRHA
MSP430F2370TRHA
AVCC
D/AVSS
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
P4.7/TBCLK
P4.6/TBOUTH/ACLK
P4.5/TB2
pin designation, MSP430F23x0
P4.4/TB1
P4.3/TB0
P4.2/TB2
P1.0/TACLK
P1.1/TA0
4
5
27
26
P4.1/TB1
P4.0/TB0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
6
7
8
25
24
23
P3.7
P3.6
P3.5/UCA0RXD/UCA0SOMI
9
22
10
21
11 12 13 14 15 16 17 18 19 20
P3.4/UCA0TXD/UCA0SIMO
P3.3/UCB0CLK/UCA0STE
P1.7/TA2
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
P2.5/ROSC/CA5
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P1.5/TA0
P1.6/TA1
RHA PACKAGE
(TOP VIEW)
2
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P3.2/UCB0SOMI/UCB0SCL
40 39 38 37 36 35 34 33 32 31
1
30
2
29
3
28
DVCC
XIN/P2.6/CA6
XOUT/P2.7/CA7
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
functional block diagram
MSP430F23x0
XIN
XOUT
DVCC
D/AVSS
AVCC
P1.x/P2.x
2x8
P3.x/P4.x
2x8
ACLK
Basic Clock
System+ SMCLK
Flash
RAM
32kB
16kB
8kB
2kB
2kB
1kB
MCLK
16MHz
CPU
MAB
incl. 16
Registers
MDB
Hardware
Multiplier
Emulation
JTAG
Interface
Brownout
Protection
MPY,
MPYS,
MAC,
MACS
Ports
P1/P2
2x8 I/O
Interrupt
capability
Watchdog
WDT+
15-Bit
Ports
P3/P4
2x8 I/O
Timer_A3
Timer_B3
Comp_A+
3 CC
Registers
3 CC
Registers
8
Channels
USCI A0:
UART
IrDA, SPI
USCI B0:
SPI, I2C
RST/NMI
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
Terminal Functions, MSP430F23x0
TERMINAL
NAME
NO
DESCRIPTION
I/O
DVCC
1
XIN/P2.6/CA6
2
I/O
Input terminal of crystal oscillator/general-purpose digital I/O pin/Comparator_A input
XOUT/P2.7/CA7
3
I/O
Output terminal of crystal oscillator/general-purpose digital I/O pin/Comparator_A input
P1.0/TACLK
4
I/O
General-purpose digital I/O pin/Timer_A, clock signal TACLK input
P1.1/TA0
5
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI0A input, compare: Out0 output
P1.2/TA1
6
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI1A input, compare: Out1 output
P1.3/TA2
7
I/O
General-purpose digital I/O pin/Timer_A, capture: CCI2A input, compare: Out2 output
P1.4/SMCLK
8
I/O
General-purpose digital I/O pin/SMCLK signal output
P1.5/TA0
9
I/O
General-purpose digital I/O pin/Timer_A, compare: Out0 output
P1.6/TA1
10
I/O
General-purpose digital I/O pin/Timer_A, compare: Out1 output
P1.7/TA2
11
I/O
General-purpose digital I/O pin/Timer_A, compare: Out2 output
P2.0/ACLK/CA2
12
I/O
General-purpose digital I/O pin/ACLK output/Comparator_A input
P2.1/TAINCLK/CA3
13
I/O
General-purpose digital I/O pin/Timer_A, clock signal at INCLK/Comparator_A input
P2.2/CAOUT/TA0/CA4
14
I/O
General-purpose digital I/O pin/Comparator_A output/Timer_A, capture: CCI0B input/Comparator_A
input
P2.3/CA0/TA1
15
I/O
General-purpose digital I/O pin/Comparator_A input/Timer_A, compare: Out1 output
P2.4/CA1/TA2
16
I/O
General-purpose digital I/O pin/Comparator_A input/Timer_A, compare: Out2 output
P2.5/ROSC/CA5
17
I/O
General-purpose digital I/O
frequency/Comparator_A input
P3.0/UCB0STE/
UCA0CLK
18
I/O
General-purpose digital I/O pin/USCIB0 slave transmit enable/USCIA0 clock input/output
P3.1/UCB0SIMO/
UCB0SDA
19
I/O
General-purpose digital I/O pin/USCIB0 slave in/master out in SPI mode, SDA I2C data in I2C mode
P3.2/UCB0SOMI/
UCB0SCL
20
I/O
General-purpose digital I/O pin/USCIB0 slave out/master in in SPI mode, SCL I2C clock in I2C mode
P3.3/UCB0CLK/
UCA0STE
21
I/O
General-purpose digital I/O/USCIB0 clock input/output, USCIA0 slave transmit enable
P3.4/UCA0TXD/
UCA0SIMO
22
I/O
General-purpose digital I/O pin/USCIA0 transmit data output in UART mode, slave data in/master out in
SPI mode
P3.5/UCA0RXD/
UCA0SOMI
23
I/O
General-purpose digital I/O pin/USCIA0 receive data input in UART mode, slave data out/master in in
SPI mode
P3.6
24
I/O
General-purpose digital I/O pin
P3.7
25
I/O
General-purpose digital I/O pin
P4.0/TB0
26
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI0A input, compare: Out0 output
P4.1/TB1
27
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI1A input, compare: Out1 output
P4.2/TB2
28
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI2A input, compare: Out2 output
P4.3/TB0
29
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI0B input, compare: Out0 output
P4.4/TB1
30
I/O
General-purpose digital I/O pin/Timer_B, capture: CCI1B input, compare: Out1 output
P4.5/TB2
31
I/O
General-purpose digital I/O pin/Timer_B, compare: Out2 output
P4.6/TBOUTH/ACLK
32
I/O
General-purpose digital I/O pin/switch all PWM digital outputs to high impedance -- Timer_B3: TB0 to
TB2/ACLK output
P4.7/TBCLK
33
I/O
General-purpose digital I/O pin/input clock TBCLK -- Timer_B3
TDO/TDI
34
I/O
Test data output port. TDO/TDI data output or programming data input terminal
TDI/TCLK
35
I
Test data input or test clock input. The device protection fuse is connected to TDI/TCLK.
TMS
36
I
Test mode select. TMS is used as an input port for device programming and test.
4
Digital supply voltage, positive terminal. Supplies all digital parts.
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resistor
defining
the
DCO
nominal
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
Terminal Functions (Continued)
TERMINAL
NAME
DESCRIPTION
NO
I/O
TCK
37
I
Test clock. TCK is the clock input port for device programming and test.
RST/NMI
38
I
Reset input, nonmaskable interrupt input port
D/AVSS
39
AVCC
40
QFN Pad
NA
Digital/Analog supply voltage, negative terminal
Analog supply voltage, positive terminal
NA
QFN package pad connection to D/AVSS recommended
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
short-form description
CPU
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions,
are performed as register operations in conjunction with seven addressing modes for source
operand and four addressing modes for destination operand.
Program Counter
PC/R0
Stack Pointer
SP/R1
SR/CG1/R2
Status Register
Constant Generator
The CPU is integrated with 16 registers that
provide reduced instruction execution time. The
register-to-register operation execution time is
one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register,
and constant generator respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses, and can be handled
with all instructions.
instruction set
The instruction set consists of 51 instructions with
three formats and seven address modes. Each
instruction can operate on word and byte data.
Table 1 shows examples of the three types of
instruction formats; the address modes are listed
in Table 2.
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
Table 1. Instruction Word Formats
Dual operands, source-destination
e.g. ADD R4,R5
R4 + R5 ------> R5
Single operands, destination only
e.g. CALL
PC ---->(TOS), R8----> PC
Relative jump, un/conditional
e.g. JNE
R8
Jump-on-equal bit = 0
Table 2. Address Mode Descriptions
ADDRESS MODE
S D
Register
F F
MOV Rs,Rd
MOV R10,R11
Indexed
F F
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
Symbolic (PC relative)
F F
MOV EDE,TONI
M(EDE) ----> M(TONI)
Absolute
F F
MOV &MEM,&TCDAT
M(MEM) ----> M(TCDAT)
EXAMPLE
OPERATION
R10
----> R11
M(2+R5)----> M(6+R6)
Indirect
F
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) ----> M(Tab+R6)
Indirect
autoincrement
F
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) ----> R11
R10 + 2----> R10
F
MOV #X,TONI
MOV #45,TONI
Immediate
NOTE : S = source
6
SYNTAX
D = destination
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#45
----> M(TONI)
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
operating modes
The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt
event can wake up the device from any of the five low-power modes, service the request and restore back to
the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
D Active mode (AM)
--
All clocks are active
D Low-power mode 0 (LPM0)
--
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
D Low-power mode 1 (LPM1)
--
CPU is disabled
ACLK and SMCLK remain active, MCLK is disabled
DCO’s dc-generator is disabled if DCO not used in active mode
D Low-power mode 2 (LPM2)
--
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator remains enabled
ACLK remains active
D Low-power mode 3 (LPM3)
--
CPU is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
ACLK remains active
D Low-power mode 4 (LPM4)
--
CPU is disabled
ACLK is disabled
MCLK and SMCLK are disabled
DCO’s dc-generator is disabled
Crystal oscillator is stopped
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
interrupt vector addresses
The interrupt vectors and the power-up starting address are located in the address range 0xFFFF--0xFFC0. The
vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM INTERRUPT
WORD ADDRESS
PRIORITY
Power-up
External Reset
Watchdog
Flash key violation
PC out of range (see Note 1)
PORIFG
RSTIFG
WDTIFG
KEYV
(see Note 2)
Reset
0xFFFE
31, highest
NMI
Oscillator Fault
Flash memory access violation
NMIIFG
OFIFG
ACCVIFG
(see Notes 2 & 6)
(non)-maskable
(non)-maskable
(non)-maskable
0xFFFC
30
Timer_B3
TBCCR0 CCIFG (see Note 3)
maskable
0xFFFA
29
Timer_B3
TBCCR1 and TBCCR2,
CCIFGs, TBIFG
(see Notes 2 & 3)
maskable
0xFFF8
28
Comparator_A+
CAIFG
maskable
0xFFF6
27
Watchdog timer
WDTIFG
maskable
0xFFF4
26
Timer_A3
TACCR0 CCIFG (see Note 3)
maskable
0xFFF2
25
Timer_A3
TACCR1 CCIFG,
TACCR2 CCIFG,
TAIFG (see Notes 2 & 3)
maskable
0xFFF0
24
USCI_A0/USCI_B0 Receive
USCI_B0 I2C Status
UCA0RXIFG, UCB0RXIFG
(see Note 2 and 4)
maskable
0xFFEE
23
USCI_A0/USCI_B0 Transmit
USCI_B0 I2C Receive / Transmit
UCA0TXIFG, UCB0TXIFG
(see Note 2 and 5)
maskable
0xFFEC
22
0xFFEA
21
0xFFE8
20
maskable
0xFFE6
19
maskable
0xFFE4
18
0xFFE2
17
0xFFE0
16
I/O port P2 (eight flags)
I/O port P1 (eight flags)
P2IFG.0 to P2IFG.7
(see Notes 2 & 3)
P1IFG.0 to P1IFG.7
(see Notes 2 & 3)
(see Note 7)
0xFFDE
15
(see Note 8)
0xFFDC--0xFFC0
14--0, lowest
NOTES: 1.
2.
3.
4.
5.
6.
A reset is executed if the CPU tries to fetch instructions from within the module register memory address range (0x0000--0x01FF).
Multiple source flags.
Interrupt flags are located in the module.
In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.
In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.
Non-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot.
Non-maskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
7. This location is used as bootstrap loader security key (BSLSKEY).
A 0xAA55 at this location disables the BSL completely.
A zero (0h) disables the erasure of the flash if an invalid password is supplied.
8. The interrupt vectors at addresses 0xFFDC to 0xFFC0 are not used in this device and can be used for regular program code if
necessary.
8
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
special function registers
Most interrupt and module-enable bits are collected in the lowest address space. Special-function register bits
not allocated to a functional purpose are not physically present in the device. This arrangement provides simple
software access.
interrupt enable 1 and 2
Address
7
6
00h
5
4
ACCVIE
rw--0
3
2
1
0
NMIIE
OFIE
WDTIE
rw--0
rw--0
rw--0
WDTIE
Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog
Timer is configured in interval timer mode.
OFIE
Oscillator fault enable
NMIIE
(Non)maskable interrupt enable
ACCVIE
Flash access violation interrupt enable
Address
7
6
5
4
01h
UCA0RXIE
USCI_A0 receive-interrupt enable
UCA0TXIE
USCI_A0 transmit-interrupt enable
UCB0RXIE
USCI_B0 receive-interrupt enable
UCB0TXIE
USCI_B0 transmit-interrupt enable
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2
1
0
UCB0TXIE
UCB0RXIE
UCA0TXIE
UCA0RXIE
rw--0
rw--0
rw--0
rw--0
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
interrupt flag register 1 and 2
Address
7
6
5
02h
4
3
2
1
0
NMIIFG
RSTIFG
PORIFG
OFIFG
WDTIFG
rw--0
rw--(0)
rw--(1)
rw--1
rw--(0)
WDTIFG
Set on Watchdog Timer overflow (in watchdog mode) or security key violation.
Reset on VCC power-up or a reset condition at RST/NMI pin in reset mode.
OFIFG
Flag set on oscillator fault
RSTIFG
External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on
VCC power up
PORIFG
Power-on interrupt flag. Set on VCC power up.
NMIIFG
Set via RST/NMI pin
Address
7
6
5
03h
4
3
2
1
0
UCB0TX
IFG
UCB0RX
IFG
UCA0TX
IFG
UCA0RX
IFG
rw--0
rw--0
rw--0
rw--0
UCA0RXIFG USCI_A0 receive-interrupt flag
UCA0TXIFG USCI_A0 transmit-interrupt flag
UCB0RXIFG USCI_B0 receive-interrupt flag
UCB0TXIFG USCI_B0 transmit-interrupt flag
Legend
rw:
rw-0,1:
rw-(0,1):
Bit can be read and written.
Bit can be read and written. It is Reset or Set by PUC.
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device
10
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
memory organization
MSP430F2330
MSP430F2350
MSP430F2370
Memory
Main: interrupt vector
Main: code memory
Size
Flash
Flash
8KB Flash
0xFFFF -- 0xFFC0
0xFFFF -- 0xE000
16KB Flash
0xFFFF -- 0xFFC0
0xFFFF -- 0xC000
32KB
0xFFFF -- 0xFFC0
0xFFFF -- 0x8000
Information memory
Size
Flash
256 Byte
0x10FF -- 0x1000
256 Byte
0x10FF -- 0x1000
256 Byte
0x10FF -- 0x1000
Boot memory
Size
ROM
1KB
0x0FFF -- 0x0C00
1KB
0x0FFF -- 0x0C00
1KB
0x0FFF -- 0x0C00
Size
1KB Byte
0x5FF -- 0x0200
2KB Byte
0x9FF -- 0x0200
2KB
0x09FF -- 0x0200
16-bit
8-bit
8-bit SFR
0x01FF -- 0x0100
0x00FF -- 0x0010
0x000F -- 0x0000
0x01FF -- 0x0100
0x00FF -- 0x0010
0x000F -- 0x0000
0x01FF -- 0x0100
0x00FF -- 0x0010
0x000F -- 0x0000
RAM
Peripherals
bootstrap loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete
description of the features of the BSL and its implementation, see the Application report Features of the MSP430
Bootstrap Loader, Literature Number SLAA089.
BSL Function
RHA Package Pins
Data Transmit
5 -- P1.1
Data Receive
14 -- P2.2
flash memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
D Flash memory has n segments of main memory and four segments of information memory (A to D) of 64
bytes each. Each segment in main memory is 512 bytes in size.
D Segments 0 to n may be erased in one step, or each segment may be individually erased.
D Segments A to D can be erased individually, or as a group with segments 0--n.
Segments A to D are also called information memory.
D Segment A contains calibration data. After reset segment A is protected against programming or erasing.
It can be unlocked but care should be taken not to erase this segment if the calibration data is required.
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
peripherals
Peripherals are connected to the CPU through data, address, and control busses and can be handled using
all instructions. For complete module descriptions, refer to the MSP430x2xx Family User’s Guide.
oscillator and system clock
The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal
oscillator, an internal very low power, low frequency oscillator, an internal digitally-controlled oscillator (DCO)
and a high frequency crystal oscillator. The basic clock module is designed to meet the requirements of both
low system cost and low-power consumption. The internal DCO provides a fast turn-on clock source and
stabilizes in less than 1 μs. The basic clock module provides the following clock signals:
D Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal, a high frequency crystal or the internal very
D
D
low power LF oscillator.
Main clock (MCLK), the system clock used by the CPU.
Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.
The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.
DCO Calibration Data (provided from factory in flash info memory segment A)
DCO Frequency
Calibration Register
Size
Address
1 MHz
CALBC1_1MHZ
byte
0x10FF
CALDCO_1MHZ
byte
0x10FE
CALBC1_8MHZ
byte
0x10FD
CALDCO_8MHZ
byte
0x10FC
8 MHz
12 MHz
16 MHz
CALBC1_12MHZ
byte
0x10FB
CALDCO_12MHZ
byte
0x10FA
CALBC1_16MHZ
byte
0x10F9
CALDCO_16MHZ
byte
0x10F8
brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on
and power off.
digital I/O
There are 4 8-bit I/O ports implemented—ports P1 through P4:
D
D
D
D
D
All individual I/O bits are independently programmable.
Any combination of input, output, and interrupt conditions is possible.
Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
Read/write access to port-control registers is supported by all instructions.
Each I/O has an individually programmable pull--up/pull--down resistor.
The MSP430F23x0 devices provide 32 total port I/O pins available externally. Please see the device pinout for
more information.
watchdog timer +
The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a
software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog
function is not needed in an application, the module can be configured as an interval timer and can generate
interrupts at selected time intervals.
12
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
hardware multiplier
The multiplication operation is supported by a dedicated peripheral module. The module performs 16×16,
16×8, 8×16, and 8×8 bit operations. The module is capable of supporting signed and unsigned multiplication
as well as signed and unsigned multiply and accumulate operations. The result of an operation can be accessed
immediately after the operands have been loaded into the peripheral registers. No additional clock cycles are
required.
comparator_A+
The primary function of the comparator_A+ module is to support precision slope analog--to--digital conversions,
battery--voltage supervision, and monitoring of external analog signals.
timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_A3 Signal Connections
Input
Pin Number
Device
Input Signal
Module
Input Name
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
13 - P2.1
TAINCLK
INCLK
5 - P1.1
TA0
CCI0A
14 - P2.2
TA0
CCI0B
VSS
GND
Module
Block
Module
Output Signal
RHA
4 - P1.0
6 - P1.2
7 - P1.3
Output
Pin Number
RHA
Timer
NA
5 - P1.1
CCR0
TA0
9 -- P1.5
VCC
VCC
TA1
CCI1A
6 - P1.2
CAOUT (internal)
CCI1B
10 - P1.6
VSS
GND
VCC
VCC
TA2
CCI2A
ACLK (internal)
CCI2B
VSS
GND
VCC
VCC
CCR1
TA1
15 - P2.3
7 - P1.3
CCR2
POST OFFICE BOX 655303
TA2
• DALLAS, TEXAS 75265
11 - P1.7
16 - P2.4
13
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare
registers.
Timer_B3 Signal Connections
Input
Pin Number
Device
Input Signal
Module
Input Name
TBCLK
TBCLK
Module
Block
Module
Output Signal
RHA
33 - P4.7
RHA
ACLK
ACLK
SMCLK
SMCLK
TBCLK
INCLK
26 - P4.0
TB0
CCI0A
29 - P4.3
TB0
CCI0B
DVSS
GND
27 - P4.1
30 - P4.4
28 - P4.2
Output
Pin Number
DVCC
VCC
TB1
CCI1A
TB1
CCI1B
DVSS
GND
DVCC
VCC
TB2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
Timer
NA
26 - P4.0
CCR0
TB0
29 - P4.3
27 - P4.1
CCR1
TB1
30 - P4.4
28 - P4.2
CCR2
TB2
31 - P4.5
USCI
The universal serial communication interface (USCI) module is used for serial data communication. The USCI
module supports synchronous communication protocols like SPI (3 or 4 pin), I2C and asynchronous
communication protocols like UART, enhanced UART with automatic baudrate detection (LIN), and IrDA.
USCI A0 provides support for SPI (3 or 4 pin), UART, enhanced UART and IrDA.
USCI B0 provides support for SPI (3 or 4 pin) and I2C.
14
POST OFFICE BOX 655303
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MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
peripheral file map
PERIPHERALS WITH WORD ACCESS
Timer_B3
Capture/compare register
Capture/compare register
Capture/compare register
Timer_B register
Capture/compare control
Capture/compare control
Capture/compare control
Timer_B control
Timer_B interrupt vector
TBCCR2
TBCCR1
TBCCR0
TBR
TBCCTL2
TBCCTL1
TBCCTL0
TBCTL
TBIV
0x0196
0x0194
0x0192
0x0190
0x0186
0x0184
0x0182
0x0180
0x011E
Timer_A3
Capture/compare register
Capture/compare register
Capture/compare register
Timer_A register
Capture/compare control
Capture/compare control
Capture/compare control
Timer_A control
Timer_A interrupt vector
TACCR2
TACCR1
TACCR0
TAR
TACCTL2
TACCTL1
TACCTL0
TACTL
TAIV
0x0176
0x0174
0x0172
0x0170
0x0166
0x0164
0x0162
0x0160
0x012E
Flash Memory
Flash control 3
Flash control 2
Flash control 1
FCTL3
FCTL2
FCTL1
0x012C
0x012A
0x0128
Hardware Multiplier
Sum extend
Result high word
Result low word
Second operand
Multiply signed +accumulate/operand1
Multiply+accumulate/operand1
Multiply signed/operand1
Multiply unsigned/operand1
SUMEXT
RESHI
RESLO
OP2
MACS
MAC
MPYS
MPY
0x013E
0x013C
0x013A
0x0138
0x0136
0x0134
0x0132
0x0130
Watchdog Timer+
Watchdog/timer control
WDTCTL
0x0120
USCI_B0
USCI_B0 transmit buffer
USCI_B0 receive buffer
USCI_B0 status
USCI_B0 bit rate control 1
USCI_B0 bit rate control 0
USCI_B0 control 1
USCI_B0 control 0
USCI_B0 I2C slave address
USCI_B0 I2C own address
UCB0TXBUF
UCB0RXBUF
UCB0STAT
UCB0BR1
UCB0BR0
UCB0CTL1
UCB0CTL0
UCB0SA
UCB0OA
0x06F
0x06E
0x06D
0x06B
0x06A
0x069
0x068
0x011A
0x0118
USCI_A0
USCI_A0 transmit buffer
USCI_A0 receive buffer
USCI_A0 status
USCI_A0 modulation control
USCI_A0 baud rate control 1
USCI_A0 baud rate control 0
USCI_A0 control 1
USCI_A0 control 0
USCI_A0 IrDA receive control
USCI_A0 IrDA transmit control
USCI_A0 auto baud rate control
UCA0TXBUF
UCA0RXBUF
UCA0STAT
UCA0MCTL
UCA0BR1
UCA0BR0
UCA0CTL1
UCA0CTL0
UCA0IRRCTL
UCA0IRTCTL
UCA0ABCTL
0x0067
0x0066
0x0065
0x0064
0x0063
0x0062
0x0061
0x0060
0x005F
0x005E
0x005D
PERIPHERALS WITH BYTE ACCESS
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
PERIPHERALS WITH BYTE ACCESS (continued)
16
Basic Clock System+
Basic clock system control 3
Basic clock system control 2
Basic clock system control 1
DCO clock frequency control
BCSCTL3
BCSCTL2
BCSCTL1
DCOCTL
0x0053
0x0058
0x0057
0x0056
Port P4
Port P4 resistor enable
Port P4 selection
Port P4 direction
Port P4 output
Port P4 input
P4REN
P4SEL
P4DIR
P4OUT
P4IN
0x0011
0x001F
0x001E
0x001D
0x001C
Port P3
Port P3 resistor enable
Port P3 selection
Port P3 direction
Port P3 output
Port P3 input
P3REN
P3SEL
P3DIR
P3OUT
P3IN
0x0010
0x001B
0x001A
0x0019
0x0018
Port P2
Port P2 resistor enable
Port P2 selection
Port P2 interrupt enable
Port P2 interrupt edge select
Port P2 interrupt flag
Port P2 direction
Port P2 output
Port P2 input
P2REN
P2SEL
P2IE
P2IES
P2IFG
P2DIR
P2OUT
P2IN
0x002F
0x002E
0x002D
0x002C
0x002B
0x002A
0x0029
0x0028
Port P1
Port P1 resistor enable
Port P1 selection
Port P1 interrupt enable
Port P1 interrupt edge select
Port P1 interrupt flag
Port P1 direction
Port P1 output
Port P1 input
P1REN
P1SEL
P1IE
P1IES
P1IFG
P1DIR
P1OUT
P1IN
0x0027
0x0026
0x0025
0x0024
0x0023
0x0022
0x0021
0x0020
Special Function
SFR interrupt flag 2
SFR interrupt flag 1
SFR interrupt enable 2
SFR interrupt enable 1
IFG2
IFG1
IE2
IE1
0x0003
0x0002
0x0001
0x0000
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
absolute maximum ratings (see Note 1)
Voltage applied at VCC to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to + 4.1 V
Voltage applied to any pin (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --0.3 V to VCC+0.3 V
Diode current at any device terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±2 mA
Storage temperature (unprogrammed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . --55°C to 150°C
Storage temperature (programmed device, see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . --40°C to 105°C
NOTES: 1. Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended
operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
2. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage
is applied to the TDI/TCLK pin when blowing the JTAG fuse.
3. Higher temperature may be applied during board soldering process according to the current JEDEC J--STD--020 specification with
peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.
recommended operating conditions
PARAMETER
MIN
NOM
MAX
UNITS
Supply voltage during program execution, VCC
AVCC = DVCC = VCC (see Note 1)
1.8
3.6
V
Supply voltage during flash memory programming, VCC
AVCC = DVCC = VCC (see Note 1)
2.2
3.6
V
Supply voltage, VSS
AVSS = DVSS = VSS
0.0
0.0
V
I Version
--40
85
°C
T Version
--40
105
°C
VCC = 1.8 V,
Duty Cycle = 50% ±10%
dc
4.15
VCC = 2.7 V,
Duty Cycle = 50% ±10%
dc
12
VCC ≥ 3.3 V,
Duty Cycle = 50% ±10%
dc
16
Operating free-air
free air temperature range,
range TA
Processor frequency fSYSYTEM (Maximum MCLK frequency)
(see Notes 2, 3 and Figure 1)
MHz
NOTES: 1. It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can
be tolerated during power-up and operation.
2. The MSP430 CPU is clocked directly with MCLK.
Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency.
3. Modules might have a different maximum input clock specification. See the specification of the respective module in this datasheet.
Legend:
System Frequency --MHz
16 MHz
Supply voltage range
during flash memory
programming
12 MHz
Supply voltage range
during program execution
7.5 MHz
4.15 MHz
1.8 V
2.2 V
2.7 V
3.3 V
3.6 V
Supply Voltage --V
NOTE : Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V.
Figure 1. Operating Area
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
active mode supply current (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
IAM, 1MHz
IAM, 1MHz
IAM, 4kHz
IAM,100kHz
Active mode (AM)
current (1MHz)
Active mode (AM)
current (1MHz)
Active mode (AM)
current (4kHz)
Active mode (AM)
current (100kHz)
TEST CONDITIONS
TA
fDCO = fMCLK = fSMCLK = 1MHz,
fACLK = 32,768Hz,
Program executes from flash,
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
VCC
2.2 V
MIN
TYP
MAX
270
370
μA
fDCO = fMCLK = fSMCLK = 1MHz,
fACLK = 32,768Hz,
Program executes in RAM,
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ
DCOCTL = CALDCO_1MHZ,
CPUOFF = 0, SCG0 = 0, SCG1 = 0,
OSCOFF = 0
3V
390
2.2 V
226
3V
fMCLK = fSMCLK =
fACLK = 32,768Hz/8 = 4,096Hz,
fDCO = 0Hz,
Program executes in flash,
SELMx = 11, SELS = 1,
DIVMx = DIVSx = DIVAx = 11,
CPUOFF = 0, SCG0 = 1, SCG1 = 0,
OSCOFF = 0
--40..85_C
2.2 V
105_C
2.2 V
--40..85_C
3V
105_C
3V
fMCLK = fSMCLK = fDCO(0, 0) ≈ 100kHz,
fACLK = 0Hz
0Hz,
Program executes in flash,
RSELx = 0, DCOx = 0,
CPUOFF = 0,
0 SCG0 = 0
0, SCG1 = 0,
0
OSCOFF = 1
--40..85_C
2.2 V
105_C
2.2 V
--40..85_C
3V
105_C
3V
POST OFFICE BOX 655303
550
μA
318
2
6
14
μA
3
• DALLAS, TEXAS 75265
9
17
60
85
95
72
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V--T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
18
UNIT
95
105
μA
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
typical characteristics -- active mode supply current (into DVCC + AVCC)
8.0
5.0
fDCO = 16 MHz
6.0
fDCO = 12 MHz
5.0
4.0
fDCO = 8 MHz
3.0
2.0
0.0
1.5
2.0
2.5
3.0
3.5
4.0
TA = 25 °C
3.0
VCC = 3 V
2.0
TA = 85 °C
TA = 25 °C
1.0
fDCO = 1 MHz
1.0
TA = 85 °C
Active Mode Current -- mA
Active Mode Current -- mA
7.0
VCC = 2.2 V
4.0
0.0
0.0
VCC -- Supply Voltage -- V
Figure 2. Active mode current vs VCC, TA = 25°C
POST OFFICE BOX 655303
4.0
8.0
12.0
16.0
fDCO -- DCO Frequency -- MHz
Figure 3. Active mode current vs DCO frequency
• DALLAS, TEXAS 75265
19
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
low power mode supply currents (into VCC) excluding external current (see Notes 1 and 2)
PARAMETER
ILPM0, 1MHz
ILPM0, 100kHz
ILPM2
Low-power mode
0 (LPM0) current,
current
see Note 3
Low-power mode
0 (LPM0) current,
current
see Note 3
Low-power mode
2 (LPM2) current,
current
see Note 4
TEST CONDITIONS
VCC
fMCLK = 0MHz,
fSMCLK = fDCO = 1MHz,
1MHz
fACLK = 32,768Hz,
BCSCTL1 = CALBC1_1MHZ,
CALBC1 1MHZ
DCOCTL = CALDCO_1MHZ,
_
CPUOFF = 1,
1 SCG0 = 0
0, SCG1 = 0,
0
OSCOFF = 0
TA = --40..85_C
fMCLK = 0MHz,
fSMCLK = fDCO(0, 0) ≈ 100kHz,
100kHz
fACLK = 0Hz,
RSELx = 0, DCOx = 0,
CPUOFF = 1,
1 SCG0 = 0
0, SCG1 = 0,
0
OSCOFF = 1
fMCLK = fSMCLK = 0MHz, fDCO = 1MHz,
fACLK = 32
32,768Hz,
768Hz
BCSCTL1 = CALBC1_1MHZ,
DCOCTL = CALDCO_1MHZ,
CPUOFF = 1,
1 SCG0 = 0
0, SCG1 = 1,
1
OSCOFF = 0
TA = --40..85_C
TA = 105_C
TA = --40..85_C
TA = 105_C
TA = 105_C
TA = --40..85_C
TA = 105_C
TA = --40..85_C
TA = 105_C
TA = --40..85_C
TA = 105_C
22V
2.2
3V
22V
2.2
3V
22V
2.2
3V
TA = --40..25°C
ILPM3,LFXT1
Low-power mode
3 (LPM3) current,
current
see Note 4
fDCO = fMCLK = fSMCLK = 0MHz,
0MHz
fACLK = 32,768Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
TA = 85°C
MIN
TYP
MAX
68
84
μA
90
μA
110
μA
115
μA
45
μA
50
μA
50
μA
54
μA
28
μA
32
μA
32
μA
37
μA
88
36
40
20
23
0.7
TA = 105°C
0.85
ILPM3,VLO
fDCO = fMCLK = fSMCLK = 0MHz,
0MHz
fACLK from internal LF oscillator (VLO),
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 0
ILPM4
Low-power mode
4 (LPM4) current,
current
see Note 5
2.9
0.35
3.5
3V
11
TA = --40°C
0.5
TA = 85°C
2 2V
2.2V
0.5
1.7
8.6
TA = --40°C
0.5
3V
0.5
1.9
TA = 105°C
NOTES: 1. All inputs are tied to 0 V or VCC. Outputs do not source or sink any current.
2. The currents are characterized with a Micro Crystal CC4V--T1A SMD crystal with a load capacitance of 9 pF.
The internal and external load capacitance is chosen to closely match the required 9pF.
3. Current for brownout and WDT clocked by SMCLK included.
4. Current for brownout and WDT clocked by ACLK included.
5. Current for brownout included.
POST OFFICE BOX 655303
2.7
TA = 105°C
TA = 25°C
• DALLAS, TEXAS 75265
μA
μ
1.0
TA = 105°C
TA = 85°C
20
0.8
9
TA = --40..25°C
TA = 25°C
fDCO = fMCLK = fSMCLK = 0MHz,
0MHz
fACLK = 0Hz,
CPUOFF = 1, SCG0 = 1, SCG1 = 1,
OSCOFF = 1
0.25
2.2 V
TA = 105°C
TA = 85°C
μA
μ
12
TA = --40..25°C
Low-power mode
3 current,
current (LPM3)
see Note 4
1.2
3.8
3V
TA = 105°C
TA = 85°C
μA
μ
10
TA = --40..25°C
TA = 85°C
1.0
3.3
2.2 V
UNIT
3
9
μA
μ
μA
A
μA
A
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
Schmitt-trigger inputs -- Ports P1, P2, P3 P4, JTAG, RST/NMI, and XIN (see Note)
PARAMETER
VIT+
VIT--
TEST CONDITIONS
Positive-going
P
iti
i input
i
t threshold
th h ld
voltage
Negative-going
N
ti
i input
i
t threshold
th h ld
voltage
Vhys
Input voltage hysteresis
(VIT+ -- VIT-- )
RPull
Pullup/pulldown resistor
For pullup: VIN = VSS;
For pulldown: VIN = VCC
CI
Input capacitance
VIN = VSS or VCC
VCC
MIN
MAX
UNIT
0.45
0.75
VCC
2.2 V
1.00
1.65
3V
1.35
2.25
0.25
0.55
2.2 V
0.55
1.20
3V
0.75
1.65
2.2 V
0.2
1.0
3V
0.3
1.0
20
TYP
35
50
5
V
VCC
V
V
kΩ
pF
NOTE : XIN only in bypass mode.
inputs -- Ports P1, P2
PARAMETER
t(int)
TEST CONDITIONS
Port P1, P2: P1.x to P2.x, External
trigger puls width to set interrupt
flag, (see Note)
External interrupt timing
VCC
2.2 V/3 V
MIN
TYP
MAX
20
UNIT
ns
NOTE : An external signal sets the interrupt flag every time the minimum interrupt puls width t(int) is met. It may be set even with trigger signals
shorter than t(int).
leakage current -- Ports P1, P2, P3 and P4
PARAMETER
Ilkg(Px.x)
TEST CONDITIONS
High-impedance leakage current
see Notes 1 and 2
VCC
2.2 V/3 V
MIN
TYP
MAX
UNIT
±50
nA
NOTES: 1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
2. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pull--up/pull--down resistor
is disabled.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
outputs -- Ports P1, P2, P3 and P4
PARAMETER
VOH
VOL
High level output
High-level
voltage
Low level output
Low-level
voltage
VCC
MIN
I(OHmax) = --1.5 mA (see Notes 1)
TEST CONDITIONS
2.2 V
VCC --0.25
TYP
MAX
VCC
UNIT
I(OHmax) = --6 mA (see Notes 2)
2.2 V
VCC --0.6
VCC
I(OHmax) = --1.5 mA (see Notes 1)
3V
VCC --0.25
VCC
I(OHmax) = --6 mA (see Notes 2)
3V
VCC --0.6
VCC
I(OLmax) = 1.5 mA (see Notes 1)
2.2 V
VSS
VSS+0.25
I(OLmax) = 6 mA (see Notes 2)
2.2 V
VSS
VSS+0.6
I(OLmax) = 1.5 mA (see Notes 1)
3V
VSS
VSS+0.25
I(OLmax) = 6 mA (see Notes 2)
3V
VSS
VSS+0.6
V
V
NOTES: 1. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±12 mA to hold the maximum
voltage drop specified.
2. The maximum total current, IOHmax and IOLmax, for all outputs combined, should not exceed ±48 mA to hold the maximum
voltage drop specified.
output frequency -- Ports P1, P2, P3 and P4
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
7.5
MHz
fPx.y
Port output frequency
(with load)
P1.4/SMCLK, CL = 20 pF, RL = 1 kΩ
(see Note 1 and 2)
2.2 V
3V
12
MHz
fPort_CLK
Clock output frequency
P2.0/ACLK, P1.4/SMCLK, CL = 20 pF
(see Note 2)
2.2 V
7.5
MHz
3V
16
MHz
NOTES: 1. A resistive divider with 2 times 0.5 kΩ between VCC and VSS is used as load. The output is connected to the center tap of the divider.
2. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- outputs
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
TYPICAL LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
50.0
TA = 25°C
VCC = 2.2 V
P2.4
20.0
I OL -- Typical Low-Level Output Current -- mA
I OL -- Typical Low-Level Output Current -- mA
25.0
TA = 85°C
15.0
10.0
5.0
0.0
0.0
0.5
1.0
1.5
2.0
VCC = 3 V
P2.4
40.0
TA = 85°C
30.0
20.0
10.0
0.0
0.0
2.5
TA = 25°C
0.5
VOL -- Low-Level Output Voltage -- V
1.0
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
I OH -- Typical High-Level Output Current -- mA
I OH -- Typical High-Level Output Current -- mA
VCC = 2.2 V
P2.4
--5.0
--10.0
--15.0
TA = 85°C
TA = 25°C
0.5
1.0
2.5
3.0
3.5
TYPICAL HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0.0
--25.0
0.0
2.0
Figure 5
Figure 4
--20.0
1.5
VOL -- Low-Level Output Voltage -- V
1.5
2.0
2.5
VOH -- High-Level Output Voltage -- V
0.0
VCC = 3 V
P2.4
--10.0
--20.0
--30.0
--40.0
--50.0
0.0
TA = 85°C
TA = 25°C
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH -- High-Level Output Voltage -- V
Figure 6
Figure 7
NOTE : One output loaded at a time.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
POR/brownout reset (BOR) (see Notes 1 and 2)
PARAMETER
TEST CONDITIONS
VCC(start)
(see Figure 8)
dVCC/dt ≤ 3 V/s
V(B_IT--)
(see Figure 8 through Figure 10)
dVCC/dt ≤ 3 V/s
Vhys(B_IT--)
(see Figure 8)
dVCC/dt ≤ 3 V/s
td(BOR)
(see Figure 8)
t(reset)
Pulse length needed at RST/NMI pin
to accepted reset internally
VCC
MIN
TYP
MAX
0.7 × V(B_IT--)
70
2.2 V/3 V
2
130
UNIT
V
1.71
V
210
mV
2000
μs
μs
NOTES: 1. The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT--)
+ Vhys(B_IT--) is ≤ 1.8V.
2. During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT--) + Vhys(B_IT--). The default
DCO settings must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired
operating frequency.
VCC
Vhys(B_IT--)
V(B_IT--)
VCC(start)
1
0
t d(BOR)
Figure 8. POR/Brownout Reset (BOR) vs Supply Voltage
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- POR/brownout reset (BOR)
VCC
3V
VCC(drop) -- V
2
VCC = 3 V
Typical Conditions
1.5
t pw
1
VCC(drop)
0.5
0
0.001
1
1000
1 ns
tpw -- Pulse Width -- μs
1 ns
tpw -- Pulse Width -- μs
Figure 9. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal
VCC
2
3V
VCC(drop) -- V
VCC = 3 V
1.5
t pw
Typical Conditions
1
VCC(drop)
0.5
0
0.001
tf = tr
1
1000
tf
tr
tpw -- Pulse Width -- μs
tpw -- Pulse Width -- μs
Figure 10. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
main DCO characteristics
D All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14
overlaps RSELx = 15.
D DCO control bits DCOx have a step size as defined by parameter SDCO.
D Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK
cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal
to:
f average =
32 × f DCO(RSEL,DCO) × f DCO(RSEL,DCO+1)
MOD × f DCO(RSEL,DCO)+(32−MOD) × f DCO(RSEL,DCO+1)
DCO frequency
PARAMETER
VCC
Supply voltage range
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
RSELx < 14
1.8
3.6
V
RSELx = 14
2.2
3.6
V
RSELx = 15
3.0
3.6
V
fDCO(0,0)
DCO frequency (0, 0)
RSELx = 0, DCOx = 0, MODx = 0
2.2 V/3 V
0.06
0.14
MHz
fDCO(0,3)
DCO frequency (0, 3)
RSELx = 0, DCOx = 3, MODx = 0
2.2 V/3 V
0.07
0.17
MHz
fDCO(1,3)
DCO frequency (1, 3)
RSELx = 1, DCOx = 3, MODx = 0
2.2 V/3 V
0.10
0.20
MHz
fDCO(2,3)
DCO frequency (2, 3)
RSELx = 2, DCOx = 3, MODx = 0
2.2 V/3 V
0.14
0.28
MHz
fDCO(3,3)
DCO frequency (3, 3)
RSELx = 3, DCOx = 3, MODx = 0
2.2 V/3 V
0.20
0.40
MHz
fDCO(4,3)
DCO frequency (4, 3)
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
0.28
0.54
MHz
fDCO(5,3)
DCO frequency (5, 3)
RSELx = 5, DCOx = 3, MODx = 0
2.2 V/3 V
0.39
0.77
MHz
fDCO(6,3)
DCO frequency (6, 3)
RSELx = 6, DCOx = 3, MODx = 0
2.2 V/3 V
0.54
1.06
MHz
fDCO(7,3)
DCO frequency (7, 3)
RSELx = 7, DCOx = 3, MODx = 0
2.2 V/3 V
0.80
1.50
MHz
fDCO(8,3)
DCO frequency (8, 3)
RSELx = 8, DCOx = 3, MODx = 0
2.2 V/3 V
1.10
2.10
MHz
fDCO(9,3)
DCO frequency (9, 3)
RSELx = 9, DCOx = 3, MODx = 0
2.2 V/3 V
1.60
3.00
MHz
fDCO(10,3)
DCO frequency (10, 3)
RSELx = 10, DCOx = 3, MODx = 0
2.2 V/3 V
2.50
4.30
MHz
fDCO(11,3)
DCO frequency (11, 3)
RSELx = 11, DCOx = 3, MODx = 0
2.2 V/3 V
3.00
5.50
MHz
fDCO(12,3)
DCO frequency (12, 3)
RSELx = 12, DCOx = 3, MODx = 0
2.2 V/3 V
4.30
7.30
MHz
fDCO(13,3)
DCO frequency (13, 3)
RSELx = 13, DCOx = 3, MODx = 0
2.2 V/3 V
6.00
9.60
MHz
fDCO(14,3)
DCO frequency (14, 3)
RSELx = 14, DCOx = 3, MODx = 0
2.2 V/3 V
8.60
13.9
MHz
fDCO(15,3)
DCO frequency (15, 3)
RSELx = 15, DCOx = 3, MODx = 0
3V
12.0
18.5
MHz
fDCO(15,7)
DCO frequency (15, 7)
RSELx = 15, DCOx = 7, MODx = 0
3V
16.0
26.0
MHz
SRSEL
Frequency step between
range RSEL and RSEL+1
SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO)
2.2 V/3 V
SDCO
Frequency step between
tap DCO and DCO+1
SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO)
2.2 V/3 V
1.05
1.08
1.12
Measured at P1.4/SMCLK
2.2 V/3 V
40
50
60
Duty Cycle
26
1.55
ratio
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
%
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies -- tolerance at calibration
PARAMETER
TEST CONDITIONS
Frequency tolerance at calibration
TA
VCC
MIN
TYP
MAX
UNIT
25°C
3V
--1
±0.2
+1
%
25°C
3V
0.990
1
1.010
MHz
fCAL(1MHz)
1MHz calibration value
BCSCTL1= CALBC1_1MHZ;
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
fCAL(8MHz)
8MHz calibration value
BCSCTL1= CALBC1_8MHZ;
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
25°C
3V
7.920
8
8.080
MHz
fCAL(12MHz)
12MHz calibration
value
BCSCTL1= CALBC1_12MHZ;
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
25°C
3V
11.88
12
12.12
MHz
fCAL(16MHz)
16MHz calibration
value
BCSCTL1= CALBC1_16MHZ;
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
25°C
3V
15.84
16
16.16
MHz
MIN
MAX
UNIT
calibrated DCO frequencies -- tolerance over temperature 0°C -- +85°C
TA
VCC
1 MHz tolerance over temperature
PARAMETER
0°C -- 85°C
3.0 V
--2.5
±0.5
+2.5
%
8 MHz tolerance over temperature
0°C -- 85°C
3.0 V
--2.5
±1
+2.5
%
12 MHz tolerance over temperature
0°C -- 85°C
3.0 V
--2.5
±1
+2.5
%
16 MHz tolerance over temperature
0°C -- 85°C
3.0 V
--3
±2
+3
2.2 V
0.970
1
1.030
MHz
3.0 V
0.975
1
1.025
MHz
3.6 V
0.970
1
1.030
MHz
2.2 V
7.760
8
8.400
MHz
3.0 V
7.800
8
8.200
MHz
3.6 V
7.600
8
8.240
MHz
2.2 V
11.64
12
12.36
MHz
3.0 V
11.64
12
12.36
MHz
3.6 V
11.64
12
12.36
MHz
3.0 V
15.52
16
16.48
MHz
3.6 V
15.00
16
16.48
MHz
fCAL(1MHz)
fCAL(8MHz)
fCAL(12MHz)
fCAL(16MHz)
1MHz calibration value
8MHz calibration value
TEST CONDITIONS
BCSCTL1= CALBC1_1MHZ;
CALBC1 1MHZ;
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
BCSCTL1= CALBC1_8MHZ;
CALBC1 8MHZ;
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
0°C
0
C -- 85
85°C
C
0°C
0
C -- 85
85°C
C
12MHz calibration
12MH
lib ti
value
BCSCTL1= CALBC1_12MHZ;
CALBC1 12MHZ;
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
0°C
0
C -- 85
85°C
C
16MHz calibration
value
BCSCTL1= CALBC1_16MHZ;
DCOCTL = CALDCO_16MHZ
CALDCO 16MHZ
Gating time: 2ms
0°C -- 85°C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TYP
%
27
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
calibrated DCO frequencies -- tolerance over supply voltage VCC
PARAMETER
TEST CONDITIONS
TA
VCC
MIN
TYP
MAX
UNIT
1 MHz tolerance over VCC
25°C
1.8 V -- 3.6 V
--3
±2
+3
%
8 MHz tolerance over VCC
25°C
1.8 V -- 3.6 V
--3
±2
+3
%
12 MHz tolerance over VCC
25°C
2.2 V -- 3.6 V
--3
±2
+3
%
16 MHz tolerance over VCC
25°C
3.0 V -- 3.6 V
--6
±2
+3
%
25°C
1.8 V -- 3.6 V
0.970
1
1.030
MHz
fCAL(1MHz)
1MHz calibration value
BCSCTL1= CALBC1_1MHZ;
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
fCAL(8MHz)
8MHz calibration value
BCSCTL1= CALBC1_8MHZ;
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
25°C
1.8 V -- 3.6 V
7.760
8
8.240
MHz
fCAL(12MHz)
12MHz calibration
value
BCSCTL1= CALBC1_12MHZ;
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
25°C
2.2 V -- 3.6 V
11.64
12
12.36
MHz
fCAL(16MHz)
16MHz calibration
value
BCSCTL1= CALBC1_16MHZ;
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
25°C
3.0 V -- 3.6 V
15.00
16
16.48
MHz
TA
VCC
MIN
MAX
UNIT
1 MHz tolerance overall
--40°C -- 105°C
1.8 V -- 3.6 V
--5
±2
+5
%
8 MHz tolerance overall
--40°C -- 105°C
1.8 V -- 3.6 V
--5
±2
+5
%
12 MHz tolerance overall
--40°C -- 105°C
2.2 V -- 3.6 V
--5
±2
+5
%
%
calibrated DCO frequencies -- overall tolerance
PARAMETER
TEST CONDITIONS
16 MHz tolerance overall
TYP
--40°C -- 105°C
3.0 V -- 3.6 V
--6
±3
+6
--40°C -- 105°C
1.8 V -- 3.6 V
0.950
1
1.050
MHz
fCAL(1MHz)
1MHz calibration value
BCSCTL1= CALBC1_1MHZ;
DCOCTL = CALDCO_1MHZ
Gating time: 5ms
fCAL(8MHz)
8MHz calibration value
BCSCTL1= CALBC1_8MHZ;
DCOCTL = CALDCO_8MHZ
Gating time: 5ms
--40°C -- 105°C
1.8 V -- 3.6 V
7.600
8
8.400
MHz
fCAL(12MHz)
12MHz calibration
value
BCSCTL1= CALBC1_12MHZ;
DCOCTL = CALDCO_12MHZ
Gating time: 5ms
--40°C -- 105°C
2.2 V -- 3.6 V
11.40
12
12.60
MHz
fCAL(16MHz)
16MHz calibration
value
BCSCTL1= CALBC1_16MHZ;
DCOCTL = CALDCO_16MHZ
Gating time: 2ms
--40°C -- 105°C
3.0 V -- 3.6 V
15.00
16
17.00
MHz
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
1.03
Frequency -- MHz
1.02
TA = 105 °C
1.01
TA = 85 °C
1.00
TA = 25 °C
0.99
TA = --40 °C
0.98
0.97
1.5
2.0
2.5
3.0
3.5
4.0
VCC -- Supply Voltage -- V
Figure 11. Calibrated 1 MHz Frequency vs. VCC
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
,electrical
characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
wake-up from lower power modes (LPM3/4)
PARAMETER
tDCO,LPM3/4
tCPU,LPM3/4
TEST CONDITIONS
DCO clock wake--up time from
LPM3/4
(see Note 1)
VCC
MIN
TYP
MAX
BCSCTL1= CALBC1_1MHZ;
DCOCTL = CALDCO_1MHZ
2.2 V/3 V
2
BCSCTL1= CALBC1_8MHZ;
DCOCTL = CALDCO_8MHZ
2.2 V/3 V
1.5
BCSCTL1= CALBC1_12MHZ;
DCOCTL = CALDCO_12MHZ
2.2 V/3 V
1
BCSCTL1= CALBC1_16MHZ;
DCOCTL = CALDCO_16MHZ
3V
1
UNIT
μs
s
CPU wake--up time from LPM3/4
(see Note 2)
1/fMCLK +
tClock,LPM3/4
NOTES: 1. The DCO clock wake--up time is measured from the edge of an external wake--up signal (e.g. port interrupt) to the first clock edge
observable externally on a clock pin (MCLK or SMCLK).
2. Parameter applicable only if DCOCLK is used for MCLK.
typical characteristics -- DCO clock wake--up time from LPM3/4
DCO Wake Time -- us
10.00
1.00
0.10
0.10
RSELx = 0...11
RSELx = 12...15
1.00
10.00
DCO Frequency -- MHz
Figure 12. Clock wake--up time from LPM3 vs DCO frequency
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
DCO with external resistor ROSC (see Note)
PARAMETER
TEST CONDITIONS
VCC
fDCO,ROSC
DCO output frequency
with ROSC
DCOR = 1,
RSELx = 4,
4 DCOx = 3,
3 MODx = 0
0,
TA = 25°C
Dt
Temperature drift
DV
Drift with VCC
MIN
TYP
MAX
UNIT
2.2 V
1.8
3V
1.95
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
±0.1
%/°C
DCOR = 1,
RSELx = 4, DCOx = 3, MODx = 0
2.2 V/3 V
10
%/V
MHz
NOTE : ROSC = 100kΩ. Metal film resistor, type 0257. 0.6 watt with 1% tolerance and TK = ±50ppm/°C.
typical characteristics -- DCO with external resistor ROSC
10.00
1.00
0.10
RSELx = 4
0.01
10.00
100.00
1000.00
DCO Frequency -- MHz
DCO Frequency -- MHz
10.00
1.00
0.10
RSELx = 4
0.01
10.00
10000.00
ROSC -- External Resistor -- kΩ
10000.00
Figure 14. DCO Frequency vs ROSC,
VCC = 3.0 V, TA = 25°C
2.50
2.50
2.25
2.25
DCO Frequency -- MHz
ROSC = 100k
2.00
1.75
DCO Frequency -- MHz
1000.00
ROSC -- External Resistor -- kΩ
Figure 13. DCO Frequency vs ROSC,
VCC = 2.2 V, TA = 25°C
1.50
1.25
1.00
ROSC = 270k
0.75
0.50
--25
0
25
50
75
ROSC = 100k
2.00
1.75
1.50
1.25
1.00
ROSC = 270k
0.75
0.50
ROSC = 1M
0.25
0.00
--50
100.00
ROSC = 1M
0.25
100
0.00
2.0
Figure 15. DCO Frequency vs Temperature,
VCC = 3.0 V
POST OFFICE BOX 655303
2.5
3.0
3.5
4.0
VCC -- Supply Voltage -- V
TA -- Temperature -- °C
Figure 16. DCO Frequency vs VCC,
TA = 25°C
• DALLAS, TEXAS 75265
31
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, low frequency modes (see Note 4)
PARAMETER
TEST CONDITIONS
VCC
fLFXT1,LF
LFXT1 oscillator crystal
frequency, LF mode 0, 1
XTS = 0, LFXT1Sx = 0 or 1
1.8 V -- 3.6 V
fLFXT1,LF,logic
LFXT1 oscillator logic level
square wave input frequency,
LF mode
XTS = 0, XCAPx = 0,
LFXT1Sx = 3
1.8 V -- 3.6 V
Oscillation allowance for LF
crystals
OALF
Integrated effective load
capacitance LF mode
capacitance,
(see Note 1)
CL,eff
MIN
TYP
MAX
32,768
10,000
32,768
UNIT
Hz
50,000
Hz
XTS = 0, LFXT1Sx = 0;
fLFXT1,LF = 32,768 kHz,
CL,eff = 6 pF
500
kΩ
XTS = 0, LFXT1Sx = 0;
fLFXT1,LF = 32,768 kHz,
CL,eff = 12 pF
200
kΩ
XTS = 0, XCAPx = 0
1
pF
XTS = 0, XCAPx = 1
5.5
pF
XTS = 0, XCAPx = 2
8.5
pF
XTS = 0, XCAPx = 3
11
pF
Duty cycle
LF mode
XTS = 0, Measured at P1.4/ACLK,
fLFXT1,LF = 32,768Hz
fFault,LF
Oscillator fault frequency, LF
mode (see Note 3)
XTS = 0, XCAPx = 0.
LFXT1Sx = 3 (see Note 2)
2.2 V/3 V
30
2.2 V/3 V
10
50
70
%
10,000
Hz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Measured with logic level input frequency but also applies to operation with crystals.
3. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
4. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep as short of a trace as possible between the device and the crystal.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
----
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
internal very low power, low frequency oscillator (VLO)
PARAMETER
TEST CONDITIONS
VCC
fVLO
VLO frequency
2.2 V/3 V
dfVLO/dT
VLO frequency temperature drift
(See Note 1)
2.2 V/3 V
dfVLO/dVCC
VLO frequency supply voltage
drift
(See Note 2)
1.8V -- 3.6V
MIN
TYP
MAX
4
12
20
NOTES: 1. Calculated using the box method:
I Version: (MAX(--40...85_C) -- MIN(--40...85_C))/MIN(--40...85_C)/(85_C -- (--40_C))
T Version: (MAX(--40...105_C) -- MIN(--40...105_C))/MIN(--40...105_C)/(105_C -- (--40_C))
2. Calculated using the box method: (MAX(1.8...3.6V) -- MIN(1.8...3.6V))/MIN(1.8...3.6V)/(3.6V -- 1.8V)
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
kHz
0.5
%/°C
4
%/V
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
crystal oscillator, LFXT1, high frequency modes (see Note 5)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fLFXT1,HF0
LFXT1 oscillator crystal frequency,
HF mode 0
XTS = 1, XCAPx = 0, LFXT1Sx = 0
1.8 V -- 3.6 V
0.4
1
MHz
fLFXT1,HF1
LFXT1 oscillator crystal frequency,
HF mode 1
XTS = 1, XCAPx = 0, LFXT1Sx = 1
1.8 V -- 3.6 V
1
4
MHz
LFXT1 oscillator
ill t crystal
t l frequency,
f
HF mode 2
1.8 V -- 3.6 V
2
10
MHz
fLFXT1,HF2
XTS = 1, XCAPx = 0, LFXT1Sx = 2
2.2 V -- 3.6 V
2
12
MHz
3.0 V -- 3.6 V
2
16
MHz
1.8 V -- 3.6 V
0.4
10
MHz
2.2 V -- 3.6 V
0.4
12
MHz
3.0 V -- 3.6 V
0.4
16
MHz
LFXT1 oscillator
ill t logic
l i level
l
l square
wave input frequency,
frequency HF mode
fLFXT1,HF,logic
Oscillation allowance for HF
crystals
(refer to Figure 17 and Figure 18)
OAHF
Integrated effective load
capacitance, HF mode
(see Note 1)
CL,eff
Duty cycle
XTS = 1, XCAPx = 0, LFXT1Sx = 0,
fLFXT1,HF = 1 MHz, CL,eff = 15 pF
2700
Ω
XTS = 1, XCAPx = 0, LFXT1Sx = 1
fLFXT1,HF = 4 MHz, CL,eff = 15 pF
800
Ω
XTS = 1, XCAPx = 0, LFXT1Sx = 2
fLFXT1,HF = 16 MHz, CL,eff = 15 pF
300
Ω
1
pF
XTS = 1, XCAPx = 0 (see Note 2)
HF mode
Oscillator fault frequency, HF mode
(see Note 4)
fFault,HF
XTS = 1, XCAPx = 0, LFXT1Sx = 3
XTS = 1, XCAPx = 0,
Measured at P1.4/ACLK,
fLFXT1,HF = 10 MHz
2.2 V/3 V
40
50
60
%
XTS = 1, XCAPx = 0,
Measured at P1.4/ACLK,
fLFXT1,HF = 16 MHz
2.2 V/3 V
40
50
60
%
XTS = 1, XCAPx = 0, LFXT1Sx = 3
(see Notes 3)
2.2 V/3 V
30
300
kHz
NOTES: 1. Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup the effective load capacitance should always match the specification of the used crystal.
2. Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
3. Measured with logic level input frequency but also applies to operation with crystals.
4. Frequencies below the MIN specification will set the fault flag, frequencies above the MAX specification will not set the fault flag.
Frequencies in between might set the flag.
5. To improve EMI on the LFXT1 oscillator the following guidelines should be observed.
-- Keep as short of a trace as possible between the device and the crystal.
-- Design a good ground plane around the oscillator pins.
-- Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
-- Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
----
Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other
documentation. This signal is no longer required for the serial programming adapter.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- LFXT1 oscillator in HF mode (XTS = 1)
Oscillation Allowance -- Ohms
100000.00
10000.00
1000.00
LFXT1Sx = 3
100.00
LFXT1Sx = 2
LFXT1Sx = 1
10.00
0.10
1.00
10.00
100.00
Crystal Frequency -- MHz
Figure 17. Oscillation Allowance vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
XT Oscillator Supply Current -- uA
800.0
LFXT1Sx = 3
700.0
600.0
500.0
400.0
300.0
LFXT1Sx = 2
200.0
100.0
LFXT1Sx = 1
0.0
0.0
4.0
8.0
12.0
16.0
20.0
Crystal Frequency -- MHz
Figure 18. XT Oscillator Supply Current vs Crystal Frequency, CL,eff = 15 pF, TA = 25°C
34
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Timer_A
PARAMETER
TEST CONDITIONS
fTA
Timer A clock frequency
Timer_A
Internal: SMCLK, ACLK;
External: TACLK,
TACLK INCLK;
Duty Cycle = 50% ±10%
tTA,cap
Timer_A, capture timing
TA0, TA1, TA2
VCC
MIN
TYP
MAX
2.2 V
10
3V
16
2.2 V/3 V
20
UNIT
MHz
ns
Timer_B
PARAMETER
TEST CONDITIONS
fTB
Timer B clock frequency
Timer_B
Internal: SMCLK, ACLK;
External: TBCLK;
Duty Cycle = 50% ±10%
tTB,cap
Timer_B, capture timing
TB0, TB1, TB2
POST OFFICE BOX 655303
VCC
TYP
MAX
10
3V
16
2.2 V/3 V
• DALLAS, TEXAS 75265
MIN
2.2 V
20
UNIT
MHz
ns
35
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART Mode)
PARAMETER
fUSCI
USCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baudrate in MBaud)
tτ
UART receive deglitch time
(see Note NO TAG)
TEST CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50% ± 10%
2.2V /3 V
MAX
UNIT
fSYSTEM
MHz
1
MHz
2.2 V
50
150
600
ns
3V
50
100
600
ns
NOTE : Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI Master Mode, see Figure 19 and Figure 20)
PARAMETER
fUSCI
USCI input clock frequency
tSU,MI
SOMI input data setup time
tHD,MI
tVALID,MO
TEST CONDITIONS
VCC
MIN
TYP
SMCLK, ACLK
Duty Cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
2.2 V
110
ns
3V
75
ns
2.2 V
SOMI input data hold time
ns
3V
UCLK edge to SIMO valid;
CL = 20 pF
SIMO output data valid time
ns
2.2 V
30
ns
3V
20
ns
USCI (SPI Slave Mode, see Figure 21 and Figure 22)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tSTE,LEAD
STE lead time
STE low to clock
2.2 V/3 V
tSTE,LAG
STE lag time
Last clock to STE high
2.2 V/3 V
tSTE,ACC
STE access time
STE low to SOMI data out
2.2 V/3 V
50
ns
tSTE,DIS
STE disable time
STE high to SOMI high impedance
2.2 V/3 V
50
ns
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
36
SOMI output data valid time
UCLK edge to SOMI valid;
CL = 20 pF
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
50
ns
10
ns
2.2 V
20
ns
3V
15
ns
2.2 V
10
ns
3V
10
ns
2.2 V
75
110
ns
3V
50
75
ns
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)6
1/fUCxCLK
CKPL
=0
CKPL
=1
UCLK
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID ,MO
SIMO
Figure 19. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL
=0
CKPL
=1
UCLK
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID ,MO
SIMO
Figure 20. SPI Master Mode, CKPH = 1
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
37
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)7
tSTE,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL
=0
CKPL
=1
UCLK
tLOW/HIGH
tLOW/HIGH
tSU,SIMO
tHD,SIMO
SIMO
tACC
tVALID ,SOMI
tDIS
SOMI
Figure 21. SPI Slave Mode, CKPH = 0
tSTE ,LEAD
tSTE,LAG
STE
1/fUCxCLK
CKPL=0
UCLK
CKPL=1
tLOW/HIGH
tLOW/HIGH
tSU,SI
tHD,SI
SIMO
tACC
tVALID ,SO
SOMI
Figure 22. SPI Slave Mode, CKPH = 1
38
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
tDIS
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (I2C Mode, see Figure 23)
PARAMETER
TEST CONDITIONS
fUSCI
USCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
TYP
Internal: SMCLK, ACLK
External: UCLK
Duty Cycle = 50% ± 10%
MAX
UNIT
fSYSTEM
MHz
400
kHz
2.2 V/3 V
0
fSCL ≤ 100kHz
2.2 V/3 V
4.0
us
fSCL > 100kHz
2.2 V/3 V
0.6
us
fSCL ≤ 100kHz
2.2 V/3 V
4.7
us
fSCL > 100kHz
2.2 V/3 V
0.6
us
tHD,STA
Hold time (repeated) START
tSU,STA
Set p time for a repeated START
Set--up
tHD,DAT
Data hold time
2.2 V/3 V
0
ns
tSU,DAT
Data setup time
2.2 V/3 V
250
ns
tSU,STO
Setup time for STOP
2.2 V/3 V
4.0
us
tSP
Pulse width of spikes suppressed by
input filter
2.2 V
50
150
600
ns
3V
50
100
600
ns
tHD ,STA
tSU ,STA tHD ,STA
tBUF
SDA
t
LOW
tHIGH
tSP
SCL
tSU ,DAT
tSU ,STO
tHD ,DAT
Figure 23. I2C Mode Timing
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
39
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Comparator_A+ (see Note 1)
PARAMETER
TEST CONDITIONS
I(DD)
CAON 1 CARSEL=0,
CAON=1,
CARSEL 0 CAREF=0
CAREF 0
I(Refladder/RefDiode)
CAON=1, CARSEL=0,
CAREF 1/2/3
CAREF=1/2/3,
no load at P1.0/CA0 and P1.1/CA1
V(IC)
V(Ref025)
V(Ref050)
VCC
MIN
TYP
MAX
2.2 V
25
40
3V
45
60
2.2 V
30
50
3V
45
71
Common-mode input voltage
CAON=1
2.2 V/3 V
0
Voltage @ 0.25 V
node
PCA0=1, CARSEL=1, CAREF=1,
no load at P1.0/CA0 and P1.1/CA1
2.2 V/3 V
0.23
0.24
0.25
node
PCA0=1, CARSEL=1, CAREF=2,
no load at P1.0/CA0 and P1.1/CA1
2.2 V/3 V
0.47
0.48
0.5
2.2 V
390
480
540
3V
400
490
550
V
CC
Voltage @ 0.5V
V
CC
CC
CC
VCC --1
UNIT
μA
μA
V
V(RefVT)
(see Figure 27 and Figure 28)
PCA0=1, CARSEL=1, CAREF=3,
no load at P1.0/CA0
P1 0/CA0 and P1
P1.1/CA1,
1/CA1
TA = 85°C
V(offset)
Offset voltage
See Note 2
2.2 V/3 V
--30
30
mV
Vhys
Input hysteresis
CAON=1
2.2 V/3 V
0
0.7
1.4
mV
2.2 V
80
165
300
3V
70
120
240
t(response)
Response time
(low-high and high-low)
TA = 25°C, Overdrive 10 mV,
Without filter: CAF=0
(see Note 3, Figure 24 and
Figure 25)
mV
ns
TA = 25°C, Overdrive 10 mV,
2.2 V
1.4
1.9
2.8
With filter: CAF=1
μs
(see Note 3, Figure 24 and
3V
0.9
1.5
2.2
Figure 25)
NOTES: 1. The leakage current for the Comparator_A+ terminals is identical to Ilkg(Px.x) specification.
2. The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A+ inputs on successive measurements.
The two successive measurements are then summed together.
3. Response time measured at P1.3/CAOUT.
40
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
0V
VCC
0
1
CAF
CAON
To Internal
Modules
Low Pass Filter
+
_
V+
V--
0
0
1
1
CAOUT
Set CAIFG
Flag
τ ≈ 2.0 μs
Figure 24. Block Diagram of Comparator_A+ Module
VCAOUT
Overdrive
V-400 mV
t(response)
V+
Figure 25. Overdrive Definition
CASHORT
CA0
CA1
1
VIN
+
--
IOUT = 10μA
Comparator_A+
CASHORT = 1
Figure 26. Comparator_A+ Short Resistance Test Condition
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
41
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
typical characteristics -- Comparator_A+
650
650
VCC = 2.2 V
V(REFVT) -- Reference Volts -- mV
V(REFVT) -- Reference Volts -- mV
VCC = 3 V
600
Typical
550
500
450
400
--45
--25
--5
15
35
55
75
600
Typical
550
500
450
400
--45
95
--25
--5
15
Short Resistance -- kOhms
100.00
VCC = 1.8V
VCC = 2.2V
VCC = 3.0V
VCC = 3.6V
1.00
0.0
0.2
0.4
0.6
0.8
VIN/VCC -- Normalized Input Voltage -- V/V
1.0
Figure 29. Short Resistance vs VIN/VCC
42
55
75
95
Figure 28. V(RefVT) vs Temperature, VCC = 2.2 V
Figure 27. V(RefVT) vs Temperature, VCC = 3 V
10.00
35
TA -- Free-Air Temperature -- °C
TA -- Free-Air Temperature -- °C
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
Flash Memory
PARAMETER
VCC(PGM/
TEST CONDITIONS
VCC
Program and erase supply voltage
ERASE)
MIN
TYP
2.2
fFTG
Flash Timing Generator frequency
IPGM
Supply current from VCC during program
2.2 V/3.6 V
257
1
IERASE
Supply current from VCC during erase
2.2 V/3.6 V
1
tCPT
Cumulative program time (see Note 1)
2.2 V/3.6 V
tCMErase
Cumulative mass erase time
2.2 V/3.6 V
TJ = 25°C
V
476
kHz
5
mA
7
mA
10
ms
ms
105
tRetention
Data retention duration
tWord
Word or byte program time
30
tBlock, 0
Block program time for first byte or word
25
tBlock, 1-63
Block program time for each additional byte or word
tBlock, End
Block program end-sequence wait time
tMass Erase
Mass erase time
tSeg Erase
Segment erase time
cycles
100
years
18
see Note 2
UNIT
3.6
20
104
Program/erase endurance
MAX
tFTG
6
10593
4819
NOTES: 1. The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word/byte write and block write modes.
2. These values are hardwired into the Flash Controller’s state machine (tFTG = 1/fFTG).
RAM
PARAMETER
V(RAMh)
TEST CONDITIONS
RAM retention supply voltage (see Note)
CPU halted
MIN
TYP
MAX
1.6
UNIT
V
NOTE : This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen
during this supply voltage condition.
JTAG Interface
TEST
CONDITIONS
PARAMETER
fTCK
TCK input frequency
see Note 1
RInternal
Internal pullup resistance on TMS, TCK, TDI/TCLK
see Note 2
VCC
MIN
2.2 V
0
NOM
MAX
UNIT
5
MHz
3V
0
10
MHz
2.2 V/ 3 V
20
35
55
kΩ
MIN
NOM
MAX
NOTES: 1. fTCK may be restricted to meet the timing requirements of the module selected.
2. TMS, TDI/TCLK, and TCK pull-up resistors are implemented in all versions.
JTAG Fuse (see Note)
TEST
CONDITIONS
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TDI/TCLK for fuse-blow: F versions
IFB
Supply current into TDI/TCLK during fuse blow
tFB
Time to blow fuse
NOTE :
TA = 25°C
VCC
2.5
6
UNIT
V
7
V
100
mA
1
ms
Once the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched
to bypass mode.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
43
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
APPLICATION INFORMATION
Port P1 pin schematic: P1.0 to P1.7, input/output with Schmitt-trigger
Pad Logic
P1REN.x
P1DIR.x
0
0
Module X OUT
1
0
DVCC
1
P1.0/TACLK
P1.1/TA0
P1.2/TA1
P1.3/TA2
P1.4/SMCLK
P1.5/TA0
P1.6/TA1
P1.7/TA2
P1SEL.x
P1IN.x
EN
Module X IN
D
P1IE.x
P1IRQ.x
EN
Q
P1IFG.x
P1SEL.x
P1IES.x
44
1
Direction
0: Input
1: Output
1
P1OUT.x
DVSS
Set
Interrupt
Edge Select
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
Port P1 (P1.0 to P1.7) pin functions
PIN NAME (P1.X)
(P1 X)
P1.0/TACLK
/
X
0
FUNCTION
P1.0 (I/O)
Timer_A3.TACLK
DVSS
P1.1/TA0
/
P1.2/TA1
/
P1.3/TA2
/
1
2
3
P1.4/SMCLK
/
4
P1.5/TA0
/
5
P1.7/TA2
/
6
7
P1DIR.x
P1SEL.x
I: 0; O: 1
0
0
1
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
I: 0; O: 1
0
P1.1 (I/O)
P1.2 (I/O)
P1.3 (I/O)
P1.4 (I/O)
SMCLK
P1.6/TA1
/
CONTROL BITS / SIGNALS
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA0
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA1
1
1
I: 0; O: 1
0
Timer_A3.CCI0A
0
1
Timer_A3.TA2
1
1
P1.5 (I/O)
P1.6 (I/O)
P1.7 (I/O)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
45
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
Port P2 pin schematic: P2.0 -- P2.4, input/output with Schmitt-trigger
Pad Logic
To
Comparator_A
From
Comparator_A
CAPD.x
P2REN.x
P2DIR.x
0
0
Module X OUT
1
0
DVCC
1
Bus
Keeper
EN
P2SEL.x
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ.x
EN
Q
P2IFG.x
P2SEL.x
P2IES.x
46
1
Direction
0: Input
1: Output
1
P2OUT.x
DVSS
Set
Interrupt
Edge Select
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
P2.0/ACLK/CA2
P2.1/TAINCLK/CA3
P2.2/CAOUT/TA0/CA4
P2.3/CA0/TA1
P2.4/CA1/TA2
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
Port P2.0 -- P2.4 pin functions
PIN NAME (P2.X)
(P2 X)
P2.0/ACLK/CA2
/
/
P2.1/TAINCLK/CA3
/
/
P2.2/CAOUT/TA0/
/
/
/
CA4
P2.3/CA0/TA1
/
/
P2.4/CA1/TA2
/
/
X
0
1
2
3
4
CONTROL BITS / SIGNALS
FUNCTION
CAPD.x
P2DIR.x
P2SEL.x
P2.0 (I/O)
0
I: 0; O: 1
0
ACLK
0
1
1
CA2 (see Note 2)
1
X
X
P2.1 (I/O)
0
I: 0; O: 1
0
Timer_A3.TAINCLK
0
0
1
DVSS
0
1
1
CA3 (see Note 2)
1
X
X
P2.2 (I/O)
0
I: 0; O: 1
0
CAOUT
0
1
1
TA0
0
0
1
CA4 (see Note 2)
1
X
X
P2.3 (I/O)
0
I: 0; O: 1
0
CA0 (see Note 2)
1
X
X
Timer_A3.TA1
0
1
1
P2.4 (I/O)
0
I: 0; O: 1
0
CA1 (see Note 2)
1
X
X
Timer_A3.TA2
0
1
1
NOTES: 1. X: Don’t care.
2. Setting the CAPD.x bit disables the output driver as well as the input to prevent parasitic cross currents when applying analog signals.
Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin,
regardless of the state of the associated CAPD.s bit.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
47
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
Port P2 pin schematic: P2.5, input/output with Schmitt-trigger
Pad Logic
To Comparator
From Comparator
CAPD.5
To DCO
DCOR
in DCO
P2REN.5
P2DIR.5
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.5
DVSS
P2.5/ROSC/CA5
Bus
Keeper
EN
P2SEL.x
P2IN.5
EN
Module X IN
D
P2IE.5
P2IRQ.5
EN
Q
Set
P2IFG.5
P2SEL.5
Interrupt
Edge Select
P2IES.5
Port P2.5 pin functions
PIN NAME (P2.X)
(P2 X)
P2.5/R
/ OSC//CA5
X
5
FUNCTION
CONTROL BITS / SIGNALS
CAPD.5
DCOR
P2DIR.5
P2SEL.5
P2.5 (I/O)
0
0
I: 0; O: 1
0
ROSC
0
1
X
X
DVSS
0
0
1
1
CA5 (see Note 2)
1
0
X
X
NOTES: 1. X: Don’t care.
2. Setting the CAPD.x bit disables the output driver as well as the input to prevent parasitic cross currents when applying analog signals.
Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin,
regardless of the state of the associated CAPD.s bit.
48
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
Port P2 pin schematic: P2.6, input/output with Schmitt-trigger
BCSCTL3.LFXT1Sx = 11
P2.7/XOUT/CA7
LFXT1 off
0
LFXT1CLK
1
Pad Logic
To Comparator
From
Comparator
CAPD.6
P2SEL.7
P2REN.6
P2DIR.6
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.6
DVSS
P2.6/XIN/CA6
Bus
Keeper
EN
P2SEL.6
P2IN.6
EN
Module X IN
D
P2IE.6
P2IRQ.6
EN
Q
P2IFG.6
P2SEL.6
P2IES.6
Set
Interrupt
Edge Select
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
49
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
Port P2.6 pin functions
PIN NAME (P2.X)
(P2 X)
P2.6/XIN/CA6
/
/
X
6
CONTROL BITS / SIGNALS
FUNCTION
CAPD.6
P2DIR.6
P2SEL.6
P2.6 (I/O)
0
I: 0; O: 1
0
XIN (default)
X
1
1
CA6 (see Note 2)
1
X
0
NOTES: 1. X: Don’t care.
2. Setting the CAPD.x bit disables the output driver as well as the input to prevent parasitic cross currents when applying analog signals.
Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin,
regardless of the state of the associated CAPD.s bit.
50
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
Port P2 pin schematic: P2.7, input/output with Schmitt-trigger
BCSCTL3.LFXT1Sx = 11
P2.6/XIN/TA1
LFXT1 off
0
LFXT1CLK
From P2.6/XIN
1
Pad Logic
To Comparator
From
Comparator
CAPD.7
P2SEL.6
P2REN.7
P2DIR.7
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P2OUT.7
DVSS
P2.7/XOUT
Bus
Keeper
EN
P2SEL.7
P2IN.7
EN
Module X IN
D
P2IE.7
P2IRQ.7
EN
Q
P2IFG.7
P2SEL.7
P2IES.7
Set
Interrupt
Edge Select
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
51
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
Port P2.7 pin functions
PIN NAME (P2.X)
(P2 X)
P2.7/XOUT/CA7
/
/
X
7
CONTROL BITS / SIGNALS
FUNCTION
CAPD.7
P2DIR.7
P2SEL.7
P2.7 (I/O)
0
I: 0; O: 1
0
XOUT (default)
X
1
1
CA7 (see Note 2)
1
X
0
NOTES: 1. X: Don’t care.
2. Setting the CAPD.x bit disables the output driver as well as the input to prevent parasitic cross currents when applying analog signals.
Selecting the CAx input to the comparator multiplexer with the P2CAx bits automatically disables the input buffer for that pin,
regardless of the state of the associated CAPD.s bit.
52
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
Port P3 pin schematic: P3.0 to P3.5, input/output with Schmitt-trigger
Pad Logic
P3REN.x
P3DIR.x
0
Module
direction
1
P3OUT.x
0
Module X OUT
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3.0/UCB0STE/UCA0CLK
P3.1/UCB0SIMO/UCB0SDA
P3.2/UCB0SOMI/UCB0SCL
P3.3/UCB0CLK/UCA0STE
P3.4/UCA0TXD/UCA0SIMO
P3.5/UCA0RXD/UCA0SOMI
P3SEL.x
P3IN.x
EN
Module X IN
D
Port P3.0 to P3.5 pin functions
PIN NAME (P3.X)
(P3 X)
X
P3.0/UCB0STE/
/
/
UCA0CLK
0
P3.1/UCB0SIMO/
/
/
UCB0SDA
1
P3.2/UCB0SOMI/
/
/
UCB0SCL
2
P3.3/UCB0CLK/
/
/
UCA0STE
3
P3.4/UCA0TXD/
/
/
UCA0SIMO
4
P3.5/UCA0RXD/
/
/
UCA0SOMI
5
FUNCTION
P3.0 (I/O)
UCB0STE/UCA0CLK (see Notes 1 and 2)
P3.1 (I/O)
UCB0SIMO/UCB0SDA (see Notes 1, 2 and 3)
P3.2 (I/O)
UCB0SOMI/UCB0SCL (see Notes 1, 2 and 3)
P3.3 (I/O)
UCB0CLK/UCA0STE (see Notes 1 and 2)
P3.4 (I/O)
UCA0TXD/UCA0SIMO (see Notes 1 and 2)
P3.5 (I/O)
UCA0RXD/UCA0SOMI (see Notes 1 and 2)
CONTROL BITS / SIGNALS
P3DIR.x
P3SEL.x
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
I: 0; O: 1
0
X
1
NOTES: 1. X: Don’t care.
2. The pin direction is controlled by the USCI module.
3. In case the I2C functionality is selected the output drives only the logical 0 to VSS level.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
53
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
Port P3 pin schematic: P3.6 to P3.7, input/output with Schmitt-trigger
Pad Logic
P3REN.x
P3DIR.x
0
0
1
P3OUT.x
0
Module X OUT
DVSS
0
DVCC
1
1
Direction
0: Input
1: Output
1
P3.6
P3.7
P3SEL.x
P3IN.x
EN
Module X IN
D
Port P3.6 to P3.7 pin functions
PIN NAME (P3.X)
X
FUNCTION
P3DIR.x
P3SEL.x
P3.6
6
P3.6 (I/O)
I: 0; O: 1
0
P3.7
7
P3.7 (I/O)
I: 0; O: 1
0
54
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
Port P4 pin schematic: P4.0 to P4.7, input/output with Schmitt-trigger
Pad Logic
P4REN.x
P4DIR.x
0
0
Module X OUT
1
0
DVCC
1
1
Direction
0: Input
1: Output
1
P4OUT.x
DVSS
P4.0/TB0
P4.1/TB1
P4.2/TB2
P4.3/TB0
P4.4/TB1
P4.5/TB2
P4.6/TBOUTH/ACLK
P4.7/TBCLK/
TBINCLK
P4SEL.x
P4IN.x
EN
Module X IN
D
Port P4.0 to P4.7 pin functions
PIN NAME (P4.X)
(P4 X)
P4.0/TB0
/
P4.1/TB1
/
P4.2/TB2
/
P4.3/TB0
/
P4.4/TB1
/
P4.5/TB2
/
P4.6/TBOUTH/ACLK
/
/
P4.7/TBCLK
/
X
0
1
2
3
4
5
6
7
FUNCTION
CONTROL BITS / SIGNALS
P4DIR.x
P4SEL.x
I: 0; O: 1
0
Timer_B3.CCI0A
0
1
Timer_B3.OUT0
1
1
I: 0; O: 1
0
Timer_B3.CCI1A
0
1
Timer_B3.OUT1
1
1
I: 0; O: 1
0
Timer_B3.CCI2A
0
1
Timer_B3.OUT2
1
1
I: 0; O: 1
0
Timer_B3.CCI0B
0
1
Timer_B3.OUT0
1
1
I: 0; O: 1
0
Timer_B3.CCI1B
0
1
Timer_B3.OUT1
1
1
P4.0 (I/O)
P4.1 (I/O)
P4.2 (I/O)
P4.3 (I/O)
P4.4 (I/O)
P4.5 (I/O)
I: 0; O: 1
0
N/A
0
1
Timer_B3.OUT2
1
1
P4.6 (I/O)
I: 0; O: 1
0
Timer_B3.TBOUTH
0
1
ACLK
1
1
I: 0; O: 1
0
0
1
P4.7 (I/O)
Timer_B3.TBCLK
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
55
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
APPLICATION INFORMATION
JTAG pins TMS, TCK, TDI/TCLK, TDO/TDI, input/output with Schmitt-trigger
TDO
Controlled by JTAG
Controlled by JTAG
JTAG
TDO/TDI
Controlled
by JTAG
DVCC
DVCC
TDI
Fuse
Burn & Test
Fuse
Test
TDI/TCLK
&
Emulation
Module
DVCC
TMS
TMS
DVCC
During Programming Activity and
During Blowing of the Fuse, Pin
TDO/TDI Is Used to Apply the Test
Input Data for JTAG Circuitry
TCK
TCK
56
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
APPLICATION INFORMATION
JTAG fuse check mode
MSP430F23x0 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the
continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When activated,
a fuse check current, ITF, of 1 mA at 3 V, 2.5 mA at 5 V can flow from the TDI/TCLK pin to ground if the fuse
is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing overall
system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if the
TMS is being held low during power up. The second positive edge on the TMS pin deactivates the fuse check
mode. After deactivation, the fuse check mode remains inactive until another POR occurs. After each POR the
fuse check mode has the potential to be activated.
The fuse check current will only flow when the fuse check mode is active and the TMS pin is in a low state (see
Figure 30). Therefore, the additional current flow can be prevented by holding the TMS pin high (default
condition).
Time TMS Goes Low After POR
TMS
ITDI/TCLK
ITF
Figure 30. Fuse Check Mode Current
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
57
MSP430F23x0
MIXED SIGNAL MICROCONTROLLER
SLAS518A -- AUGUST 2006 -- REVISED MAY 2007
Data Sheet Revision History
LITERATURE
NUMBER
SUMMARY
SLAS518
Preliminary PRODUCT PREVIEW data sheet release.
SLAS518A
PRODUCTION DATA data sheet release.
58
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
MSP430F2330IRHAR
ACTIVE
QFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2330IRHAT
ACTIVE
QFN
RHA
40
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2330TRHAR
ACTIVE
QFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2330TRHAT
ACTIVE
QFN
RHA
40
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2350IRHAR
ACTIVE
QFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2350IRHAT
ACTIVE
QFN
RHA
40
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2350TRHAR
ACTIVE
QFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2350TRHAT
ACTIVE
QFN
RHA
40
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2370IRHAR
ACTIVE
QFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2370IRHAT
ACTIVE
QFN
RHA
40
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2370TRHAR
ACTIVE
QFN
RHA
40
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
MSP430F2370TRHAT
ACTIVE
QFN
RHA
40
250
CU NIPDAU
Level-3-260C-168 HR
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-May-2007
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
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dsp.ti.com
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logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
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