Hitachi HD66765 396-channel segment driver with internal ram for 4096-color display Datasheet

—PRELIMINARY—
HD66765
396-channel Segment Driver with Internal RAM for 4096-color
Displays
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Target Specification
Rev.0.1
January, 2001
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Description
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The HD66765, 396-channel segment driver LSI, displays 132RGB-by-176-dot graphics on STN
displays in 4096 colors. It is for driving STN color LCD displays to a maximum of 132RGB by 176
dots, in combination with the HD66764 common driver. The HD66765’s bit-operation functions, 16bit high-speed bus interface, and high-speed RAM-write functions enable efficient data transfer and
high-speed rewriting of data to the graphics RAM.
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The HD66765 and HD66764 have various functions for reducing the power consumption of an LCD
system. The HD66765 has a low-voltage operation (1.8 V min.) and an internal RAM to display a
maximum of 132RGB-by-176-dot color, and the HD66764 has a step-up circuit to generate the LCDdrive voltage, a bleeder resistor for the drive interface with the LCD, and voltage-followers. Since the
HD66765 incorporates a circuit that interfaces with the HD66764, it can set instructions for the
HD66764. In addition, precise power control can be achieved by combining these hardware functions
with software functions, such as a partial display that only requires a low drive-voltage duty, and
standby and sleep modes. This LSI is suitable for any medium-sized or small portable battery-driven
product requiring long-term driving capabilities, such as digital cellular phones supporting a WWW
browser, bidirectional pagers, and small PDAs.
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Features
•
•
•
•
•
•
132RGB x 176-dot graphics display LCD controller/driver for 4,096 STN colors (when HD66764
is used)
Low-voltage drive and flickerless PWM grayscale drive
16-/8-bit high-speed bus interface and serial peripheral interface (SPI)
High-speed burst-RAM write function
Writing to a window-RAM address area by using a window-address function
Bit-operation functions for graphics processing:
 Write-data mask function in bit units
 Logical operation in pixel unit and conditional write function
HD66765
•
Various color-display control functions:
 4,096 out of 13,824 possible colors can be displayed at the same time (grayscale palette
included)
 Vertical scroll display function in raster-row units
•
Low-power operation supports:
 Vcc = 1.8 to 3.6 V (low-voltage range)
 VLCD = 2.0 to 4.0 V (liquid crystal drive voltage)
 Power-save functions such as the standby mode and sleep mode
 Partial LCD drive of two screens in any position
 Programmable drive duty ratios (1/16–1/176) and bias values (1/4–1/13) displayed on LCD
 Maximum 12-times step-up circuit for liquid crystal drive voltage (HD66764)
 Voltage followers to decrease direct current flow in the LCD drive bleeder-resistors
(HD66764)
 128-step contrast adjuster (HD66764)
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•
Built-in circuit for interfacing with the HD66764 common driver
•
Maximum 132RGB-by-176-dot display in combination with the HD66764 common driver
•
Internal RAM capacity: 34,848 bytes
•
396-segment liquid crystal display driver
•
n-raster-row AC liquid-crystal drive (C-pattern waveform drive)
•
Internal oscillation and hardware reset
•
Shift change of segment driver
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Type Number
Type Number
External Appearance
HD66765TB0
Bending TCP
HCD66765BP
Au-bump chip
2
Preliminary
HD66765 Block Diagram
OSC1 OSC2
Vcc
Index register
(IR)
IM2-1,
IM0/ID
7
CS*
16
Address counter
(AC)
System
interface
- 16 bits
- 8 bits
- Serial peripheral
(SPI)
RS
E/WR*/SCL
12
Read data
latch
16
Write data
latch
12
Segment driver
in
Latch circuit
TEST
Sp
Grayscale selection circuit
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RESET*
Latch circuit
Graphics RAM
(GRAM)
34,848 bytes
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48
CCS*
Common driver
interface
(serial)
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16
12
16
CDA
Timing generator
Bit operation
16
CCL
CL1
FLM
M
DISPTMG
DCCLK
12
RW/RD*
DB0/SDI,
DB1/SDO,
to DB15
CPG
Control register
(CR)
Palette register
(PK)
PWM grayscale circuit
GND
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VSH
VSL
Pr
3
SEG1
to SEG396
HD66765
HD66765 PAD Arrangement
SEG76
SEG75
SEG12
SEG11
No.1 No.500
DUMMY1
SEG10
SEG9
DUMMY42
SEG77
SEG78
No.2
- Chip size : 13.22mm x 3.85mm
- Chip thickness : 550um (typ.)
- PAD coordinate : PAD center
- Coordinate origine : Chip center
No.433
SEG2
SEG1
SEG91
SEG92
SEG93
SEG94
DUMMY2
DUMMY3
- Au bump size :
(1) 80um x 80 um
DUMMY1, DUMMY2-DUMMY39,
DUMMY40, DUMMY41, DUMMY42
No.435 No.434
DUMMY16
DUMMY17
RESET
DB15
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DB14
(2) 35um x 80um
SEG304-SEG93
DB13
DB12
DB11
DB10
(3) 80um x 35um
SEG386-SEG321,
SEG76-SEG11
DB9
DB8
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GNDDUM1
DB7
(4) 45um x 80um
SEG10-SEG1, SEG396-SEG387,
SEG320-SEG305, SEG92-SEG77
DB6
DB5
DB4
DB3
DB2
- Au bump pitch : Refer PAD coordinate
- Au bump height : 15um (typ.)
DB1/SDO
DB0/SDI
RW/RD*
E/WR*/SCL
p
S HD66765
RS
CS*
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GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
(Top View)
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
in
Y
VSH
VSH
VSH
VSH
VSH
VSH
lim
X
OSC2
re
OSC1
GNDDUM2
IM2
IM1
P
IM0/ID
VccDUM1
TEST
DCCLK
CL1
FLM
M
DISPTMG
CCS
CCL
CDA
RESET
DUMMY38
DUMMY39
TYPE CODE
HD66765
DUMMY18
DUMMY19
SEG303
SEG304
SEG305
SEG306
SEG396
SEG395
No.121
No.190
SEG388
SEG387
SEG319
SEG320
DUMMY40
DUMMY41
SEG321
SEG322
4
No.123
SEG385
SEG386
No.122
No.188 No.189
HD66765
HD66765 PAD Coordinate
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
PAD Name
DUMMY1
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
DUMMY2
DUMMY3
DUMMY4
DUMMY5
DUMMY6
DUMMY7
DUMMY8
DUMMY9
DUMMY10
DUMMY11
DUMMY12
DUMMY13
DUMMY14
DUMMY15
DUMMY16
DUMMY17
RESET*
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
GNDDUM1
DB7
DB6
DB5
DB4
DB3
DB2
DB1/SDO
DB0/SDI
RW/RD*
E/WR*/SCL
RS
CS*
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VCC
VCC
VCC
VCC
VSH
VSH
VSH
VSH
VSH
VSH
OSC2
OSC1
GNDDUM2
IM2
IM1
IM0/ID
VCCDUM1
TEST
DCCLK
CL1
FLM
M
DISPTMG
CCS
CCL
CDA
RESET*
DUMMY18
DUMMY19
DUMMY20
DUMMY21
DUMMY22
DUMMY23
DUMMY24
DUMMY25
DUMMY26
DUMMY27
DUMMY28
X
-6480
-6234
-6174
-6113
-6053
-5993
-5933
-5873
-5813
-5753
-5693
-5505
-5405
-5305
-5205
-5105
-5005
-4905
-4805
-4705
-4605
-4504
-4404
-4304
-4204
-4104
-4004
-3874
-3743
-3613
-3483
-3352
-3222
-3091
-2961
-2831
-2731
-2631
-2500
-2370
-2239
-2109
-1979
-1848
-1718
-1587
-1457
-1327
-1196
-1066
-966
-866
-766
-666
-565
-465
-365
-265
-165
-65
65
165
265
365
465
565
696
796
896
996
1096
1196
1327
1457
1557
1657
1787
1918
2018
2118
2248
2379
2509
2640
2770
2900
3031
3161
3292
3422
3522
3622
3722
3822
3922
4022
4122
4222
4322
4422
Y
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
No.
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
PAD Name
DUMMY29
DUMMY30
DUMMY31
DUMMY32
DUMMY33
DUMMY34
DUMMY35
DUMMY36
DUMMY37
DUMMY38
DUMMY39
SEG396
SEG395
SEG394
SEG393
SEG392
SEG391
SEG390
SEG389
SEG388
SEG387
DUMMY40
SEG386
SEG385
SEG384
SEG383
SEG382
SEG381
SEG380
SEG379
SEG378
SEG377
SEG376
SEG375
SEG374
SEG373
SEG372
SEG371
SEG370
SEG369
SEG368
SEG367
SEG366
SEG365
SEG364
SEG363
SEG362
SEG361
SEG360
SEG359
SEG358
SEG357
SEG356
SEG355
SEG354
SEG353
SEG352
SEG351
SEG350
SEG349
SEG348
SEG347
SEG346
SEG345
SEG344
SEG343
SEG342
SEG341
SEG340
SEG339
SEG338
SEG337
SEG336
SEG335
SEG334
SEG333
SEG332
SEG331
SEG330
SEG329
SEG328
SEG327
SEG326
SEG325
SEG324
SEG323
SEG322
SEG321
DUMMY41
SEG320
SEG319
SEG318
SEG317
SEG316
SEG315
SEG314
SEG313
SEG312
SEG311
SEG310
Y
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1795
-1626
-1576
-1526
-1476
-1426
-1376
-1326
-1276
-1226
-1176
-1126
-1076
-1026
-975
-925
-875
-825
-775
-725
-675
-625
-575
-525
-475
-425
-375
-325
-275
-225
-175
-125
-75
-25
25
75
125
175
225
275
325
375
425
475
525
575
625
675
725
775
825
875
925
975
1026
1076
1126
1176
1226
1276
1326
1376
1426
1476
1526
1576
1626
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
No.
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
PAD Name
SEG309
SEG308
SEG307
SEG306
SEG305
SEG304
SEG303
SEG302
SEG301
SEG300
SEG299
SEG298
SEG297
SEG296
SEG295
SEG294
SEG293
SEG292
SEG291
SEG290
SEG289
SEG288
SEG287
SEG286
SEG285
SEG284
SEG283
SEG282
SEG281
SEG280
SEG279
SEG278
SEG277
SEG276
SEG275
SEG274
SEG273
SEG272
SEG271
SEG270
SEG269
SEG268
SEG267
SEG266
SEG265
SEG264
SEG263
SEG262
SEG261
SEG260
SEG259
SEG258
SEG257
SEG256
SEG255
SEG254
SEG253
SEG252
SEG251
SEG250
SEG249
SEG248
SEG247
SEG246
SEG245
SEG244
SEG243
SEG242
SEG241
SEG240
SEG239
SEG238
SEG237
SEG236
SEG235
SEG234
SEG233
SEG232
SEG231
SEG230
SEG229
SEG228
SEG227
SEG226
SEG225
SEG224
SEG223
SEG222
SEG221
SEG220
SEG219
SEG218
SEG217
SEG216
SEG215
SEG214
SEG213
SEG212
SEG211
SEG210
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Pr
X
4522
4623
4723
4823
4923
5023
5123
5223
5323
5423
5523
5693
5753
5813
5873
5933
5993
6053
6113
6174
6234
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6480
6234
6174
6113
6053
5993
5933
5873
5813
5753
5693
5633
X
5573
5513
5453
5393
5333
5278
5228
5178
5128
5078
5028
4978
4928
4877
4827
4777
4727
4677
4627
4577
4527
4477
4427
4377
4327
4277
4227
4177
4127
4077
4027
3977
3927
3877
3827
3777
3727
3677
3627
3577
3527
3477
3427
3377
3327
3277
3227
3177
3127
3077
3027
2977
2926
2876
2826
2776
2726
2676
2626
2576
2526
2476
2426
2376
2326
2276
2226
2176
2126
2076
2026
1976
1926
1876
1826
1776
1726
1676
1626
1576
1526
1476
1426
1376
1326
1276
1226
1176
1126
1076
1026
975
925
875
825
775
725
675
625
575
No.
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
PAD Name
SEG209
SEG208
SEG207
SEG206
SEG205
SEG204
SEG203
SEG202
SEG201
SEG200
SEG199
SEG198
SEG197
SEG196
SEG195
SEG194
SEG193
SEG192
SEG191
SEG190
SEG189
SEG188
SEG187
SEG186
SEG185
SEG184
SEG183
SEG182
SEG181
SEG180
SEG179
SEG178
SEG177
SEG176
SEG175
SEG174
SEG173
SEG172
SEG171
SEG170
SEG169
SEG168
SEG167
SEG166
SEG165
SEG164
SEG163
SEG162
SEG161
SEG160
SEG159
SEG158
SEG157
SEG156
SEG155
SEG154
SEG153
SEG152
SEG151
SEG150
SEG149
SEG148
SEG147
SEG146
SEG145
SEG144
SEG143
SEG142
SEG141
SEG140
SEG139
SEG138
SEG137
SEG136
SEG135
SEG134
SEG133
SEG132
SEG131
SEG130
SEG129
SEG128
SEG127
SEG126
SEG125
SEG124
SEG123
SEG122
SEG121
SEG120
SEG119
SEG118
SEG117
SEG116
SEG115
SEG114
SEG113
SEG112
SEG111
SEG110
X
525
475
425
375
325
275
225
175
125
75
25
-25
-75
-125
-175
-225
-275
-325
-375
-425
-475
-525
-575
-625
-675
-725
-775
-825
-875
-925
-975
-1026
-1076
-1126
-1176
-1226
-1276
-1326
-1376
-1426
-1476
-1526
-1576
-1626
-1676
-1726
-1776
-1826
-1876
-1926
-1976
-2026
-2076
-2126
-2176
-2226
-2276
-2326
-2376
-2426
-2476
-2526
-2576
-2626
-2676
-2726
-2776
-2826
-2876
-2926
-2977
-3027
-3077
-3127
-3177
-3227
-3277
-3327
-3377
-3427
-3477
-3527
-3577
-3627
-3677
-3727
-3777
-3827
-3877
-3927
-3977
-4027
-4077
-4127
-4177
-4227
-4277
-4327
-4377
-4427
Y
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
No.
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
UNIT: m Rev 0.1
PAD Name
X
SEG109
-4477
SEG108
-4527
SEG107
-4577
SEG106
-4627
SEG105
-4677
SEG104
-4727
SEG103
-4777
SEG102
-4827
SEG101
-4877
SEG100
-4928
SEG99
-4978
SEG98
-5028
SEG97
-5078
SEG96
-5128
SEG95
-5178
SEG94
-5228
SEG93
-5278
SEG92
-5333
SEG91
-5393
SEG90
-5453
SEG89
-5513
SEG88
-5573
SEG87
-5633
SEG86
-5693
SEG85
-5753
SEG84
-5813
SEG83
-5873
SEG82
-5933
SEG81
-5993
SEG80
-6053
SEG79
-6113
SEG78
-6174
SEG77
-6234
DUMMY42
-6480
SEG76
-6480
SEG75
-6480
SEG74
-6480
SEG73
-6480
SEG72
-6480
SEG71
-6480
SEG70
-6480
SEG69
-6480
SEG68
-6480
SEG67
-6480
SEG66
-6480
SEG65
-6480
SEG64
-6480
SEG63
-6480
SEG62
-6480
SEG61
-6480
SEG60
-6480
SEG59
-6480
SEG58
-6480
SEG57
-6480
SEG56
-6480
SEG55
-6480
SEG54
-6480
SEG53
-6480
SEG52
-6480
SEG51
-6480
SEG50
-6480
SEG49
-6480
SEG48
-6480
SEG47
-6480
SEG46
-6480
SEG45
-6480
SEG44
-6480
SEG43
-6480
SEG42
-6480
SEG41
-6480
SEG40
-6480
SEG39
-6480
SEG38
-6480
SEG37
-6480
SEG36
-6480
SEG35
-6480
SEG34
-6480
SEG33
-6480
SEG32
-6480
SEG31
-6480
SEG30
-6480
SEG29
-6480
SEG28
-6480
SEG27
-6480
SEG26
-6480
SEG25
-6480
SEG24
-6480
SEG23
-6480
SEG22
-6480
SEG21
-6480
SEG20
-6480
SEG19
-6480
SEG18
-6480
SEG17
-6480
SEG16
-6480
SEG15
-6480
SEG14
-6480
SEG13
-6480
SEG12
-6480
SEG11
-6480
Y
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1626
1576
1526
1476
1426
1376
1326
1276
1226
1176
1126
1076
1026
975
925
875
825
775
725
675
625
575
525
475
425
375
325
275
225
175
125
75
25
-25
-75
-125
-175
-225
-275
-325
-375
-425
-475
-525
-575
-625
-675
-725
-775
-825
-875
-925
-975
-1026
-1076
-1126
-1176
-1226
-1276
-1326
-1376
-1426
-1476
-1526
-1576
-1626
n
o
i
t
a
c
i
if
c
e
p
S
5
Y
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
1795
HD66765
Pin Functions
Table 1
Signals
IM2-1,
IM0/ID
Pin Functional Description
Number of
Pins
I/O
Connected to
Functions
3
GND or VCC
Selects the MPU interface mode:
I
IM2
GND
GND
GND
GND
Vcc
IM1 IM0/ID MPU interface mode
GND GND 68-system 16-bit bus interface
GND Vcc 68-system 8-bit bus interface
Vcc GND 80-system 16-bit bus interface
Vcc
Vcc 80-system 8-bit bus interface
GND ID
Serial peripheral interface (SPI)
n
o
ti
When a serial interface is selected, the IM0 pin is
used as the ID setting for a device code.
CS*
1
I
MPU
RS
1
I
MPU
E/WR*/SCL
1
I
MPU
RW/RD*
DB0/SDI
e
r
P
1
in
lim
1
I
I/O
y
r
a
a
c
fi
Selects the HD66765:
Low: HD66765 is selected and can be accessed
High: HD66765 is not selected and cannot be
accessed
Must be fixed at GND level when not in use.
i
c
e
Selects the register.
Low: Index/status
High: Control
p
S
For a 68-system bus interface, serves as an enable
signal to activate data read/write operation.
For an 80-system bus interface, serves as a write
strobe signal and writes data at the low level.
For a synchronous clock interface, serves as the
synchronous clock signal.
MPU
For a 68-system bus interface, serves as a signal to
select data read/write operation.
Low: Write
High: Read
For an 80-system bus interface, serves as a read
strobe signal and reads data at the low level.
MPU
Serves as a 16-bit bidirectional data bus.
For an 8-bit bus interface, data transfer uses DB15DB8; fix unused DB7-DB0 to the Vcc or GND level.
For a clock-synchronous serial interface, serves as
the serial data input pin (SDI). The input level is read
on the rising edge of the SCL signal.
6
HD66765
Table 1
Pin Functional Description (cont)
Signals
Number of
Pins
I/O
Connected to
Functions
DB1/SDO
1
MCU
Serves as a 16-bit bidirectional data bus.
For an 8-bit bus interface, data transfer uses DB15DB8; fix unused DB7-DB0 to the Vcc or GND level.
I/O
For a clock-synchronous serial interface, serves as a
serial data output pin (SDO). Successive bit values
are output on the falling edge of the SCL signal.
DB2-DB15 14
SEG1–SE
G396
396
I/O
O
MPU
LCD
n
o
Serves as a 16-bit bidirectional data bus.
For an 8-bit bus interface, data transfer uses DB15DB8; fix unused DB7-DB0 to the Vcc or GND level.
i
t
a
c
i
if
Output signals for segment drive. In the display-off
period (D1–0 = 00, 01) or standby mode (STB = 1), all
pins output GND level.
The SGS bit can change the shift direction of the
segment signal. For example, if SGS = 0, RAM
address 0000 is output from SEG1. If SGS = 1, it is
output from SEG396.
SEG1, SEG4, SEG7, ... display red (R), SEG2, SEG5,
SEG8, ... display green (G), and SEG3, SEG6,
SEG9, ... display blue (B) (SGS = 0).
c
e
p
CL1
1
O
M
1
O
FLM
1
O
DISPTMG
1
DCCLK
CCL
CDA
CCS*
y
r
a
HD66764
in
S
The one-raster-row-cycle pulse is output.
HD66764
The AC-cycle signal is output.
HD66764
The frame-start pulse is output.
HD66764
Outputs the display period signal.
O
HD66764
Outputs clocks for the step-up.
O
HD66764
Clock signal for a serial transfer of register setting
values to the common driver. Data is output on the
falling edge of this clock.
1
O
HD66764
Data signal for serial transfer as register setting values
to the common driver.
1
O
HD66764
e
r
P
lim
1
1
O
Chip-select for the HD66764.
Low: the HD66764 is selected and can receive a serial
transfer.
High: the HD66764 is not selected and cannot receive
a serial transfer.
VSH
1
I
HD66764
Input for the LCD-drive voltage for the segment driver,
which can be provided by the HD66764’s on-chip
power supply. VSH ≤ 4.0 V
VCC, GND
2
—
Power supply
VCC: + 1.8 V to + 3.6 V; GND (logic): 0
7
HD66765
Table 1
Pin Functional Description (cont)
Signals
Number of
Pins
I/O
Connected to
Functions
OSC1,
OSC2
2
I or O Oscillationresistor
RESET*
1
I
MPU or external Reset pin. Initializes the LSI when low. Must be reset
R-C circuit
after power-on.
VccDUM
O
Input pins
Outputs the internal VCC level; shorting this pin sets
the adjacent input pin to the VCC level.
GNDDUM
O
Input pins
Outputs the internal GND level; shorting this pin sets
the adjacent input pin to the GND level.
Dummy
—
—
Dummy pad. Must be left disconnected.
I
GND
Test pin. Must be fixed at GND level.
TEST
1
Connect an external resistor for R-C oscillation.
When providing clocks from outside, open OSC2.
n
o
ti
a
c
fi
i
c
e
y
r
a
p
S
in
im
l
e
r
P
8
HD66765
Block Function Description
System Interface
The HD66765 has five high-speed system interfaces: an 80-system 16-bit/8-bit bus, a 68-system 16-bit/8bit bus, and a serial peripheral (SPI: Serial Peripheral Interface port). The interface mode is selected by
the IM2-0 pins.
The HD66765 has three 16-bit registers: an index register (IR), a write data register (WDR), and a read
data register (RDR). The IR stores index information from the control registers and the GRAM. The
WDR temporarily stores data to be written into control registers and the GRAM, and the RDR
temporarily stores data read from the GRAM. Data written into the GRAM from the MPU is first written
into the WDR and then is automatically written into the GRAM by internal operation. Data is read
through the RDR when reading from the GRAM, and the first read data is invalid and the second and the
following data are normal. When a logic operation is performed inside of the HD66765 by using the
display data set in the GRAM and the data written from the MPU, the data read through the RDR is used.
Accordingly, the MPU does not need to read data twice nor to fetch the read data into the MPU. This
enables high-speed processing.
n
o
i
t
a
c
i
if
c
e
p
S
Execution time for instruction excluding oscillation start is 0 clock cycle and instructions can be written
in succession.
Table 2
WR
RD
0
1
0
1
R/W
RS
Operations
0
0
Writes indexes into IR
1
0
Reads internal status
1
0
1
Writes into control registers and GRAM through WDR
0
1
1
Reads from GRAM through RDR
Pr
Table 3
in
68-system
Bus
im
l
e
80-system Bus
1
y
r
a
Register Selection (8/16 Parallel Interface)
0
Register Selection (Serial Peripheral Interface)
Start bytes
R/W Bits
RS Bits
Operations
0
0
Writes indexes into IR
1
0
Reads internal status
0
1
Writes into control registers and GRAM through WDR
1
1
Reads from GRAM through RDR
9
HD66765
Bit Operation
The HD66765 supports the following functions: a write data mask function that selects and writes data
into the GRAM in bit units, and a logic operation function that performs logic operations or conditional
determination on the display data set in the GRAM and writes into the GRAM. With the 16-bit bus
interface, these functions can greatly reduce the processing loads of the MPU graphics software and can
rewrite the display data in the GRAM at high speed. For details, see the Graphics Operation Function
section.
Address Counter (AC)
n
o
ti
The address counter (AC) assigns addresses to the GRAM. When an address set instruction is written into
the IR, the address information is sent from the IR to the AC.
a
c
fi
After writing into the GRAM, the AC is automatically incremented by 1 (or decremented by 1). After
reading from the data, the AC is not updated. A window address function allows for data to be written
only to a window area specified by GRAM.
i
c
e
Graphics RAM (GRAM)
p
S
The graphics RAM (GRAM) has eight bits/pixel and stores the bit-pattern data of 132 x 176 bytes.
y
r
a
PWM Grayscale Circuit
The PWM grayscale circuit generates a PWM signal that corresponds to the grayscale levels as specified
in the grayscale palette register. Any 4096 out of 13,824 possible colors can be displayed at the same
time. For details, see the Grayscale Palette section.
in
im
l
e
Grayscale Selection Circuit
r
P
The grayscale selection circuit reads data from the GRAM and controls the signal generated in the PWM
grayscale circuit. PWM (pulse width modulation) is used to control each color in the display. For details,
see the Grayscale Palette section.
Timing Generator
The timing generator generates timing signals for the operation of internal circuits such as the GRAM.
The RAM read timing for display and internal operation timing by MPU access are generated separately
to avoid interference with one another. The timing generator generates the interface signals (M, FLM,
CL1, DISPTMG, and DCCLK) for the common driver.
Oscillation Circuit (OSC)
The HD66765 can provide R-C oscillation simply through the addition of an external oscillation-resistor
between the OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage, display
size, and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can also
be supplied externally. Since R-C oscillation stops during the standby mode, current consumption can be
reduced. For details, see the Oscillation Circuit section.
10
HD66765
Liquid Crystal Display Driver Circuit
The liquid crystal display driver circuit consists of 396 segment signal drivers (SEG1 to SEG396).
Display pattern data is latched when 396-bit data has arrived. The latched data then enables the segment
signal drivers to generate drive waveform outputs. The shift direction of 396-bit data can be changed by
the SGS bit by selecting an appropriate direction for the device mounting configuration.
When multiplexing drive is not used, or during standby mode, all of the common and segment signal
drivers listed above, and the common drivers from the HD66764, output the GND level, halting the
display.
n
o
i
t
a
Interface with Common Driver
A serial interface circuit provides an interface with the HD66764 common driver. When sending an
instruction setting from the HD66765 to a common driver, a register setting value from within the
HD66765 is transferred via the serial interface circuit. A transfer is started by setting a serial transfer
enable in the HD66765. However, transfer to and reading from the common driver are not possible
during standby. For details, see the Common Serial Transfer section.
c
i
if
c
e
p
y
r
a
S
in
im
l
e
Pr
11
HD66765
CMS=0
COM1
CMS=1
COM176
"0000"H
"0001"H
"0082"H
"0083"H
COM2
COM175
"0100"H
"0101"H
"0182"H
"0183"H
COM3
COM4
COM5
COM6
COM7
COM8
COM174
COM173
COM172
COM171
COM170
COM169
"0200"H
"0300"H
"0400"H
"0500"H
"0600"H
"0700"H
"0201"H
"0301"H
"0401"H
"0501"H
"0601"H
"0701"H
"0282"H
"0382"H
"0482"H
"0582"H
"0682"H
"0782"H
"0283"H
"0383"H
"0483"H
"0583"H
"0683"H
"0783"H
COM9
COM10
COM11
COM168
COM167
COM166
"0800"H
"0900"H
"0A00"H
"0801"H
"0901"H
"0A01"H
"0882"H
"0982"H
"0A82"H
"0883"H
"0983"H
"0A83"H
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM165
COM164
COM163
COM162
COM161
COM160
COM159
COM158
COM157
"0B00"H
"0C00"H
"0D00"H
"0E00"H
"0F00"H
"1000"H
"1100"H
"1200"H
"1300"H
"0B01"H
"0C01"H
"0D01"H
"0E01"H
"0F01"H
"1001"H
"1101"H
"1201"H
"1301"H
"0B82"H
"0C82"H
"0D82"H
"0E82"H
"0F82"H
"1082"H
"1182"H
"1282"H
"1382"H
"0B83"H
"0C83"H
"0D83"H
"0E83"H
"0F83"H
"1083"H
"1183"H
"1283"H
"1383"H
COM169
COM170
COM171
COM172
COM173
COM174
COM175
COM176
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
"A800"H
"A900"H
"AA00"H
"AB00"H
"AC00"H
"AD00"H
"AE00"H
"AF00"H
"A882"H
"A982"H
"AA82"H
"AB82"H
"AC82"H
"AD82"H
"AE82"H
"AF82"H
"A883"H
"A983"H
"AA83"H
"AB83"H
"AC83"H
"AD83"H
"AE83"H
"AF83"H
Table
GRAM
data
DB
11
DB
0
DB
11
y
r
a
in
im
l
e
r
P
DB
0
DB
11
DB
0
DB
11
DB
0
n
o
ti
a
c
fi
i
c
e
p
S
"A801"H
"A901"H
"AA01"H
"AB01"H
"AC01"H
"AD01"H
"AE01"H
"AF01"H
Relationship between GRAM data and output pin (SGS=0)
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
Selected
palette
N/A
PK palette
PK palette
PK palette
Output pin
N/A
SEG (3n+1)
SEG (3n+2)
SEG (3n+3)
DB
1
DB
0
n = Lower 6-bits address (0 to 131)
12
SEG396
SEG395
SEG394
SEG393
SEG392
SEG391
SEG6
SEG5
SEG4
SEG3
SEG/COM pins
SEG2
Relationship between GRAM address and display position (SGS=0)
SEG1
Table
HD66765
CMS=0
COM1
CMS=1
COM176
COM2
COM175
COM174
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM171
COM170
COM169
COM168
COM167
COM166
COM165
COM164
COM163
COM162
COM161
COM160
COM159
COM169
COM170
COM171
COM172
COM173
COM174
COM175
COM176
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
Table
GRAM
data
DB
11
COM173
COM172
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM158
COM157
DB
0
DB
0
DB
11
DB
0
DB
11
DB
0
"0083"H
"0082"H
"0001"H
"0000"H
"0183"H
"0182"H
"0101"H
"0100"H
"0283"H
"0383"H
"0483"H
"0583"H
"0683"H
"0783"H
"0282"H
"0382"H
"0482"H
"0582"H
"0682"H
"0782"H
"0201"H
"0301"H
"0401"H
"0501"H
"0601"H
"0701"H
"0200"H
"0300"H
"0400"H
"0500"H
"0600"H
"0700"H
"0883"H
"0983"H
"0A83"H
"0882"H
"0982"H
"0A82"H
"0801"H
"0901"H
"0A01"H
"0800"H
"0900"H
"0A00"H
"0B83"H
"0C83"H
"0D83"H
"0E83"H
"0F83"H
"1083"H
"1183"H
"1283"H
"1383"H
"0B82"H
"0C82"H
"0D82"H
"0E82"H
"0F82"H
"1082"H
"1182"H
"1282"H
"1382"H
"0B01"H
"0C01"H
"0D01"H
"0E01"H
"0F01"H
"1001"H
"1101"H
"1201"H
"1301"H
"0B00"H
"0C00"H
"0D00"H
"0E00"H
"0F00"H
"1000"H
"1100"H
"1200"H
"1300"H
"A801"H
"A901"H
"AA01"H
"AB01"H
"AC01"H
"AD01"H
"AE01"H
"AF01"H
"A800"H
"A900"H
"AA00"H
"AB00"H
"AC00"H
"AD00"H
"AE00"H
"AF00"H
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lim
"A883"H
"A983"H
"AA83"H
"AB83"H
"AC83"H
"AD83"H
"AE83"H
"AF83"H
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o
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t
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S
"A882"H
"A982"H
"AA82"H
"AB82"H
"AC82"H
"AD82"H
"AE82"H
"AF82"H
Relationship between GRAM data and output pin (SGS=1)
DB
15
DB
14
DB
13
DB
12
DB
11
DB
10
DB
9
DB
8
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
Selected
palette
N/A
PK palette
PK palette
PK palette
Output pin
N/A
SEG (396n-3n)
SEG (395-3n)
SEG (394-3n)
DB
0
n = Lower 6-bits address (0 to 131)
13
SEG396
SEG395
SEG394
SEG393
SEG392
SEG391
SEG6
DB
11
in
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P
SEG5
SEG4
SEG3
SEG/COM pins
SEG2
Relationship between GRAM address and display position (SGS=1)
SEG1
Table
HD66765
Instructions
Outline
The HD66765 uses the 16-bit bus architecture. Before the internal operation of the HD66765 starts,
control information is temporarily stored in the registers described below to allow high-speed interfacing
with a high-performance microcomputer. The internal operation of the HD66765 is determined by signals
sent from the microcomputer. These signals, which include the register selection signal (RS), the
read/write signal (R/W), and the data bus signals (DB15 to DB0), make up the HD66765 instructions.
There are nine categories of instructions that:
•
•
•
•
•
•
•
•
•
Specify the index
Read the status
Control the display
Control power management
Process the graphics data
Set internal GRAM addresses
Transfer data to and from the internal GRAM
Set grayscale level for the internal grayscale palette table
Interface with the common driver
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Normally, instructions that write data are used the most. However, an auto-update of internal GRAM
addresses after each data write can lighten the microcomputer program load.
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Because instructions are executed in 0 cycles, they can be written in succession.
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14
HD66765
Instruction Descriptions
Index
The index instruction specifies the RAM control indexes (R00h to R37h). It sets the register number in
the range of 00000 to 110111 in binary form. However, R40 to R44 are disabled since they are test
registers.
R/W
RS
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
W
0
*
*
*
*
*
*
*
*
*
ID6
ID5
ID4
ID3
Figure 1 Index Instruction
Status Read
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on
DB2
DB1
DB0
ID2
ID1
ID0
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The status read instruction reads the internal status of the HD66765.
L7–0: Indicate the driving raster-row position where the liquid crystal display is being driven.
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C6–0: Read the contrast setting values (CT6–0).
in
R/W
RS
DB15
DB14
DB13
DB12
DB11
R
0
L7
L6
L5
L4
L3
S
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
L2
L1
L0
0
C6
C5
C4
C3
C2
C1
C0
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Figure 2 Status Read Instruction
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Start Oscillation (R00h)
The start oscillation instruction restarts the oscillator from the halt state in the standby mode. After
issuing this instruction, wait at least 10 ms for oscillation to stabilize before issuing the next instruction.
(See the Standby Mode section.)
If this register is read forcibly, *765H is read.
R/W
RS
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
R
1
0
0
0
0
0
1
1
1
0
1
1
0
0
1
0
1
Figure 3 Start Oscillation Instruction
15
HD66765
Driver Output Control (R01h)
R/W
RS
DB15
DB14
DB13
DB12
DB11
DB10
W
1
0
0
0
0
0
0
DB9
DB8
CMS SGS
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
NL4
NL3
NL2
NL1
NL0
Figure 4 Driver Output Control Instruction
CMS: Selects the output shift direction of a common driver. When CMS = 0, COM1 shifts to COM176.
When CMS = 1, COM176 shifts to COM1.
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SGS: Selects the output shift direction of a segment. When SGS = 0, SEG1 shifts to SEG396 and
<R><G><B> color is assigned from SEG1. When SGS = 1, SEG396 shifts to SEG1 and <R><G><B>
color is assigned from SEG396. Re-write to the RAM when intending to change the SGS bit.
Note:
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The CMS bit is for setting the common driver. Control according to the bit’s value is executed by
the common driver. For details, see the data sheet for the common driver.
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NL4–0: Specify the LCD drive duty ratio. The duty ratio can be adjusted for every eight raster-rows.
GRAM address mapping does not depend on the setting value of the drive duty ratio.
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16
HD66765
Table 8
NL Bits and Drive Duty
NL4
NL3
NL2
NL1
NL0
Display Size
LCD Drive Duty
Common Driver
Used
0
0
0
0
0
Setting disabled
Setting disabled
Setting disabled
0
0
0
0
1
396 x 16 dots
1/16 Duty
COM1–COM16
0
0
0
1
0
396 x 24 dots
1/24 Duty
COM1–COM24
0
0
0
1
1
396 x 32 dots
1/32 Duty
COM1–COM32
0
0
1
0
0
396 x 40 dots
1/40 Duty
COM1–COM40
0
0
1
0
1
396 x 48 dots
1/48 Duty
COM1–COM48
0
0
1
1
0
396 x 56 dots
1/56 Duty
COM1–COM56
0
0
1
1
1
396 x 64 dots
1/64 Duty
0
1
0
0
0
396 x 72 dots
1/72 Duty
0
1
0
0
1
396 x 80 dots
1/80 Duty
0
1
0
1
0
396 x 88 dots
1/88 Duty
0
1
0
1
1
396 x 96 dots
1/96 Duty
COM1–COM96
0
1
1
0
0
396 x 104 dots
1/104 Duty
COM1–COM104
0
1
1
0
1
396 x 112 dots
1/112 Duty
COM1–COM112
0
1
1
1
0
396 x 120 dots
1/120 Duty
COM1–COM120
0
1
1
1
1
396 x 128 dots
1/128 Duty
COM1–COM128
1
0
0
0
0
396 x 136 dots
1/136 Duty
COM1–COM136
1
0
0
0
1
1/144 Duty
COM1–COM144
1
0
0
1
0
396 x 152 dots
1/152 Duty
COM1–COM152
1
0
0
lim
396 x 144 dots
1
396 x 160 dots
1/160 Duty
COM1–COM160
1
0
1
0
0
396 x 168 dots
1/168 Duty
COM1–COM168
1
0
0
1
396 x 176 dots
1/176 Duty
COM1–COM176
P
re
1
1
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COM1–COM64
COM1–COM72
COM1–COM80
COM1–COM88
HD66765
LCD-Driving-Waveform Control (R02h)
R/W
RS
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
W
1
0
0
0
0
0
0
B/C
EOR
0
0
DB5
DB4
DB3
DB2
DB1
DB0
NW5 NW4 NW3 NW2 NW1 NW0
Figure 5 LCD-Driving-Waveform Control Instruction
B/C: When B/C = 0, a B-pattern waveform is generated and alternates in every frame for LCD drive.
When B/C = 1, a C-pattern waveform is generated and alternates in each raster-row specified by bits
EOR and NW4–NW0 in the LCD-driving-waveform control register. For details, see the n-raster-row
Reversed AC Drive section.
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EOR: When the C-pattern waveform is set (B/C = 1) and EOR = 1, the odd/even frame-select signals and
the n-raster-row reversed signals are EORed for alternating drive. EOR is used when the LCD is not
alternated by combining the set values of the LCD drive duty ratio and the n raster-row. For details, see
the n-raster-row Reversed AC Drive section.
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NW5–0: Specify the number of raster-rows n that will alternate at the C-pattern waveform setting (B/C =
1). NW4–NW0 alternate for every set value + 1 raster-row, and the first to the 64th raster-rows can be
selected.
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Power Control 1 (R03h)
in
Power Control 2 (R0Ch)
R/W
RS
W
1
W
1
DB15
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DB14
Pr
DB13
DB12
DB11
DB10
DB9
DB8
DB7
0
BS2
BS1
BS0
BT3
BT2
BT1
BT0
0
0
0
0
0
0
0
0
0
0
DB6
DB5
DB4
DC2 DC1 DC0
0
0
0
DB3
DB2
DB1
DB0
AP1
AP0
SLP
STB
0
VC2
VC1
VC0
Figure 6 Power Control Instruction
BS2–0: The LCD drive bias value is set. The LCD drive bias value can be selected according to its drive
duty ratio and voltage.
BT3–0: The output factor of step-up is switched. The LCD drive voltage level can be selected according
to its drive duty ratio and bias. Lower amplification of the step-up circuit consumes less current.
DC2–0: The operating frequency in the step-up circuit is selected. When the step-up operating frequency
is high, the driving ability of the step-up circuit and the display quality become high, but the current
consumption is increased. Adjust the frequency considering the display quality and the current
consumption.
AP1–0: The amount of fixed current from the fixed current source in the operational amplifier for the
LCD is adjusted. When the amount of fixed current is large, the LCD driving ability and the display
quality become high, but the current consumption is increased. Adjust the fixed current considering the
display quality and the current consumption.
18
HD66765
During no display, when AP1–0 = 00, the current consumption can be reduced by ending the operational
amplifier and step-up circuit operation.
VC2-0: Sets an adjustment factor for the Vci voltage (VC2-0).
SLP: When SLP = 1, the HD66765 enters the sleep mode, where the internal display operations are
halted except for the R-C oscillator, thus reducing current consumption. Only the following instructions
can be executed during the sleep mode.
Power control (BS2–0, BT3–0, DC2–0, AP1–0, SLP, and STB bits)
Common interface control (TE, IDX)
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During the sleep mode, the other GRAM data and instructions cannot be updated although they are
retained.
Note:
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BS2-0, BT3-0, DC2-0, AP1-0, VC2-0 and SLP bits are for setting the common driver. Control
according to the bits’ values is executed by the common driver. For details, see the data sheet for
the common driver.
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STB: When STB = 1, the HD66765 enters the standby mode, where display operation completely stops,
halting all the internal operations including the internal R-C oscillator. Further, no external clock pulses
are supplied. For details, see the Standby Mode section.
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Only the following instructions can be executed during the standby mode.
in
a. Standby mode cancel (STB = 0)
b. Start oscillation
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During the standby mode, the GRAM data and instructions may be lost. To prevent this, they must be set
again after the standby mode is canceled. Serial transfer to the common driver is not possible when it is in
standby mode. Transfer the data again after it has been released from standby mode.
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Contrast Control (R04h)
R/W
RS
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
1
0
0
0
0
VR3
VR2
VR1
VR0
0
CT6
CT5
CT4
CT3
CT2
CT1
CT0
Figure 7 Contrast Control Instruction
CT6–0: These bits control the LCD drive voltage to adjust 128-step contrast. For details, see the Contrast
Adjuster section.
VR3–0: These bits adjust the output voltage in the LCD drive reference generator.
Note:
CT6-0 and VR3-0 bits are for setting the common driver. Control according to the bits’ values is
executed by the common driver. For details, see the data sheet for the common driver.
19
HD66765
Entry Mode (R05h)
Compare Register (R06h)
R/W
RS
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
1
0
0
0
0
0
0
HWM
0
0
0
I/D1
I/D0
AM
LG2
LG1
LG0
W
1
0
0
0
0
CP8
CP7
CP6
CP5
CP4
CP3
CP2
CP1
CP0
CP11 CP10 CP9
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Figure 8 Entry Mode and Compare Register Instruction
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The write data sent from the microcomputer is modified in the HD66765 and written to the GRAM. The
display data in the GRAM can be quickly rewritten to reduce the load of the microcomputer software
processing. For details, see the Graphics Operation Function section.
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HWM: When HWM=1, data can be written to the GRAM at high speed. In high-speed write mode, four
words of data are written to the GRAM in a single operation after writing to RAM four times. Write to
RAM four times, otherwise the four words cannot be written to the GRAM. Thus, set the lower 2 bits to 0
when setting the RAM address. For details, see High-Speed RAM Write Mode section.
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I/D1-0: When I/D1-0 = 1, the address counter (AC) is automatically incremented by 1 after the data is
written to the GRAM. When I/D1-0 = 0, the AC is automatically decremented by 1 after the data is
written to the GRAM. The increment/decrement setting of the address counter by I/D1-0 is done
independently for the upper (AD15-8) and lower (AD7-0) addresses. The direction of moving through the
addresses when the GRAM is written to is set by the AM bit.
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AM: Set the automatic update method of the AC after the data is written to the GRAM. When AM = 0,
the data is continuously written in parallel. When AM = 1, the data is continuously written vertically.
When window address range is specified, the GRAM in the window address range can be written to
according to the I/D1-0 and AM settings.
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20
HD66765
Direction
Settings
I/D1-0 = "00"
I/D1-0 = "01"
I/D1-0 = "10"
I/D1-0 = "11"
Horizontal: decrement
Vertical: decrement
Horizontal: increment
Vertical: decrement
Horizontal: decrement
Vertical: increment
Horizontal: increment
Vertical: increment
0000h
0000h
0000h
0000h
AM = "0"
Horizontal
AF83h
AF83
AF83h
0000h
0000h
0000h
AM = "1"
Vertical
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AF83h
AF83h
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AF83h
0000h
AF83h
AF83h
Note: When a window address range has been set, the GRAM can only be witten to within that range.
Figure 9 Address Direction Settings
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LG2–0: Compare the data read from the GRAM by the microcomputer with the compare registers
(CP7–0) by a compare/logical operation and write the results to GRAM. For details, see the
Logical/Compare Operation Function.
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CP11–0: Set the compare register for the compare operation with the data read from the GRAM or
written by the microcomputer.
Write data sent
from the
microcomputer
(DB11-0)
Logical/compare
operation
(LG2-0)
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Write data mask *
(WM11-0)
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
1
1
1
0
0
1
1
1
0
Logical operaion (with read data and write data)
LG2-0 = "000" Replace
LG2-0 = "001" OR
LG2-0 = "010" AND
LG2-0 = "011" EOR
Compare operaion (with compare register)
LG2-0 = "100" Replacement of matched readdata
LG2-0 = "101" Replacement of unmatched read data
LG2-0 = "110" Replacement of matched write data
LG2-0 = "111" Replacement of ummatched write data
Write data mask (WM11-0)
GRAM
Note : The write data mask (WM11-0) is set by the register in the RAM Write Data Mask section.
Figure 10 Logical/Compare Operation and Swapping for the GRAM
21
HD66765
Display Control (R07h)
R/W
RS
DB15
DB14
DB13
DB12
DB11
W
1
0
0
0
0
0
DB10
DB9
DB8
VLE2 VLE1 SPT
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
REV
D1
D0
Figure 11 Display Control Instruction
VLE2–1: When VLE1 = 1, a vertical scroll is performed in the 1st screen. When VLE2 = 1, a vertical
scroll is performed in the 2nd screen. Vertical scrolling on the two screens can be independently
controlled.
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SPT: When SPT = 1, the 2-division LCD drive is performed. For details, see the Screen-division Driving
Function section.
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REV: Displays all character and graphics display sections with reversal when REV = 1. For details, see
the Reversed Display Function section. Since the grayscale level can be reversed, display of the same
data is enabled on normally-white and normally-black panels.
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D1–0: Display is on when D1 = 1 and off when D1 = 0. When off, the display data remains in the
GRAM, and can be displayed instantly by setting D1 = 1. When D1 is 0, the display is off with all of the
SEG/COM pin outputs set to the GND level. Because of this, the HD66765 can control the charging
current for the LCD with AC driving.
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When D1–0 = 01, the internal display of the HD66765 is performed although the display is off. When
D1-0 = 00, the internal display operation halts and the display is off.
Table 9
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D Bits and Operation
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SEG/COM Output
HD66765 Internal Display
Operation
Master/Slave Signal (CL1,
FLM, M, and DISPTMG)
GND
Halt
Halt
GND
Operate
Operate
0
Unlit display
Operate
Operate
1
Display
Operate
Operate
D1
D0
0
0
0
1
1
1
Notes: 1. Writing from the microcomputer to the GRAM is independent from D1–0.
2. In the sleep and standby modes, D1–0 = 00. However, the register contents of D1–0 are not
modified.
Note:
SPT and D1 bits are for setting the common driver. Control according to the bits’ values is
executed by the common driver. For details, see the data sheet for the common driver.
22
HD66765
COM Driver Interface Control (R0Ah)
R/W
RS
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
1
0
0
0
0
0
0
0
TE
0
0
0
0
0
IDX2 IDX1 IDX0
R
1
0
0
0
0
0
0
0
TE
0
0
0
0
0
IDX2 IDX1 IDX0
Figure 12 COM Driver Interface Control Instruction
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IDX2-0: Index bits that select instructions for the common driver. The instruction that corresponds to the
setting made here is transferred, with the index, to the common driver via the serial interface. These
instructions are transferred in bit rows as shown below. The upper 3 bits correspond to IDX2-0. The
IDX2-0 setting at the time of transfer selects the instruction for the common driver as listed below.
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To change an instruction setting on the common driver, first change the instruction bit on the HD66765,
select the instruction, which includes the changed instruction bit, from the list below, by setting IDX2-0
as required. The instruction is transferred to the common driver as the transfer starts (TE=1), and is the
executed.
Sp
TE: Serial transfer enable for the common driver. When TE=0, serial transfer is possible. Do not change
the instruction during transfer. When TE=1, transfer starts. TE returning to 0 indicates the end of the
transfer. Note that, serial transfer to the common driver requires 18 clock cycles at most. Do not change
the instruction during the transfer.
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* New instructions should be transferred to the common driver soon after they have been set on the
HD66765.
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23
HD66765
Table of common driver (HD66764) instructions
IDX2
IDX1
IDX0
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
BS2
BS1
BS0
BT3
BT2
BT1
BT0
0
DC1
DC0
AP1
AP0
SLP
0
0
1
0
0
0
0
0
0
0
0
0
0
VC2
VC1
VC0
0
1
0
0
VR3
VR2
VR1
VR0
0
CT6
CT5
CT4
CT3
CT2
CT1
CT0
0
1
1
0
0
D1
1
0
0
0
0
0
0
0
SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10
1
0
1
0
0
0
0
0
SS27 SS26 SS125 SS24 SS23 SS22 SS21 SS20
1
1
0
0
0
0
0
0
SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20
Instruction setting change
CMS SPT SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10
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Change the instruction bit setting
corresponding to the HD66765
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Sp
Transfer to the common driver must be executed immediately after setting up the instruction
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Index set R0Ah
Instruction read
in
NO
(During transfer)
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TE = "0"
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YES (Transfer can be executed)
Common side index (IDX2 to 0)
TE = 1 (transfer start)
Notes:
Specify the IDX2 to 0 in the HD66764
instruction including a changed instruction bit
1. Transfer to the common driver must take place immediately after setting up the instruction.
2. The serial transfer period takes a maximum of 1/fosc x 18 clock cycles (sec).
3. Serial transfer cannot be executed in standby mode. If the chip enters standbymode during transfer,
the serial transfer is forcibly suspended. Transfer must be executed again because correct transfer is
not guaranteed in this situation.
4. Serial transfer can be forcibly suspended by writing TE = 0. Transfer must be executed again because
correct transfer is not guaranteed in this situation.
5. Do not enter standby mode during transfer or forcibly terminate transfer except in case of emergency.
Before executing, confirm that the transfer is completed.
Figure 13 Common Interface: Serial Transfer Sequence
24
HD66765
Frame Cycle Control (R0Bh)
R/W
RS
DB15
DB14
DB13
DB12
DB11
DB10
W
1
0
0
0
0
0
0
DB9
DB8
DIV1 DIV0
DB7
DB6
DB5
DB4
0
0
0
0
DB3
DB2
DB1
DB0
RTN3 RTN2 RTN1 RTN0
Figure 14 Frame Cycle Control Instruction
RTN3-0: Set the line retrace period (RTN3-0) to be added to raster-row cycles. The raster-row cycle
becomes longer according to the number of clocks set at RTN3-0.
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DIV1-0: Set the division ratio of clocks for internal operation (DIV1-0). Internal operations are driven by
clocks which are frequency divided according to the DIV1-0 setting. Frame frequency can be adjusted
along with the line retrace period (RTN3-0). When changing the drive-duty cycle, adjust the frame
frequency. For details, see the Frame Frequency Adjustment Function section.
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Table 10 RTN Bits and Clock Cycles
RTN3
RTN2
RTN1
RTN0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
:
:
:
1
1
1
1
1
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25
1
26
2
27
3
28
:
:
0
14
39
1
15
40
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:
1
Sp
Line Retrace Period
(Clock Cycles)
0
Clock
Cycles per
Raster-row
Table 11 DIV Bits and Clock Frequency
Internal Operation
Clock Frequency
DIV1
DIV0
Division Ratio
0
0
1
fosc / 1
0
1
2
fosc / 2
1
0
4
fosc / 4
1
1
8
fosc / 8
* fosc = R-C oscillation frequency
25
HD66765
Formula for the frame frequency
fosc
Frame frequency =
[Hz]
Clock cycles per raster-row × division ratio × 1/duty cycle
fosc: R-C oscillation frequency
Duty: drive duty (NL bit)
Division ratio: DIV bit
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Clock cycles per raster-row: (RTN + 25) clock cycles
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Vertical Scroll Control (R11h)
R/W
RS
W
1
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
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DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
VL27 VL26 VL25 VL24 VL23 VL22 VL21 VL20 VL17 VL16 VL15 VL14 VL13 VL12 VL11 VL10
Sp
Figure 15 Vertical Scroll Control Instruction
VL17–10: Specify the display-start raster-row at the 1st screen display for vertical smooth scrolling.
Any raster-row from the first to 176th can be selected. After the 176th raster-row is displayed, the
display restarts from the first raster-row. The display-start raster-row (VL17–10) is valid only when
VLE1 = 1. The raster-row display is fixed when VLE1 = 0. (VLE1 is the 1st-screen vertical-scroll
enable bit.)
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VL27–20: Specify the display-start raster-row at the 2nd screen display. The display-start raster-row
(VL27–20) is valid only when VLE2 = 1. The raster-row display is fixed when VLE2 = 0. (VLE2 is the
2nd-screen vertical-scroll enable bit.) The vertical scroll for the 1st and 2nd screens can be independently
set.
Table 22
Pr
VL Bits and Display-start Raster-row
VL27
VL17
VL26
VL16
VL25
VL15
VL24
VL14
VL23
VL13
VL22
VL12
VL21
VL11
VL20
VL10
Display-start Raster-row
0
0
0
0
0
0
0
0
1st raster-row
0
0
0
0
0
0
0
1
2nd raster-row
0
0
0
0
0
0
1
0
3rd raster-row
:
:
:
:
:
:
:
:
:
1
0
1
0
1
1
1
0
175th raster-row
1
0
1
0
1
1
1
1
176th raster-row
Note: Do not set over the 176th (AFH) raster-row.
26
HD66765
1st Screen Driving Position (R14h)
2nd Screen Driving Position (R15h)
R/W
RS
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
1
SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10 SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10
W
1
SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20 SS27 SS26 SS25 SS24 SS23 SS22 SS21 SS20
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Figure 16 1st Screen Driving Position and 2nd Screen Driving Position Instructions
SS17–0: Specify the driving start position for the first screen in a line unit. The LCD driving starts from
the 'set value + 1' common driver.
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SE17–0: Specify the driving end position for the first screen in a line unit. The LCD driving is
performed to the 'set value + 1' common driver. For instance, when SS17–10 = 07H and SE17–10 = 10H
are set, the LCD driving is performed from COM8 to COM17, and non-selection driving is performed for
COM1 to COM7, COM18, and others. Ensure that SS17–10 ≤ SE17–10 ≤ AFH. For details, see the
Screen-division Driving Function section.
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SS27–0: Specify the driving start position for the second screen in a line unit. The LCD driving starts
from the 'set value + 1' common driver. The second screen is driven when SPT = 1.
in
SE27–0: Specify the driving end position for the second screen in a line unit. The LCD driving is
performed to the 'set value + 1' common driver. For instance, when SPT = 1, SS27–20 = 20H, and
SE27–20 = AFH are set, the LCD driving is performed from COM33 to COM80. Ensure that SS17–10 ≤
SE17–10 ≤ SS27–20 ≤ SE27–20 ≤ 4FH. For details, see the Screen-division Driving Function section.
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27
HD66765
Horizontal RAM Address Position (R16h)
Vertical RAM Address Position (R17h)
R/W
RS
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
1
HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0
W
1
VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0
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Figure 17 Horizontal/Vertical RAM Address Position Instruction
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HSA7-0/HEA7-0: Specify the horizontal start/end positions of a window for access in memory. Data can
be written to the GRAM from the address specified by HEA7-0 from the address specified by HSA7-0.
Note that an address must be set before RAM is written to. Ensure 00h ≤ HSA7-0 ≤ HEA7-0 ≤ 3Fh.
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VSA7-0/VEA7-0: Specify the vertical start/end positions of a window for access in memory. Data can be
written to the GRAM from the address specified by VEA7-0 from the address specified by VSA7-0. Note
that an address must be set before RAM is written to. Ensure 00h ≤ VSA7-0 ≤ VEA7-0 ≤ AFh.
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HEA
HSA
0000h
in
VSA
VEA
lim
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Window address setting range
"00"h HSA7-0 HEA7-0 "83"h
"00"h VSA7-0 VEA7-0 "AF"h
Window address
GRAM address space
Note:
Sp
AF83h
1. Ensure that the window address area is within the GRAM address space.
2. In high-speed write mode, data are written to GRAM in four-words.
Thus, dummy write operations should be inserted depending on the window address
area. For details, see the High-Speed Burst RAM Write Function section.
Figure 18 Window Address Setting Range
28
HD66765
RAM Write Data Mask (R20h)
R/W
W
RS
1
DB15
DB14
0
DB13
0
0
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
WM
11
WM
10
WM
9
WM
8
WM
7
WM
6
WM
5
WM
4
WM
3
WM
2
WM
1
WM
0
Figure 19 RAM Write Data Mask Instruction
WM11–0: In writing to the GRAM, these bits mask writing in a bit unit. When WM11 = 1, this bit
masks the write data of DB11 and does not write to the GRAM. Similarly, the WM10–0 bits mask the
write data of DB10–0 in a bit unit. When SWP = 1, the upper and lower bytes in the write data mask are
swapped. For details, see the Graphics Operation Function section.
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RAM Address Set (R21h)
R/W
W
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RS
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
AD
15
AD
14
AD
13
AD
12
AD
11
AD
10
AD
9
AD
8
AD
7
AD
6
AD
5
AD
4
AD
3
AD
2
AD
1
AD
0
Sp
Figure 20 RAM Address Set Instruction
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AD15–0: Initially set GRAM addresses to the address counter (AC). Once the GRAM data is written,
the AC is automatically updated according to the AM and I/D bit settings. This allows consecutive
accesses without resetting addresses. Once the GRAM data is read, the AC is not automatically updated.
GRAM address setting is not allowed in the standby mode. Ensure that the address is set within the
specified window address.
in
Table 13
AD14–AD0
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GRAM Address Range in Eight-grayscale Mode
Pr
GRAM Setting
"0000"H–"0083"H
Bitmap data for COM1
"0100"H–"0183"H
Bitmap data for COM2
"0200"H–"0283"H
Bitmap data for COM3
"0300"H–"0383"H
Bitmap data for COM4
:
:
"AC00"H–"AC83"H
Bitmap data for COM173
"AD00"H–"AD83"H
Bitmap data for COM174
"AE00"H–"AE83"H
Bitmap data for COM175
"AF00"H–"AF83"H
Bitmap data for COM176
29
HD66765
Write Data to GRAM (R22h)
R/W
W
RS
DB15
1
DB14
0
DB13
0
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
WD
11
WD
10
WD
9
WD
8
WD
7
WD
6
WD
5
WD
4
WD
3
WD
2
WD
1
WD
0
0
Figure 21 Write Data to GRAM Instruction
WD11–0 : Write 12-bit data to the GRAM. This data calls each grayscale palette. After a write, the
address is automatically updated according to the AM and I/D bit settings. During the standby mode, the
GRAM cannot be accessed.
DB15
0
GRAM write data
DB14
0
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
0
WD
11
WD
10
WD
9
WD
8
WD
7
WD
6
R3
R2
R1
R0
G3
0
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G2
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DB5
DB4
DB3
DB2
DB1
DB0
WD
5
WD
4
WD
3
WD
2
WD
1
WD
0
G1
G0
B3
B2
B1
B0
1 pixel data
Figure 22 GRAM Write Data Instruction
Table 14
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GRAM Data and Grayscale Palette
GRAM Data Setting
R3
R2
R1
R0
G3
G2
G1
G0
B3
B2
B1
B0
0
0
0
0
0
0
0
0
0
in
lim
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P
Grayscale Palette
0
0
PK04
PK03
PK02
PK01
PK00
0
1
PK14
PK13
PK12
PK11
PK10
1
0
PK24
PK23
PK22
PK21
PK20
1
1
PK34
PK33
PK32
PK31
PK30
1
0
0
PK44
PK43
PK42
PK41
PK40
0
1
0
1
PK54
PK53
PK52
PK51
PK50
0
1
1
0
PK64
PK63
PK62
PK61
PK60
0
1
1
1
PK74
PK73
PK72
PK71
PK70
1
0
0
0
PK84
PK83
PK82
PK81
PK80
1
0
0
1
PK94
PK93
PK92
PK91
PK90
1
0
1
0
PK104
PK103
PK102
PK101
PK100
1
0
1
1
PK114
PK113
PK112
PK111
PK110
1
1
0
0
PK124
PK123
PK122
PK121
PK120
1
1
0
1
PK134
PK133
PK132
PK131
PK130
1
1
1
0
PK144
PK143
PK142
PK141
PK140
1
1
1
1
PK154
PK153
PK152
PK151
PK150
30
HD66765
Read Data from GRAM (R22h)
R/W
R
RS
DB15
1
0
DB14
0
DB13
0
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
RD
11
RD
10
RD
9
RD
8
RD
7
RD
6
RD
5
RD
4
RD
3
RD
2
RD
1
RD
0
Figure 23 Read Data from GRAM Instruction
RD11–0: Read 12-bit data from the GRAM. When the data is read to the microcomputer, the first-word
read immediately after the GRAM address setting is latched from the GRAM to the internal read-data
latch. The data on the data bus (DB11–0) becomes invalid and the second-word read is normal.
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When bit processing, such as a logical operation, is performed within the HD66765, only one read can be
processed since the latched data in the first word is used.
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Sets the I/D, AM, HSA/HEA, and
VSA/VEA bits
Sets the I/D, AM, HSA/HEA, and
VSA/VEA bits
Address: N set
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Dummy read (invalid data)
First word
Second word
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Read (data of address N)
Read-data latch -> DB11-0
Dummy read (invalid data)
Read (data of address M)
DB11-0 -> GRAM
First word
GRAM -> Read-data latch
Read-data latch -> DB11-0
Read (data of address N)
Automatic address update: N + α
Address: M set
Second word
GRAM -> Read-data latch
Second word
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First word
Dummy read (invalid data)
First word
GRAM -> Read-data latch
Address: N set
Second word
i) Data read to the microcomputer
Dummy read (invalid data)
GRAM -> Read-data latch
Write (data of address N+ α )
DB11-0 -> GRAM
ii) Logical operation processing in the HD66765
Figure 24 GRAM Read Sequence
31
HD66765
Grayscale Palette Control (R30h to R39h)
R/W
RS
DB15
DB14
DB13
DB7
DB6
DB5
R30h
W
1
0
0
0
PK14 PK13 PK12 PK11 PK10
DB12
DB11
DB10
DB9
DB8
0
0
0
PK04 PK03 PK02 PK01 PK00
DB4
DB3
DB2
DB1
DB0
R31h
W
1
0
0
0
PK34 PK33 PK32 PK31 PK30
0
0
0
PK24 PK23 PK22 PK21 PK20
R32h
W
1
0
0
0
PK54 PK53 PK52 PK51 PK50
0
0
0
PK44 PK43 PK42 PK41 PK40
R33h
W
1
0
0
0
PK74 PK73 PK72 PK71 PK70
0
0
0
PK64 PK63 PK62 PK61 PK60
R34h
W
1
0
0
0
PK94 PK93 PK92 PK91 PK90
0
0
0
PK84 PK83 PK82 PK81 PK80
R35h
W
1
0
0
0
PK114 PK113 PK112 PK111 PK110
0
0
0
PK104 PK103 PK102 PK101 PK100
R36h
W
1
0
0
0
PK134 PK133 PK132 PK131 PK130
0
0
0
PK124 PK123 PK122 PK121 PK120
R37h
W
1
0
0
0
PK154 PK153 PK152 PK151 PK150
0
0
0
PK144 PK143 PK142 PK141 PK140
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Figure 25 Grayscale Palette Control Instruction
RK154–00: Specify the grayscale level for 16-palettes from the 24-grayscale level. For details, see the
Grayscale Palette and Grayscale Palette Table sections.
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32
Table 17 Instruction List
Upper Code
Reg.
No.
IR
Register Name
Index
SR
Execu-tion
Cycle
Lower Code
R/W
0
RS
0
DB15
*
DB14
*
DB13
*
DB12
*
DB11
*
DB10
*
DB9
*
DB8
*
DB7
*
DB6
ID6
DB5
ID5
DB4
ID4
DB3
ID3
DB2
ID2
DB1
ID1
DB0
ID0
Status read
1
0
L7
L6
L5
L4
L3
L2
L1
L0
0
C6
C5
C4
C3
C2
C1
C0
R00h
Start oscillation
0
1
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
Device code read
1
1
0
0
0
0
0
1
1
1
0
1
1
0
0
0
1
1
R01h
Driver output control
0
1
0
0
0
0
0
0
CMS
SGS
0
0
0
NL4
NL3
NL2
NL1
NL0
Description
Sets the index register value.
Reads the driving raster-row position (L7-0) and contrast setting (C6-0).
Starts the oscillation mode.
0
0
10 ms
Reads 0765H.
0
Sets the common driver shift direction (CMS), segment driver shift
0
direction (SGS), and driving duty ratio (NL4-0).
R02h
LCD-driving-waveform
0
1
0
0
0
0
0
0
B/C
EOR
0
0
NW5
NW4
NW3
NW2
NW1
NW0
control
R03h
Power control 1
Sets the LCD drive AC waveform (B/C), EOR output (EOR), and the
0
number of n-raster-rows (NW5-0) at C-pattern AC drive.
0
1
0
BS2
BS1
BS0
BT3
BT2
BT1
BT0
0
DC2
DC1
DC0
AP1
AP0
SLP
STB
Sets the standby mode (STB), LCD power on (AP1-0),
0
sleep mode (SLP), boosting cycle (DC2-0),
boosting ouput multiplying factor (BT3-0), and LCD drive bias value
(BS2-0).
R04h
Contrast control
0
1
0
0
0
0
VR3
VR2
VR1
VR0
0
CT6
CT5
CT4
CT3
CT2
CT1
CT0
Sets the contrast adjustment (CT6-0) and regulator adjustment (VR3-0).
0
R05h
Entry mode
0
1
0
0
0
0
0
0
HWM
0
0
0
I/D1
I/D0
AM
LG2
LG1
LG0
Specifies the logical operation (LG2-0), AC counter mode (AM), increment/
0
R06h
Compare register
0
1
0
0
0
0
0
0
0
0
CP7
CP6
CP5
CP4
CP3
CP2
CP1
CP0
decrement mode (I/D1-0) and high-speed-write mode (HWM).
Sets the compare register (CP7-0).
0
R07h
Display control
0
1
0
0
0
0
0
VLE2
VLE1
SPT
0
0
0
0
0
REV
D1
D0
R0Ah
COM driver interface control
0
1
0
0
0
0
0
0
0
TE
0
0
0
0
0
IDX2
IDX1
1
1
0
0
0
0
0
0
0
TE
0
0
0
0
0
IDX2
IDX1
1
0
0
0
0
0
0
DIV1
DIV0
0
0
0
0
Specifies display on (D1-0), reversed display (REV), ,screen division driving
(SPT), and vertical scroll (VLE2-1).
0
IDX0
Specifies the serial transfer enable (TE) and index for the COM transfer
0
IDX0
instructions (IDX2-0).
RTN3 RTN2 RTN1 RTN0 Sets the line retrace period (RTN3-0) and operating clock frequency-division ratio (DIV1-0)
0
R0Bh
Frame cycle control
0
0
R0Ch
Power control 2
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
VC2
VC1
VC0
Sets an adjustment factor for the Vci voltage (VC2-0).
0
R11h
Vertical scroll control
0
1
VL27
VL26
VL25
VL24
VL23
VL22
VL21
VL20
VL17
VL16
VL15
VL14
VL13
VL12
VL11
VL10
Specifies the 1st-screen display-start raster-row (VL17-10) and 2nd-
0
R14h
1st screen driving position
0
1
SE17
SE16
SE15
SE14
SE13
SE12
SE11
SE10
SS17
SS16
SS15
SS14
SS13
SS12
SS11
SS10
Sets 1st-screen driving start (SS17-10) and end (SE17-10).
0
R15h
2nd screen driving position
0
1
SE27
SE26
SE25
SE24
SE23
SE22
SE21
SE20
SS27
SS26
SS25
SS24
SS23
SS22
SS21
SS20
Sets 2nd-screen driving start (SS27-20) and end (SE27-20).
0
R16h
Horizontal RAM address position
0
1
R17h
Vertical RAM address position
0
1
HEA7 HEA6 HEA5 HEA4 HEA3 HEA2 HEA1 HEA0 HSA7 HSA6 HSA5 HSA4 HSA3 HSA2 HSA1 HSA0 Sets the start (HSA7-0) and end (HEA7-0) of the horizontal RAM address range.
VEA7 VEA6 VEA5 VEA4 VEA3 VEA2 VEA1 VEA0 VSA7 VSA6 VSA5 VSA4 VSA3 VSA2 VSA1 VSA0 Sets the start (VSA7-0) and end (VEA7-0) of the vertical RAM address range.
R20h
RAM write data mask
0
1
R21h
RAM address set
0
1
R22h
Write data to GRAM
0
1
Write Data (upper)
Write Data (lower)
Write data from GRAM
1
1
Read Data (upper)
Read Data (lower)
Grayscale palette control (1)
0
1
screen display-start raster-row (VL27-20).
R30h
0
0
0
0
WM
WM
11
10
WM9
WM8
WM7
WM6
WM5
WM4
AD15-8 (upper)
0
0
0
PK14
PK13
PK12
WM3
WM2
WM1
WM0
AD7-0 (lower)
PK11
PK10
0
0
0
PK04
PK03
PK02
PK01
PK00
0
0
Specifies write data mask (WM15-0) at RAM write.
0
Initially sets the RAM address to the address counter (AC).
0
Write data to RAM.
0
Read data from RAM.
Specifies the Grayscale palette.
0
0
R31h
Grayscale palette control (2)
0
1
0
0
0
PK34
PK33
PK32
PK31
PK30
0
0
0
PK24
PK23
PK22
PK21
PK20
Specifies the Grayscale palette.
0
R32h
Grayscale palette control (3)
0
1
0
0
0
PK54
PK53
PK52
PK51
PK50
0
0
0
PK44
PK43
PK42
PK41
PK40
Specifies the Grayscale palette.
0
R33h
Grayscale palette control (4)
0
1
0
0
0
PK74
PK73
PK72
PK71
PK70
0
0
0
PK64
PK63
PK62
PK61
PK60
Specifies the Grayscale palette.
0
R34h
Grayscale palette control (5)
0
1
0
0
0
PK94
PK93
PK92
PK91
PK90
0
0
0
PK84
PK83
PK82
PK81
PK80
Specifies the Grayscale palette.
0
R35h
Grayscale palette control (6)
0
1
0
0
0
PK114 PK113 PK112 PK111 PK110
0
0
0
PK104 PK103 PK102 PK101 PK100 Specifies the Grayscale palette.
0
R36h
Grayscale palette control (7)
0
1
0
0
0
PK134 PK133 PK132 PK131 PK130
0
0
0
PK124 PK123 PK122 PK121 PK120 Specifies the Grayscale palette.
0
R37h
Grayscale palette control (8)
0
1
0
0
0
PK154 PK153 PK152 PK151 PK150
0
0
0
PK144 PK143 PK142 PK141 PK140 Specifies the Grayscale palette.
0
Note: 1. '*' means 'doesn't matter'.
2. After setting TE = 1, 18 (max.) clock cycles are required for a serial transfer to be completed. During that time, do not change the bits of instructions which are to be transferred.
3. High-speed write mode is available only for the RAM writing.
HITACHI
33
HD66765
Reset Function
The HD66765 is internally initialized by RESET input. Reset the common driver as its settings are not
automatically reinitialized when the HD66765 is reset. The reset input must be held for at least 1 ms. Do
not access the GRAM or initially set the instructions until the R-C oscillation frequency is stable after
power has been supplied (10 ms).
Instruction Set Initialization:
1.
2.
3.
4.
Start oscillation executed
Driver output control (NL4–0 = 10101, SGS = 0, CMS = 0)
B-pattern waveform AC drive (B/C = 0, ECR = 0, NW5–0 = 00000)
Power control 1 (DC2–0 = 000, AP1–0 = 00: LCD power off, STB = 0: Standby mode off, SLP = 0,
BS2-0 = 000, BT2-0 = 000)
5. Contrast control (Weak contrast (VR3-0 = 0000, CT6–0 = 0000000))
6. Entry mode set (HWM = 0, I/D1-0 = 11: Increment by 1, AM = 0: Horizontal move, LG2–0 = 000:
Replace mode)
7. Compare register (CP7–0: 00000000)
8. Display control (VLE2–1 = 00: No vertical scroll, SPT = 0, REV = 0, D1–0 = 00: Display off)
9. COM driver interface control (TE = 0, IDX2-0 = 000)
10. Frame cycle control (DIV1-0 = 00: 1-divided clock, RTN2-0: No retrace line period)
11. Power control 2 (VC2-0 = 000)
12. Vertical scroll (VL27–20 = 00000000, VL17–10 = 00000000)
13. 1st screen division (SE17-10 = 11111111, SS17-10 = 00000000)
14. 2nd screen division (SE27-20 = 11111111, SS27-20 = 00000000)
15. Horizontal RAM address position (HEA7-0 = 00111111, HSA7-0 = 000000)
16. Vertical RAM address position (VEA7-0 = 10101111, VSA7-0 = 00000000)
17. RAM write data mask (WM11–0 = 000H: No mask)
18. RAM address set (AD15–0 = 0000H)
19.
Grayscale palette
PK04–00 = 00000, PK14–10 = 00010, PK24–20 = 00100, PK34–30 = 00110,
PK44–40 = 00111, PK54–50 = 01000, PK64–60 = 01001, PK74–70 = 01010,
PK84–80 = 01011, PK94–90 = 01100, PK104–100 = 01101, PK114–110 = 01110,
PK124–120 = 10000, PK134–130 = 10010, PK144–140 = 10101, PK154–150 = 10111
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GRAM Data Initialization:
This is not automatically initialized by reset input but must be initialized by software while display is off
(D1–0 = 00).
Output Pin Initialization:
1.
2.
3.
4.
LCD driver output pins (SEG/COM): Output GND level
Oscillator output pin (OSC2): Outputs oscillation signal
Common interface signals (CCS*, CCL, and CDA): Halt
Timing signals (CL1, M, FLM, DISPTMG, and DCCLK): Halt
34
HD66765
Parallel Data Transfer
16-bit Bus Interface
Setting the IM2/1/0 (interface mode) to the GND/GND/GND level allows 68-system E-clocksynchronized 16-bit parallel data transfer. Setting the IM2/1/0 to the GND/Vcc/GND level allows 80system 16-bit parallel data transfer. When the number of buses or the mounting area is limited, use an 8bit bus interface.
H8/2245
CSn*
A1
HWR*
(RD*)
D15-D0
CS*
RS
HD66765
WR*
(RD*)
DB15-DB0
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16
Figure 26 Interface to 16-bit Microcomputer
8-bit Bus Interface
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Setting the IM2/1/0 (interface mode) to the GND/GND/Vcc level allows 68-system E-clock-synchronized
8-bit parallel data transfer using pins DB15–DB8. Setting the IM1/0 to the Vcc/Vcc level allows 80system 8-bit parallel data transfer. The 16-bit instructions and RAM data are divided into eight
upper/lower bits and the transfer starts from the upper eight bits. Fix unused pins DB7–DB0 to the Vcc
or GND level. Note that the upper bytes must also be written when the index register is written to.
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H8/2245
CSn*
A1
HWR*
(RD*)
D15-D8
CS*
RS
HD66765
WR*
(RD*)
DB15-DB8
DB7-0
8
8
GND
Figure 27 Interface to 8-bit Microcomputer
Note: Transfer synchronization function for an 8-bit bus interface
The HD66765 supports the transfer synchronization function which resets the upper/lower
counter to count upper/lower 8-bit data transfer in the 8-bit bus interface. Noise causing transfer
mismatch between the eight upper and lower bits can be corrected by a reset triggered by
consecutively writing a 00H instruction four times. The next transfer starts from the upper eight
bits. Executing synchronization function periodically can recover any runaway in the display
system.
35
HD66765
RS
R/W
E
DB15-DB8
Upper or
Lower
"00"H
"00"H
"00"H
"00"H
(1)
(2)
(3)
(4)
Upper
Lower
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8-bit transfer syhchronization
Figure 28 8-bit Transfer Synchronization
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36
HD66765
Serial Data Transfer
Setting the IM1 pin to the GND level and the IM2 pin to the Vcc level allows standard clocksynchronized serial data (SPI) transfer, using the chip select line (CS*), serial transfer clock line (SCL),
serial input data (SDI), and serial output data (SDO). For a serial interface, the IM0/ID pin function uses
an ID pin. If the chip is set up for serial interface, the DB15-2 pins which are not used must be fixed at
Vcc or GND.
The HD66765 initiates serial data transfer by transferring the start byte at the falling edge of CS* input. It
ends serial data transfer at the rising edge of CS* input.
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The HD66765 is selected when the 6-bit chip address in the start byte transferred from the transmitting
device matches the 6-bit device identification code assigned to the HD66765. The HD66765, when
selected, receives the subsequent data string. The least significant bit of the identification code can be
determined by the ID pin. The five upper bits must be 01110. Two different chip addresses must be
assigned to a single HD66765 because the seventh bit of the start byte is used as a register select bit (RS):
that is, when RS = 0, data can be written to the index register or status can be read, and when RS = 1, an
instruction can be issued or data can be written to or read from RAM. Read or write is selected according
to the eighth bit of the start byte (R/W bit). The data is received when the R/W bit is 0, and is transmitted
when the R/W bit is 1.
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After receiving the start byte, the HD66765 receives or transmits the subsequent data byte-by-byte. The
data is transferred with the MSB first. All HD66765 instructions are 16 bits. Two bytes are received with
the MSB first (DB15 to 0), then the instructions are internally executed. After the start byte has been
received, the first byte is fetched internally as the upper eight bits of the instruction and the second byte is
fetched internally as the lower eight bits of the instruction.
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Four bytes of RAM read data after the start byte are invalid. The HD66765 starts to read correct RAM
data from the fifth byte.
Table 18
Pr
Start Byte Format
Transfer Bit
S
1
2
Start byte format
Transfer start
Device ID code
0
1
Note: ID bit is selected by the IM0/ID pin.
Table 19
RS and R/W Bit Function
RS
R/W
Function
0
0
Sets index register
0
1
Reads status
1
0
Writes instruction or RAM data
1
1
Reads instruction or RAM data
37
3
1
4
1
5
0
6
ID
7
8
RS
R/W
HD66765
a) Timing of Basic Data-Transfer through Clock-Synchronized Serial Bus Interface
Transfer start
Transfer end
CS*
(Input)
2
1
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCL
(Input)
MSB
SDI
(Input)
"0" "1" "1" "1"
LSB
on
"0" ID RS RW DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
15 14 13 12 11 10 9 8 7 6 5
4
3 2 1
Device ID code
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RS R/W
fi ic
Start byte
DB
0
Index register setting, instruction, RAM data write
SDO
(Output)
DB DB DB DB DB DB DB DB DB DB DB DB DB DB DB
15 14 13 12 11 10 9 8 7 6 5
4
3 2 1
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DB
0
Status read, instruction read, RAM data read
S
b) Timing of Consecutive Data-Transfer through Clock-Synchronized Serial Bus Interface
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CS*
(Input)
1 2 3 4 5 6 7 8
9 10 1112 13 14 15 16
in
SCL
(Input)
lim
SDI
(Input)
Start byte
Start
e
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P
Instruction 1: upper
eight bits
1718 19 20 21 22 23 24 25 26 2728 29 30 31 32
Instruction 1: lower
eight bits
Instruction 2: upper
eight bits
Instruction 1: execution
time
End
Note: The first byte after the start byte is always the upper eight bits.
c) RAM-Data Read-Transfer Timing
CS*
(Input)
SCL
(Input)
SDI
(Input)
Start byte
RS = 1,
R/W = 1
SDO
(Output)
Dummy
read 1
Dummy
read 2
Dummy
read 3
Dummy
read 4
Dummy
read 5
RAM read:
upper
eight bits
RAM read:
lower
eight bits
Start
End
Note: Five bytes of the RAM read data after the start byte are invalid. The HD66765 starts
to read the correct RAM data from the sixth byte.
Figure 29 Procedure for Transfer on Clock-Synchronized Serial Bus Interface
38
HD66765
d) Status Read/Instruction Read
CS*
(Input)
SCL
(Input)
Start byte
RS = 0,
R/W = 1
SDI
(Input)
SDO
(Output)
Dummy read 1
Status read:
upper eight bits
Status read:
lower eight bits
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Start
End
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Note: One byte of the read data after the start byte are invalid. The HD66765 starts
to read the correct data from the second byte.
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Figure 29 Procedure for Transfer on Clock-Synchronized Serial Bus Interface (cont)
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39
HD66765
High-Speed Burst RAM Write Function
The HD66765 has a high-speed burst RAM-write function that can be used to write data to RAM in onefourth the access time required for an equivalent standard RAM-write operation. This function is
especially suitable for applications which require the high-speed rewriting of the display data, for
example, display of color animations, etc.
When the high-speed RAM-write mode (HWM) is selected, data for writing to RAM is once stored to the
HD66765 internal register. When data is selected four times per word, all data is written to the on-chip
RAM. While this is taking place, the next data can be written to an internal register so that high-speed
and consecutive RAM writing can be executed for animated displays, etc.
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Microcomputer
12
Address
counter
(AC)
Register 1
Sp
Register 2
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16
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Register 3
Register 4
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"0000"H "0001"H "0002"H "0003"H
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GRAM
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Figure 30 Flow of Operation in High-Speed Consecutive Writing to RAM
Pr
CS*
(Input)
1
2
3
4
1
2
3
4
1
2
3
4
E
(Input)
DB15-0
(Input/output)
Index
(R22h)
RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM
data data data data data data data data data data data data
1
2
3
4
5
6
7
8
9
10
11
12
RAM write
execution time
RAM write data
(64 bits)
RAM address
(AC15 to 0)
RAM write
execution time
RAM data 1 to 4
"0000"H
RAM data 5 to 8
"0004"H
Index
(R22h)
RAM write
execution time *
RAM data 9 to 12
"0008"H
"000A"H
♦ The lower two bits of the address must be set in the following way in high-speed write mode.
When ID0 becomes 0, the lower two bits of the address must be set to 11
When ID1 becomes 1, the lower two bits of the address must be set to 00.
Note: When a high-speed RAM write is canceled, the next instruction must only be executed after
the RAM write execution time has elapsed.
Figure 31 Example of the Operation of High-Speed Consecutive Writing to RAM
40
HD66765
When high-speed RAM write mode is used, note the following.
Notes: 1. The logical and compare operations cannot be used.
2. Data is written to RAM each four words. When an address is set, the lower two bits in the
address must be set to the following values.
*When ID0=0, the lower two bits in the address must be set to 11 and be written to RAM.
*When ID0=1, the lower two bits in the address must be set to 00 and be written to RAM.
3. Data is written to RAM each four words. If less than four words of data is written to RAM, the
last data will not be written to RAM.
4. When the index register and RAM data write (R22h) have been selected, the data is always
written first. RAM cannot be written to and read from at the same time. HWM must be set to
0 while RAM is being read.
5. High-speed and normal RAM write operations cannot be executed at the same time. The mode
must be switched and the address must then be set.
6. When high-speed RAM write is used with a window address-range specified, dummy write
operation may be required to suit the window address range-specification. Refer to the HighSpeed RAM Write in the Window Address section.
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Table 20
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Comparison between Normal and High-Speed RAM Write Operations
Normal RAM Write
(HWM=0)
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High-Speed RAM Write
(HWM=1)
Logical operation function
Can be used
Compare operation function
Can be used
Cannot be used
Swap function
Can be used
Can be used
Can be used
Can be used
RAM read
re
RAM write
P
Window address
in
lim
Write mask function
RAM address set
Cannot be used
Can be specified by word
ID0 bit=0: Set the lower two bits to 11
ID0 bit=1: Set the lower two bits to 00
Can be read by word
Cannot be used
Can be written by word
Dummy write operations may have to be
inserted according to a window addressrange specification
Can be set by word
Can be set by word
41
HD66765
High-Speed RAM Write in the Window Address
When a window address range is specified, RAM data which is in an optional window area can be
rewritten consecutively and quickly by inserting dummy write operations so that RAM access counts
become 4N as shown in the tables below.
Dummy write operations may have to be inserted as the first or last operations for a row of data,
depending on the horizontal window-address range specification bits (HSA1 to 0, HEA1 to 0). Number
of dummy write operations of a row must be 4N.
Table 21
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Number of Dummy Write Operations in High-Speed RAM Write (HSA Bits)
HSA1
HSA0
Number of Dummy Write Operations to
be Inserted at the Start of a Row
0
0
0
0
1
1
1
0
2
1
1
3
Table 22
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Number of Dummy Write Operations in High-Speed RAM Write (HEA Bits)
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HEA1
HEA0
Number of Dummy Write Operations to
be Inserted at the End of a Row
0
0
3
0
1
2
1
0
1
1
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Each row of access must consist of 4 × N operations, including the dummy writes.
Horizontal access count =
first dummy write count + write data count + last dummy write count = 4 × N
42
HD66765
An example of high-speed RAM write with a window address-range specified is shown below.
The window address-range can be rewritten to consecutively and quickly by inserting two dummy writes
at the start of a row and three dummy writes at the end of a row, as determined by using the window
address-range specification bits (HSA1 to 0=10, HEA1 to 0=00).
Writing in the horizontal direction
AM = 0, ID0 = 1
"0000"h
GRAM address map
"8012"h
Window address-range setting
HSA = "12"h, HEA = "30"h
VSA = "80"h, VEA = "A0"h
High-speed RAM write mode
setting HWM = 1
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Window address-range
specification (rewrite area)
Address set
AD = "8010"h *
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Dummy RAM write × 2
RAM write × 31
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"A083"h
Window address-range setting
HSA = "12"h, HEA = "30"h
VSA = "80"h, VEA = "A0"h
× 152
Dummy RAM write × 3
"A030"h
S
Note: The address set for the high-speed RAM write must be 00 or 11 according to
the value of the ID0 bit. Only RAM in the specified window address-range
will be overwritten.
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Figure 32 Example of the High-Speed RAM Write with a Window Address-Range Specification
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43
HD66765
Window Address Function
When data is written to the on-chip GRAM, a window address-range which is specified by the horizontal
address register (start: HSA7-0, end: HEA7-0) or the vertical address register (start: VSA7-0, end:
VEA7-0) can be written to consecutively.
Data is written to addresses in the direction specified by the AM bit (increment/decrement). When image
data, etc. is being written, data can be written consecutively without thinking a data wrap by doing this.
The window must be specified to be within the GRAM address area described below. Addresses must be
set within the window address.
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[Restriction on window address-range settings]
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(horizontal direction) 00H ≤ HSA7-0 ≤ HEA7-0 ≤ 3FH
(vertical direction) 00H ≤ VSA7-0 ≤ VEA7-0 ≤ AFH
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[Restriction on address settings during the window address]
(RAM address) HSA5 to 0 ≤ AD7-0 ≤ HEA7-0
Sp
VSA7-0 ≤ AD15-8 ≤ VEA7-0
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Note: In high-speed RAM-write mode, the lower two bits of the address must be set as shown below
according to the value of the ID0 bit.
in
ID0=0: The lower two bits of the address must be set to 11.
ID0=1: The lower two bits of the address must be set to 00.
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44
HD66765
GRAM address map
"0000"H
"0083"H
Window address area
"2010"H
"2110"H
"202F"H
"212F"H
"5F10"H
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"5F2F"H
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"AF00"H
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Window address-range specification area
HSA7-0 = "10"H, HSE7-0 = "2F"H
VSA7-0 = "20"H, VEA7-0 = "5F"H
in
"AF83"H
I/D = "1" (increment)
AM = "0" (horizontal writing)
Figure 33 Example of Address Operation in the Window Address Specification
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45
HD66765
Graphics Operation Function
The HD66765 can greatly reduce the load of the microcomputer graphics software processing through the
16-bit bus architecture and internal graphics-bit operation function. This function supports the following:
1. A write data mask function that selectively rewrites some of the bits in the 12-bit write data.
2. A logical operation write function that writes the data sent from the microcomputer and the
original RAM data by a logical operation.
3. A conditional write function that compares the original RAM data or write data and the comparebit data and writes the data sent from the microcomputer only when the conditions match.
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Even if the display size is large, the display data in the graphics RAM (GRAM) can be quickly rewritten.
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The graphics bit operation can be controlled by combining the entry mode register, the bit set value of the
RAM-write-data mask register, and the read/write from the microcomputer.
Table 23
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Graphics Operation
Bit Setting
Sp
Operation Mode
I/D
AM
LG2–0
Operation and Usage
Write mode 1
0/1
0
000
Horizontal data replacement, horizontal-border
drawing
Write mode 2
0/1
1
000
Vertical data replacement, vertical-border drawing
Write mode 3
0/1
0
110 111
Conditional horizontal data replacement, horizontalborder drawing
Write mode 4
0/1
1
110 111
Conditional vertical data replacement, vertical-border
drawing
0/1
0
Pr
001 010
011
Horizontal data write with logical operation,
horizontal-border drawing
0/1
1
001 010
011
Vertical data write with logical operation, verticalborder drawing
Read/write mode 3
0/1
0
100 101
Conditional horizontal data replacement, horizontalborder drawing
Read/write mode 4
0/1
1
100 101
Conditional vertical data replacement, vertical-border
drawing
Read/write mode 2
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Read/write mode 1
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HD66765
Microcomputer
16
Read-data latch
+1/-1
Write-data latch
+256
12
12
12
Address
counter
(AC)
3
Logical/Compare operation (LG2—0:)
000: replacement, 001: OR, 010: AND, 011: EOR,
100: replacement with matched read, 101: replacement
with unmatched read, 110: replacement with matched
write, 111: replacement with unmatched write
Logical operation bit
(LG2—0)
12
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Compare bit (CP11—0)
12
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12
Write bit mask
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16
Graphics RAM (GRAM)
Sp
Write-mask register
(WM11—0)
Figure 34 Data Processing Flow of the Graphics Operation
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47
HD66765
Write-data Mask Function
The HD66765 has a bit-wise write-data mask function that controls writing the two-byte data from the
microcomputer to the GRAM. Bits that are 0 in the write-data mask register (WM11–0) cause the
corresponding DB bit to be written to the GRAM. Bits that are 1 prevent writing to the corresponding
GRAM bit to the GRAM; the data in the GRAM is retained. This function can be used when only onepixel data is rewritten or the particular display color is selectively rewritten.
DB11
Data written by
the microcomputer
DB0
R03 R02 R01 R00 G03 G02 G01 G00 B03 B02 B01 B00
DB11
Write-data mask
1
1
1
*
*
*
0
0
0
1
1
1
*
*
*
0
*
0
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DB11
GRAM data
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DB0
1
DB0
G03 G02 G01
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B01 B00
Figure 35 Example of Write-data Mask Function Operation
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48
HD66765
Logical/Compare Operation Function
The HD66765 performs a logical operation or conditional replacement between the two-byte write data
sent from the microcomputer and the read data from the GRAM. The logical operation function has four
types: replacement, OR, AND, and EOR. The conditional replacement performs a compare operation for
the set value of the compare register (CP11–0) and the read data value from the GRAM, and rewrites
only the pixel data in the GRAM that satisfies the conditions (in a byte unit). This function can be used
when a particular color is selectively rewritten. The swap function or write-data mask function can be
effectively used.
Table 24
n
o
ti
Logical/Compare Operation
Bit Setting
a
c
fi
LG2
LG1
LG0
Description of Logical/Compare Operation Function
0
0
0
Writes the data written from the microcomputer directly to the GRAM. Only
write processing is performed since the data in the read-data latch is not used.
0
0
1
ORs the data in the read-data latch and the data written by the microcomputer.
Writes the result to GRAM. Read, modify, or write processing is performed.
0
1
0
ANDs the data in the read-data latch and the data written by the
microcomputer. Writes the result to GRAM.
0
1
1
EORs the data in the read-data latch and the data written by the
microcomputer. Writes the result to GRAM.
1
0
0
Compares the data in the read-data latch and the set value of the compare
register (CP11–0). When the read data matches CP11–0, the data from the
microcomputer is written to the GRAM. Only the particular color specified in
the compare register can be rewritten. Read, modify, or write processing is
performed.
i
c
e
y
r
a
Sp
in
1
0
1
1
1
1
im
l
e
1
Pr
Compares the data in the read-data latch and the set value of the compare
register (CP11–0). When the read data does not match CP11–0, the data from
the microcomputer is written to the GRAM. Colors other than the particular
one specified in the compare register can be rewritten. Read, modify, or write
processing is performed.
0
Compares the data written to the GRAM by the microcomputer and the set
value of the compare register (CP11–0). When the write data matches
CP11–0, the data from the microcomputer is written to the GRAM. Only write
processing is performed.
1
Compares the data written to the GRAM by the microcomputer and the set
value of the compare register (CP11–0). When the write data does not match
CP11–0, the data from the microcomputer is written to the GRAM. Only write
processing is performed.
49
HD66765
Graphics Operation Processing
1. Write mode 1: AM = 0, LG2–0 = 000
This mode is used when the data is horizontally written at high speed. It can also be used to initialize
the graphics RAM (GRAM) or to draw borders. The write-data mask function (WM11–0) is also
enabled in these operations. After writing, the address counter (AC) automatically increments by 1
(I/D = 1) or decrements by 1 (I/D = 0), and automatically jumps to the counter edge one-raster-row
below after it has reached the left or right edge of the GRAM.
n
o
ti
Operation Examples:
1) I/D = "1", AM = "0", LG2-0 = "000"
2) WM11—0 = "0FF"H
3) AC = "0000"H
DB11
0 0 0 0 1 1 1 1 1 1 1 1
Write-data mask:
DB11
i
c
e
*Write mask for plain <G> and <B>.
DB0
Write data (1):
1 0 0 1 1 0 0 1 0 1 0 0
Write data (2):
1 1 0 0 0 0 1 1 0 0 0 0
y
r
a
"0000"H
Sp
"0001"H
1 0 0 1 * * * * * * * *
Write data (1)
in
im
l
e
Pr
a
c
fi
DB0
"0002"H
1 1 0 0 * * * * * * * *
Write data (2)
GRAM
Note: The bits in the GRAM
indicated by ’*’ are not changed.
Figure 36 Writing Operation of Write Mode 1
50
HD66765
2. Write mode 2: AM = 1, LG2–0 = 000
This mode is used when the data is vertically written at high speed. It can also be used to initialize
the GRAM, develop the font pattern in the vertical direction, or draw borders. The write-data mask
function (WM11–0) is also enabled in these operations. After writing, the address counter (AC)
automatically increments by 256, and automatically jumps to the upper-right edge (I/D = 1) or upperleft edge (I/D = 0) following the I/D bit after it has reached the lower edge of the GRAM.
Operation Examples:
1) I/D = "1", AM = "1", LG2-0 = "000"
2) WM11—0 = "0FF"H
3) AC = "0000"H
DB11
Write-data mask:
a
c
fi
0 0 0 0 1 1 1 1 1 1 1 1
DB11
DB0
i
c
e
Write data (1):
1 0 0 1 1 0 0 1 0 1 0 0
Write data (2):
1 1 0 0 0 0 1 1 0 0 0 0
Write data (3):
0 1 1 1 0 1 0 0 0 0 0 1
Sp
"0000"H
1 0 0 1 * * * * * * * *
Write data (1)
"0001"H
1 1 0 0 * * * * * * * *
Write data (2)
"0002"H
0 1 1 1 0 1 0 0 0 0 0 1
Write data (3)
y
r
a
in
lim
e
r
P
n
o
ti
DB0
GRAM
Note: 1. The bits in the GRAM indicated by ’*’ are not changed.
2. After writin to address "AF00"H, the AC jumps to "0001"H.
Figure 37 Writing Operation of Write Mode 2
51
HD66765
3. Write mode 3: AM = 0, LG2–0 = 110/111
This mode is used when the data is horizontally written by comparing the write data and the set value
of the compare register (CP11–0). When the result of the comparison in a byte unit satisfies the
condition, the write data sent from the microcomputer is written to the GRAM. In this operation, the
write-data mask function (WM11–0) is also enabled. After writing, the address counter (AC)
automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0), and automatically jumps to the
counter edge one-raster-row below after it has reached the left or right edge of the GRAM.
Operation Examples:
n
o
ti
1) I/D = "1", AM = "0", LG2-0 = "110" (matched write)
2) CP11—0 = "530"H
3) WM11—0 = "000"H
4) AC = "0000"H
DB11
a
c
fi
DB0
0 0 0 0 0 0 0 0 0 0 0 0
Write-data mask:
DB11
i
c
e
DB0
0 1 0 1 0 0 1 1 0 0 0 0
Compare register:
Compare
operaton
(Matched)
Write data (1):
0 1 0 1 0 0 1 1 0 0 0 0
Sp
C
Compare
operaton
Write data (2):
0 0 0 0 1 1 1 1 0 0 0 0
y
r
a
"0000"H
R
0 1 0 1 0 0 1 1 0 0 0 0
Conditional
replacement
R
Replacement
* * * * * * * * * * * *
"0001"H
in
0 1 0 1 0 0 1 1 0 0 0 0
Matched replacement
of write data (1)
im
l
e
Pr
C
Conditional
replacement
* * * * * * * * * * * *
GRAM
Figure 38 Writing Operation of Write Mode 3
52
"0002"H
HD66765
4. Write mode 4: AM = 1, LG2–0 = 110/111
This mode is used when a vertical comparison is performed between the write data and the set value
of the compare register (CP11–0) to write the data. When the result by the comparison in a byte unit
satisfies the condition, the write data sent from the microcomputer is written to the GRAM. In this
operation, the write-data mask function (WM11–0) are also enabled. After writing, the address
counter (AC) automatically increments by 256, and automatically jumps to the upper-right edge (I/D
= 1) or upper-left edge (I/D = 0) following the I/D bit after it has reached the lower edge of the
GRAM.
Operation Examples:
n
o
ti
1) I/D = "1", AM = "1", LG2-0 = "111" (unmatched write)
2) CP11—0 = "530"H
3) WM11—0 = "000"H
4) AC = "0000"H
DB11
i
c
e
0 0 0 0 0 0 0 0 0 0 0 0
Write-data mask:
DB11
DB0
0 1 0 1 0 0 1 1 0 0 0 0
Compare register:
1 0 0 1 1 0 0 1 1 0 0 1
ry
(Matched)
Write data (2):
0 1 0 1 0 0 1 1 0 0 0 0
a
n
i
"0000"H
1 0 0 1 1 0 0 1 1 0 0 1
"0001"H
* * * * * * * * * * * *
Pr
im
l
e
Sp
Compare
operaton
(Unmatched)
Write data (1):
"AF00"H
a
c
fi
DB0
C
Compare
operaton
C
Conditional
replacement
R
1 0 0 1 1 0 0 1 1 0 0 1
Conditional
replacement
R
* * * * * * * * * * * *
Write data (1)
GRAM
Figure 39 Writing Operation of Write Mode 4
53
HD66765
5. Read/Write mode 1: AM = 0, LG2–0 = 001/010/011
This mode is used when the data is horizontally written at high speed by performing a logical
operation with the original data. It reads the display data (original data), which has already been
written in the GRAM, performs a logical operation with the write data sent from the microcomputer,
and rewrites the data to the GRAM. This mode reads the data during the same access-pulse width
(68-system: enabled high level, 80-system: RD* low level) as the write operation since reading the
original data does not latch the read data into the microcomputer but temporarily holds it in the readdata latch. However, the bus cycle requires the same time as the read operation. The write-data mask
function (WM11–0) is also enabled in these operations. After writing, the address counter (AC)
automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0), and automatically jumps to the
counter edge one-raster-row below after it has reached the left or right edges of the GRAM.
n
o
ti
Operation Examples:
a
c
fi
1) I/D = "1", AM = "0", LG2-0 = "001" (Logical OR)
2) WM11—0 = "000"H
3) AC = "0000"H
DB11
Write-data mask:
DB11
DB0
Read data (1):
1 0 0 1 1 0 0 1 0 1 0 0
Write data (1):
1 0 1 1 1 1 0 0 0 1 1 0
Read data (2):
0 0 0 0 1 1 1 1 0 0 0 0
Write data (2):
1 1 0 0 0 0 1 1 1 0 0 0
1 0 1 1 1 1 0 1 0 1 1 0
Read data (1) + Write data (1)
P
ry
Sp
Logical operation
(OR)
a
n
i
lim
"0000"H
re
i
c
e
DB0
0 0 0 0 0 0 0 0 0 0 0 0
1 0 1 1 1 1 0 1 0 1 1 0
Logical operation
(OR)
1 1 0 0 1 1 1 1 1 0 0 0
"0001"H
"0002"H
1 1 0 0 1 1 1 1 1 0 0 0
Read data (2) + Write data (2)
GRAM
Figure 40 Writing Operation of Read/Write Mode 1
54
HD66765
6. Read/Write mode 2: AM = 1, LG1–0 = 001/010/011
This mode is used when the data is vertically written at high speed by performing a logical operation
with the original data. It reads the display data (original data), which has already been written in the
GRAM, performs a logical operation with the write data sent from the microcomputer, and rewrites
the data to the GRAM. This mode can read the data during the same access-pulse width (68-system:
enabled high level, 80-system: RD* low level) as for the write operation since the read operation of
the original data does not latch the read data into the microcomputer and temporarily holds it in the
read-data latch. However, the bus cycle requires the same time as the read operation. The write-data
mask function (WM11–0) is also enabled in these operations. After writing, the address counter (AC)
automatically increments by 256, and automatically jumps to the upper-right edge (I/D = 1) or upperleft edge (I/D = 0) following the I/D bit after it has reached the lower edge of the GRAM.
n
o
ti
Operation Examples:
a
c
fi
1) I/D = "1", AM = "1", LG2-0 = "001" (Logical OR)
2) WM11—0 = "FF0"H
3) AC = "0000"H
DB11
Write-data mask:
DB11
DB0
Read data (1):
1 0 0 0 1 0 0 1 0 1 0 1
Write data (1):
1 0 1 1 1 1 0 0 0 1 1 0
Read data (2):
0 0 0 0 1 1 1 1 0 0 0 0
Write data (2):
1 1 0 0 0 0 1 1 1 0 0 0
"0000"H
im
l
e
"AF00"H
ry
Sp
Logical operation
(OR)
a
n
i
1 0 1 1 1 1 0 1 0 1 1 1
Logical operation
(OR)
1 1 0 0 1 1 1 1 1 0 0 0
* * * * * * * * 0 1 1 1 Read data (1) + Write data (1)
Pr
"0001"H
i
c
e
DB0
1 1 1 1 1 1 1 1 0 0 0 0
* * * * * * * * 1 0 0 0
Read data (2) + Write data (2)
GRAM
Note: 1. The bits in the GRAM indicated by ’*’ are not changed.
2. After writin to address "AF00"H, the AC jumps to "0001"H.
Figure 41 Writing Operation of Read/Write Mode 2
55
HD66765
7. Read/Write mode 3: AM = 0, LG2–0 = 100/101
This mode is used when the data is horizontally written by comparing the original data and the set
value of compare register (CP11–0). It reads the display data (original data), which has already been
written in the GRAM, compares the original data and the set value of the compare register in byte
units, and writes the data sent from the microcomputer to the GRAM only when the result of the
comparison satisfies the condition. This mode reads the data during the same access-pulse width (68system: enabled high level, 80-system: RD* low level) as write operation since reading the original
data does not latch the read data into the microcomputer but temporarily holds it in the read-data
latch. However, the bus cycle requires the same time as the read operation. The write-data mask
function (WM11–0) is also enabled in these operations. After writing, the address counter (AC)
automatically increments by 1 (I/D = 1) or decrements by 1 (I/D = 0), and automatically jumps to the
counter edge one-raster-row below after it has reached the left or right edges of the GRAM.
n
o
ti
a
c
fi
Operation Examples:
1) I/D = "1", AM = "0", LG2-0 = "100" (matched write)
2) CP11—0 = "530"H
3) WM11—0 = "000"H
4) AC = "0000"H
DB11
DB0
0 0 0 0 0 0 0 0 0 0 0 0
Write-data mask:
DB11
DB0
y
r
a
0 1 0 1 0 0 1 1 0 0 0 0
Compare register:
(Matched)
Read data (1):
Compare
operaton
in
C
Conditional
replacement
im
l
e
Pr
Write data (2):
Sp
0 1 0 1 0 0 1 1 0 0 0 0
Write data (1):
Read data (2):
i
c
e
1 0 1 1 1 1 0 0 0 1 1 0
R
0 0 0 0 1 1 1 1 0 0 0 0
C
Conditional
replacement
1 1 0 0 0 0 1 1 1 0 0 0
"0000"H
1 0 1 1 1 1 0 0 0 1 1 0
Compare
operaton
R
0 0 0 0 1 1 1 1 0 0 0 0
"0001"H
1 0 1 1 1 1 0 0 0 1 1 0
0 0 0 0 1 1 1 1 0 0 0 0
Matched replacement
write data (1)
GRAM
Figure 42 Writing Operation of Read/Write Mode 3
56
HD66765
8. Read/Write mode 4: AM = 1, LG2–0 = 100/101
This mode is used when the data is vertically written by comparing the original data and the set value
of the compare register (CP11–0). It reads the display data (original data), which has already been
written in the GRAM, compares the original data and the set value of the compare register in byte
units, and writes the data sent from the microcomputer to the GRAM only when the result of the
compare operation satisfies the condition. This mode reads the data during the same access-pulse
width (68-system: enabled high level, 80-system: RD* low level) as the write operation since reading
the original data does not latch the read data into the microcomputer but temporarily holds it in the
read-data latch. However, the bus cycle requires the same time as the read operation. The write-data
mask function (WM11–0) is also enabled in these operations. After writing, the address counter (AC)
automatically increments by 256, and automatically jumps to the upper-right edge (I/D = 1) or upperleft edge (I/D = 0) following the I/D bit after it has reached the lower edge of the GRAM.
n
o
ti
a
c
fi
Operation Examples:
1) I/D = "1", AM = "1", LG2-0 = "101" (ummatched write)
2) CP11—0 = "530"H
3) WM11—0 = "000"H
4) AC = "0000"H
DB11
Sp
0 0 0 0 0 0 0 0 0 0 0 0
Write-data mask:
DB11
Compare register:
DB0
ry
0 1 0 1 0 0 1 1 0 0 0 0
Compare
operaton
(unmatched)
Read data (1):
Write data (1):
Pr
Write data (2):
a
n
1 0 0 1 1 0 0 1 0 1 0 1
i
Conditional
replacement
R
1 0 1 1 1 1 0 0 0 1 1 0
Compare
operaton
0 1 0 1 0 0 1 1 0 0 0 0
C
Conditional
replacement
1 1 0 0 0 0 1 1 1 0 0 0
"0000"H
1 0 1 1 1 1 0 0 0 1 1 0
Write data (1)
"0001"H
0 1 0 1 0 0 1 1 0 0 0 0
Write data (2)
"AF00"H
C
1 0 1 1 1 1 0 0 0 1 1 0
im
l
e
Read data (2):
i
c
e
DB0
R
0 1 0 1 0 0 1 1 0 0 0 0
GRAM
Note: 1. The bits in the GRAM indicated by ’*’ are not changed.
2. After writin to address "AF00"H, the AC jumps to "0001"H.
Figure 43 Writing Operation of Read/Write Mode 4
57
HD66765
Grayscale Palette
The HD66765 incorporates a grayscale palette to simultaneously display 4,096 out of 13,824 possible
colors. The grayscales consist of sixteen five-bit palettes. The 24-stage grayscale levels can be selected
from the five-bit palette data.
In this palette, a pulse-width control system (PWM) is used to eliminate flicker in the LCD display. The
time over which the LCDs are switched on is adjusted according to the level and grayscales are displayed
so that flicker is reduced and grayscales are clearly displayed.
n
o
ti
Graphics RAM (GRAM)
a
c
fi
MSB
Display data
R3
R2
R1
R0
G3
4
G2
y
r
a
G0
Sp
4
<RGB> Palette
i
c
e
G1
B3
B2
B1
LSB
B0
4
"0000"
PK04 PK03 PK02 PK01 PK03
"1000"
PK84 PK83 PK82 PK81 PK80
"0001"
PK14 PK13 PK12 PK11 RK13
"1001"
PK94 PK93 PK92 PK91 RK90
"0010"
PK24 PK23 PK22 PK21 PK23
"1010" PK104 PK103 PK102 PK101 PK100
"0011"
PK34 PK33 PK32 PK31 PK33
"1011" PK114 PK113 PK112 PK111 PK110
in
lim
PK44 PK43 PK42 PK41 PK43
"1100" PK124 PK123 PK122 PK121 PK120
"0101"
PK54 PK53 PK52 PK51 PK53
"1101" PK134 PK133 PK132 PK131 PK130
"0110"
PK64 PK63 PK62 PK61 PK63
"1110" PK144 PK143 PK142 PK141 PK140
"0111"
PK74 PK73 PK72 PK71 PK73
"1111" PK154 PK153 PK152 PK151 PK150
"0100"
e
r
P
5
24 grayscale ontrol
<R>
LCD driver
5
24 grayscale ontrol
<G>
5
24 grayscale ontrol
<B>
LCD driver
R
G
LCD
Figure 44 Grayscale Palette Control
58
LCD driver
B
HD66765
Grayscale Palette Table
The grayscale register that is set for the RGB palette register (PK) can be set to any level. 24-grayscale
lighting levels can be set according to palette values (00000 to 10111).
Table 25
Grayscale Control Level
Palette Register Value (PK)
Grayscale Control Level
0
0
0
0
0
Unlit level*1
0
0
0
0
1
2/24 level
0
0
0
1
0
3/24 level
0
0
0
1
1
4/24 level
0
0
1
0
0
5/24 level
0
0
1
0
1
6/24 level
0
0
1
1
0
7/24 level
0
0
1
1
1
8/24 level
0
1
0
0
0
9/24 level
0
1
0
0
1
10/24 level
0
1
0
1
0
11/24 level
0
1
0
1
1
12/24 level
0
1
1
0
0
13/24 level
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
0
0
i
c
e
Sp
in
lim
1
a
c
fi
14/24 level
15/24 level
e
r
P
0
y
r
a
n
o
ti
16/24 level
0
17/24 level
1
18/24 level
1
0
19/24 level
0
1
1
20/24 level
0
1
0
0
21/24 level
1
0
1
0
1
22/24 level
1
0
1
1
0
23/24 level
1
0
1
1
1
All-lit level*2
Notes: 1. The unlit level corresponds to a black display when a normally-black color-LCD panel is used,
and a white display when a normally-white color-LCD panel is used.
2. The all-lit level corresponds to a white display when a normally-black color-LCD panel is used,
and a black display when a normally-white color-LCD panel is used.
59
HD66765
Common Driver Interface
The HD66765 and the HD66764 common driver can drive displays of up to 132 (RGB) × 176 dots in
size. Signals to set instructions for CR oscillation, the display timing signal, and the common driver are
supplied from the HD66765 to the common driver. The LCD drive voltage is generated by the common
driver. The LCD segment drive level (VSH) is also supplied from the common driver. On/off control of
the display is required to be controlled by both the common and segment driver. Follow the on/off
sequence of the display.
n
o
ti
SEG1 to 396
COM1 to 176
VSH
VSH
i
c
e
CL1
CL1
FLM
HD66765
(Segment driver)
M
DISPTMG
DCCLK
y
r
a
CCS*
OSC1
FLM
Sp
M
DISPTMG
HD66764
(Common driver)
DCCLK
CCS*
CCL
CCL
CDA
CDA
in
OSC2
Rf
a
c
fi
im
l
e
Note: The oscillation resistance (Rf)
must be located near the chip.
Pr
Figure 45 Connection to the Common Driver
60
HD66765
Common Driver Serial Transfer
The HD66765 has an on-chip serial circuit to interface with the common driver (HD66764). Registers of
the common driver can be set by transferring register settings from the HD66765. The serial interface
consists of the serial chip select (CCS*), serial transfer clock (CCL), and serial transfer data (CDA) lines.
The HD66765 serial interface circuit is only for transmitting, and cannot be used for receiving data from
the common driver.
Serial transfer is started by setting the serial transfer register (TE) in the HD66765 to 1. After TE has
been set to 1, CDA will be output in synchronization with CCS*, CCL, and CCL. Transfer is in 16-bit
blocks. The data transferred consists of a common driver index register (IDX2 to 0) and an instruction for
a register selected by IDX2 to 0. For more information on the common driver indices and instructions,
refer to the common-driver data sheet. Serial transfer is independent of the HD66765′s internal operation,
so other instructions can be executed during transfer. Serial transfer to the common driver requires a
maximum of 18 clock cycles.
n
o
ti
a
c
fi
i
c
e
When the serial transfer is finished, TE is automatically cleared to 0. After reading the register to confirm
that TE=0, serial transfer of the next instruction may be started.
Sp
a) Example of Interface with Common Driver HD66764
y
r
a
in
im
l
e
MPU
Pr
HD66764
HD66765
CCS*
CCL
CDA
CCS*
CCL
CDA
CS*
WR*
RD*
RS
DB15-0
16
b) Basic Serial Transfer
Transfer start
Transfer end
CCS*
(Output)
CCL
(Output)
1
2
3
4
5
6
7
8
9
10
11
12
MSB
CDA
(Output)
13
14
15
16
LSB
IDX2 IDX1 IDX0 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5
Index
DB4 DB3 DB2 DB1 DB0
Instruction data
Figure 46 Common Driver Serial Transfer
61
HD66765
c) Serial Transfer Sequence
Change the instruction bit setting
corresponding to the HD66765
Instruction setting change
Transfer to the common driver must be executed immediately after setting up the instruction
Index set R0Ah
Instruction read
n
o
ti
NO
(During transfer)
TE = "0"
a
c
fi
YES (Transfer can be executed)
Common side index (IDX2 to 0)
TE = 1 (transfer start)
i
c
e
Specify the IDX2 to 0 in the common side
instruction including a changed instruction bit
Sp
Figure 46 Common Driver Serial Transfer (cont)
y
r
a
Notes: 1. Transfer to the common driver must take place immediately after setting up the instruction.
2. The serial transfer period takes a maximum of 1/fosc × 18 clock cycles (sec).
3. Serial transfer cannot be executed in standby mode. If the chip enters standby mode during
transfer, the serial transfer is forcibly suspended. Transfer must be executed again after
standby has been canceled because correct transfer is not guaranteed in this situation.
4. Serial transfer can be forcibly suspended by writing TE=0. Transfer must be executed again
because correct transfer is not guaranteed in this situation.
5. The instruction bit for the common driver is not executed when it is not transferred to the
common driver. When the setting is changed, transfer must be executed again.
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When transfer to the common driver is executed, the transfer is executed by using one of the following
common driver (HD66764) instructions, corresponding to the value set by the IDX2 to 0.
Table 26
Common Driver (HD66764) Instructions
IDX2
IDX1
IDX0
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
BS2
BS1
BS0
BT3
BT2
BT1
BT0
0
AP1
AP0
SLP
0
0
1
0
0
0
0
0
0
0
0
0
0
VC2
VC1
VC0
0
1
0
0
VR3
VR2
VR1
VR0
0
CT6
CT5
CT4
CT3
CT2
CT1
CT0
0
1
1
0
0
D1
1
0
0
0
0
0
0
0
SE17 SE16 SE15 SE14 SE13 SE12 SE11 SE10
1
0
1
0
0
0
0
0
SS27 SS26 SS125 SS24 SS23 SS22 SS21 SS20
1
1
0
0
0
0
0
0
SE27 SE26 SE25 SE24 SE23 SE22 SE21 SE20
DC1 DC0
CMS SPT SS17 SS16 SS15 SS14 SS13 SS12 SS11 SS10
62
HD66765
Instruction Setting Flow
When the common driver HD66764 is used, follow the below about each instruction setting. The
instruction setting for the common driver is executed by the serial interface. When the instruction for the
common driver is set, the serial transfer must be executed to the common driver. The transfer to the
common driver must be executed immediately after the instruction set.
Follow the below serial transfer flow about each setting and then transfer must be executed.
[Display on/off]
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[Duty setting]
[Standby]
[Partial setting]
Display off (D1 to 0 = 00)
Serial transfer
Power off (AP1 to 0 = 00)
[Sleep]
Display off flow
Display
off
Standby
set
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p
Serial transfer
Oscillation start
Power setting
Partial setting
Duty setting, etc.
S
Wait 10 ms
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Standby set (STB = "1")
Standby
cancel
Display off flow
Sleep set (SLP = "1")
Serial transfer
Sleep cancel (SLP = "0")
Serial transfer
Standby cancel (STB = "0")
Display on (D1 to 0 = 10)
Serial transfer
Wait at least one frame
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Display on (D1 to 0 = 11)
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Serial transfer
Display
on
Power setting flow
Power setting
Display on flow
Display on flow
Note: For more information on the flow for power settings, refer to the common-driver data sheet.
Figure 47 Instruction Setting Flow
63
Sleep
set
Sleep
cancel
HD66765
Oscillation Circuit
The HD66765 can oscillate between the OSC1 and OSC2 pins using an internal R-C oscillator with an
external oscillation resistor. Note that in R-C oscillation, the oscillation frequency is changed according
to the external resistance value, wiring length, or operating power-supply voltage. If Rf is increased or
power supply voltage is decrease, the oscillation frequency decreases. For the relationship between Rf
resistor value and oscillation frequency, see the Electric Characteristics Notes section.
1) External Clock Mode
Clock
(200 KHz)
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OSC1
Damping
resistance (2 k ) OSC2
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HD66765
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2) External Resistance Oscillation Mode
OSC1
Sp
Note: The Rf resistance must be located near
the OSC1/OSC2 pin on the chip.
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Rf
OSC2
HD66765
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Figure 48 Oscillation Circuits
When using the HD66765 with the HD66764 common driver, the relationship between the SEG and
COM output levels is as shown in the following figure. The LCD drive level (VSH, VSL) which is used
by the HD66765 is supplied from the HD66764 common driver. While the display is off, SEG and COM
outputs go to GND level.
Pr
M
VCH
COM waveform
VSH
VM
VSL (GND)
No lit
Lit
Lit
Lit
SEG waveform
No lit No lit
VCL
Figure 49 Relationship with SEG/COM Output Level
64
HD66765
Frame-Frequency Adjustment Function
The HD66765 has an on-chip frame-frequency adjustment function. The frame frequency can be adjusted
by the instruction setting (DIV, RTN) during the LCD drive as the oscillation frequency is always same.
When the display duty is changed, the frame frequency can be adjusted to be the same.
If the oscillation frequency is set to high, an animation or a static image can be displayed in suitable ways
by changing the frame frequency. When a static image is displayed, the frame frequency can be set low
and the low-power consumption mode can be entered. When high-speed screen switching, for an
animated display, etc. is required, the frame frequency can be set high.
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Relationship between LCD Drive Duty and Frame Frequency
The relationship between the LCD drive duty and the frame frequency is calculated by the following
expression. The frame frequency can be adjusted in the retrace-line period bit (RTN) and in the operation
clock division bit (DIV) by the instruction.
a
c
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(Formula for the frame frequency)
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fosc
Sp
in
Frame frequency =
[Hz]
Clock cycles per raster-row × division ratio × 1/duty cycle
Pr
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fosc: R-C oscillation frequency
Duty: drive duty (NL bit)
Division ratio: DIV bit
Clock cycles per raster-row: (RTN + 25) clock cycles
65
HD66765
Example Calculation 1
To set the maximum frame frequency to 60 Hz
Display duty: 1/176
Retrace-line period: 0 clock (RTN3 to 0 = 0000)
Operation clock division ratio: 1 division
fosc = 60 Hz × (0 + 25) clock × 1 division × 176 lines = 264 (kHz)
n
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ti
In this case, the CR oscillation frequency becomes 264 kHz. The external resistance value of the CR
oscillator must be adjusted to be 264 kHz. The display duty can be changed by the partial display, etc.
and the frame frequency can be the same by setting the RNT bit and DIV bit to achieve the following.
a
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fi
Partial display
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Display duty: 1/40
Retrace-line period: 3 clock (RTN3 to 0 = 0011)
Operation clock division ratio: 4 division
Sp
Frame frequency = 264 kHz/ ((3 + 25) clock × 4 division × 40 lines) = 58.9 (Hz)
Example Calculation 2
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in
Switching the frame frequency to suit animation/static image display
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(Animation display)
Pr
Frame frequency: 90 Hz
Display duty: 1/176
Retrace-line period: 0 clock (RTN3 to 0 = 0000)
Operation clock division ratio: 1 division
fosc = 90 Hz × (0 + 25) clock × 1 division × 176 lines = 396 (kHz)
(Static image display)
Frame frequency: 60 Hz
Display duty: 1/176
Retrace-line period: 13 clock (RTN3 to 0 = 1101)
Operation clock division ratio: 1 division
Frame frequency: 396 kHz/ ((13 + 25) clock × 2 division × 176 lines) = 59.2 (Hz)
66
HD66765
n-raster-row Reversed AC Drive
The HD66765 supports not only the LCD reversed AC drive in a one-frame unit (B-pattern waveform)
but also the n-raster-row reversed AC drive which alternates in an n-raster-row unit from one to 64 rasterrows (C-pattern waveform). When a problem affecting display quality occurs, such as crosstalk at highduty driving of more than 1/64 duty, the n-raster-row reversed AC drive (C-pattern waveform) can
improve the quality.
Determine the number of raster-rows n (NW bit set value + 1) for alternating after confirmation of the
display quality with the actual LCD panel. However, if the number of AC raster-rows is reduced, the
LCD alternating frequency becomes high. Because of this, the charge or discharge current is increased in
the LCD cells.
a
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1 frame
1 frame
1 2 3 4 5 6 7 8 9 10 11 12 13
B-pat t ern
wa veform drive
• 1/80 duty
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C- pat tern
wav eform drive
• 1/80 duty
• 11-raster-row
revers al
• Without EORs
C- pat tern
wav eform drive
• 1/80 duty
• 11-rast er-row
reversal
• With EORs
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79 80 1 2 3 4 5 6 7 8 9 10 111213
79 80 1 2 3
Sp
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Note: Specify the numb er of AC drive raster-rows and the necess ity of EOR so that the DC bias is not generated f
the liquid crys tal.
Figure 50 Example of an AC Signal under n-raster-row Reversed AC Drive
67
HD66765
Screen-division Driving Function
The HD66765 can select and drive two screens at any position with the screen-driving position registers
(R14h and R15h). Any two screens required for display are selectively driven and a duty ratio is lowered
by LCD-driving duty setting (NL4-0), thus reducing LCD-driving voltage and power consumption.
For the 1st division screen, start line (SS17-10) and end line (SE17-10) are specified by the 1st screendriving position register (R14h). For the 2nd division screen, start line (SS27-20) and end line (SE27-20)
are specified by the 2nd screen-driving position register (R15h). The 2nd screen control is effective when
the SPT bit is 1. The total count of selection-driving lines for the 1st and 2nd screens must correspond to
the LCD-driving duty set value.
n
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1/24 duty driving on 2 screen
COM1
ca
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COM17
ec
COM26
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COM42
Sp
in
lim
Always applying
non-selection
level
2nd screen :
17 raster-row
driving
Always applying
non-selection
level
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- Driving duty : NL4-0 = "00010" (1/24 duty)
- 1st screen setting : SS17-10 = "00"H, SE17-10 = "06"H
- 2nd screen setting : SS27-20 = "19"H, SE27-20 = "29"H, SPT = "1"
Figure 51
1st screen :
7 raster-row
driving
Display example in 2-screen division driving
68
HD66765
Restrictions on the 1st/2nd Screen Driving Position Register Settings
The following restrictions must be satisfied when setting the start line (SS17-10) and end line (SE17-10)
of the 1st screen driving position register (R14) and the start line (SS27-20) and end line (SE27-20) of the
2nd screen driving position register (R15) for the HD66765. Note that incorrect display may occur if the
restrictions are not satisfied.
Table 27 Restrictions on the 1st/2nd Screen Driving Position Register Settings
1st Screen Driving (SPT = 0)
2nd Screen Driving (SPT = 1)
Register setting
SS17-10 ≤ SE17-0 ≤ AFH
SS17-10 ≤ SE17-10 < SS27-20
≤ SE27-20 ≤ AFH
Display operation
• Time-sharing driving for COM pins
(SS1+1) to (SE1+1)
• Non-selection level driving for others
• Time-sharing driving for COM pins
(SS1+1) to (SE1+1) and (SS2+1) to
(SE2+1)
• Non-selection level driving for others
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Notes: 1. When the total line count in screen division driving settings is less than the duty setting, nonselection level driving is performed without the screen division driving setting range.
2. When the total line count in screen division driving settings is larger than the duty setting, the
start line, the duty-setting line, and the lines between them are displayed and non-selection
level driving is performed for other lines.
3. For the 1st screen driving, the SS27-20 and SE27-20 settings are ignored.
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69
HD66765
Modification history
Revision 0.1
-
First release
HD66765
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1.
This document may, wholly or partially, be subject to change without notice.
2.
All right reserved: No one is permitted to reproduce or duplicated, in any form, the whole or part of this
document without Hitachi's permission.
3.
Hitachi will not be held responsible for any damage to the user that may result from accidents or any
other reasons during operation of the user's unit according to this document.
4.
Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi's semiconductor products.
Hitachi assumes no responsibility for any
intellectual property claims or other problems that may result from applications based on the examples
described herein.
5.
No license is granted by implication or otherwise under any patents or other rights of any third party of
Hitachi, Ltd.
6.
MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company.
Such use includes, but is not limited to use in life support systems. Buyers of Hitachi's products are
requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.