Revised June 2003 FIN1028 3.3V LVDS 2-Bit High Speed Differential Receiver General Description Features This dual receiver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The receiver translates LVDS levels, with a typical differential input threshold of 100 mV, to LVTTL signal levels. LVDS provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data. ■ Greater than 400Mbs data rate The FIN1028 can be paired with its companion driver, the FIN1027, or any other LVDS driver. ■ Fail safe protection for open-circuit, shorted and terminated conditions ■ 3.3V power supply operation ■ 0.4ns maximum differential pulse skew ■ 2.5ns maximum propagation delay ■ Low power dissipation ■ Power-Off protection ■ Meets or exceeds the TIA/EIA-644 LVDS standard ■ Flow-through pinout simplifies PCB layout ■ 8-Lead SOIC and 8-terminal MLP packages save space Ordering Code: Order Number Package Number FIN1028M (Note 1) M08A FIN1028MPX (Preliminary) Package Description 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow MLP08C 8-Terminal Molded Leadless Package (MLP) Dual, JEDEC MO-229, 2mm Square [TAPE and REEL] Note 1: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pin Descriptions Connection Diagrams Pin Name Description ROUT1, ROUT2 Pin Assignment for SOIC LVTTL Data Outputs RIN1+, RIN2+ Non-inverting LVDS Inputs RIN1−, RIN2− Inverting LVDS Inputs VCC Power Supply GND Ground Function Table Input Outputs RIN+ RIN+ L H L H L H ROUT Fail Safe Condition (Top View) H Terminal Assignments for MLP H = HIGH Logic Level L = LOW Logic Level Fail Safe = Open, Shorted, Terminated (Top Through View) © 2003 Fairchild Semiconductor Corporation DS500503 www.fairchildsemi.com FIN1028 3.3V LVDS 2-Bit High Speed Differential Receiver March 2001 FIN1028 Absolute Maximum Ratings(Note 2) Supply Voltage (VCC) −0.5V to +4.6V Recommended Operating Conditions DC Input Voltage (RINx+, RINx−) −0.5V to +4.7V Supply Voltage (VCC) DC Output Voltage (ROUTx) −0.5V to +6V DC Output Current (IO) 16 mA Storage Temperature Range (TSTG) 0 to VCC Magnitude of Differential Voltage −65°C to +150°C (|VID|) 100 mV to VCC 150°C Common-mode Input Voltage (Soldering, 10 seconds) 260°C ESD (Human Body Model) ≥ 6500V Operating Temperature (TA) Max Junction Temperature (TJ) Lead Temperature (TL) (VIC) 0.05V to 2.35V −40°C to +85°C Note 2: The “Absolute Maximum Ratings”: are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specification. ≥ 300V ESD (Machine Model) 3.0V to 3.6V Input Voltage (VIN) DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol Parameter Min Test Conditions VTH Differential Input Threshold HIGH See Figure 1 and Table 1 VTL Differential Input Threshold LOW See Figure 1 and Table 1 Typ Max (Note 3) 100 −100 Units mV mV IIN Input Current VIN = 0V or VCC ±20 µA II(OFF) Power-OFF Input Current VCC = 0V, VIN = 0V or 3.6V ±20 µA VOH Output HIGH Voltage IOH = −100 µA VCC −0.2 IOH = −8 mA VOL Output LOW Voltage V 2.4 IOH = 100 µA 0.2 IOL = 8 mA 0.5 −1.5 V VIK Input Clamp Voltage IIK = −18 mA ICC Power Supply Current (RIN+ = 1V and RIN− = 1.4V) or CIN Input Capacitance 4 pF COUT Output Capacitance 6 pF V 9 (RIN+ = 1.4V and RIN− = 1V) mA Note 3: All typical values are at TA = 25°C and with VCC = 3.3V. AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified Symbol tPLH Parameter Test Conditions Differential Propagation Delay Typ Differential Propagation Delay 2.5 0.9 HIGH-to-LOW Max (Note 4) 0.9 LOW-to-HIGH tPHL Min 2.5 tTLH Output Rise Time (20% to 80%) |VID| = 400 mV, CL = 10 pF, 0.5 tTHL Output Fall Time (80% to 20%) See Figure 1 and Figure 2 0.5 tSK(P) Pulse Skew |tPLH - tPHL| tSK(LH), Channel-to-Channel Skew tSK(HL) (Note 5) tSK(PP) Part-to-Part Skew (Note 6) Units ns ns ns ns 0.4 ns 0.3 ns 1.0 ns Note 4: All typical values are at TA = 25°C and with VCC = 3.3V. Note 5: tSK(LH), tSK(HL) is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direction. Note 6: tSK(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction (either LOW-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits. www.fairchildsemi.com 2 FIN1028 Note A: All input pulses have frequency = 10 MHz, tR or tF = 1 ns Note B: CL includes all probe and fixture capacitances FIGURE 1. Differential Driver Propagation Delay and Transition Time Test Circuit TABLE 1. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages (V) Resulting Differential Input Voltage (mV) Resulting Common Mode Input Voltage (V) VIC VIA VIB VID 1.25 1.15 100 1.2 1.15 1.25 −100 1.2 2.4 2.3 100 2.35 2.3 2.4 −100 2.35 0.1 0 100 0.05 0 0.1 −100 0.05 1.5 0.9 600 1.2 0.9 1.5 −600 1.2 2.4 1.8 600 2.1 1.8 2.4 −600 2.1 0.6 0 600 0.3 0 0.6 −600 0.3 FIGURE 2. AC Waveforms 3 www.fairchildsemi.com FIN1028 DC /AC Typical Performance Curves FIGURE 3. Output High Voltage vs. Power Supply Voltage FIGURE 4. Output Low Voltage vs. Power Supply Voltage FIGURE 5. Output Short Circuit Current vs. Power Supply Voltage FIGURE 6. Power Supply Current vs. Frequency FIGURE 8. Differential Propagation Delay vs. Power Supply Voltage FIGURE 7. Power Supply Current vs. Ambient Temperature www.fairchildsemi.com 4 FIN1028 DC /AC Typical Performance Curves (Continued) FIGURE 9. Differential Propagation Delay vs. Ambient Temperature FIGURE 10. Differential Skew (tPLH - tPHL) vs. Power Supply Voltage FIGURE 12. Differential Propagation Delay vs. Differential Input Voltage FIGURE 11. Differential Skew (tPHL - tPHL) vs. Ambient Temperature FIGURE 13. Differential Propagation Delay vs. Common-Mode Voltage FIGURE 14. Transition Time vs. Power Supply Voltage 5 www.fairchildsemi.com FIN1028 DC /AC Typical Performance Curves (Continued) FIGURE 15. Transition Time vs. Ambient Temperature FIGURE 16. Differential Propagation Delay vs. Load FIGURE 17. Differential Propagation Delay vs. Load FIGURE 18. Transition Time vs. Load FIGURE 19. Transition Time vs. Load FIGURE 20. Power Supply Current vs. Power Supply Voltage www.fairchildsemi.com 6 TAPE FORMAT for MLP Ao Bo Package ±0.10 ±0.10 2x2 2.30 2.30 D D1 E F Ko P1 Po P2 T TC W Wc ±0.05 Min ±0.1 ±0.1 ±0.1 TYP TYP ±0/05 TYP ±0.005 ±0.3 TYP 1.55 1.0 1.75 3.5 1.0 8.0 4.0 2.0 0.3 0.06 8.0 5.3 MLP Embossed Tape Dimensions (Dimensions are in millimeters) REEL DIMENSIONS (millimeters) Tape Width Dia A Max Dim B Min Dia C +0.5/−0.2 Dia D Min Dim N Min Dim W1 +2/−0 Dim W2 Max Dim W3 (LSL - USL) 8 mm 330 1.5 13 20.2 178 8.4 14.4 7.9 ∼ 10.4 7 www.fairchildsemi.com FIN1028 Tape and Reel Specification FIN1028 Physical Dimensions inches (millimeters) unless otherwise noted 8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M08A www.fairchildsemi.com 8 FIN1028 3.3V LVDS 2-Bit High Speed Differential Receiver Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 8-Terminal Molded Leadless Package (MLP) Dual, JEDEC MO-229, 2mm Square Package Number MLP08C (Preliminary) Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com