TI1 DRV8806 Quad serial interface low-side driver ic Datasheet

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DRV8806
SLVSBA3C – JUNE 2012 – REVISED DECEMBER 2015
DRV8806 Quad Serial Interface Low-Side Driver IC
1 Features
3 Description
•
The DRV8806 provides a 4-channel low-side driver
with overcurrent protection. It has built-in diodes to
clamp turnoff transients generated by inductive loads
and can be used to drive unipolar stepper motors, DC
motors, relays, solenoids, or other loads.
1
•
•
•
4-Channel Protected Low-Side Driver
– Four NMOS FETs With Overcurrent Protection
– Integrated Inductive Clamp Diodes
– Serial Interface
– Open/Shorted Load Detection
2-A (Single Channel On)/1-A (All Channels On)
Maximum Drive Current per Channel (at 25°C)
8.2-V to 40-V Operating Supply Voltage Range
Thermally-Enhanced Surface Mount Package
2 Applications
•
•
•
•
The DRV8806 can supply up to 2-A (single channel
on) or 1-A (all channels on) continuous output current
(with adequate PCB heatsinking at 25°C).
A serial interface is provided to control the output
drivers. Fault status can be read through the serial
interface. Multiple DRV8806 devices can be chained
together to use a single serial interface.
Internal shutdown functions are provided for
overcurrent protection, short-circuit protection,
undervoltage lockout, and overtemperature, and
faults are indicated by a fault output pin.
Relay Drivers
Unipolar Stepper Motor Drivers
Solenoid Drivers
General Low-Side Switch Applications
The DRV8806 is available in a 16-pin HTSSOP
package (Eco-friendly: RoHS & no Sb/Br).
Device Information(1)
PART NUMBER
DRV8806
PACKAGE
HTSSOP (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
8.2V to 40V
RESET
nFAULT
Fault
Protection
Clamp
Diodes
1A
M
1A
1A
±
Controller
DRV8806
Quad
Low-Side
Driver
+
Serial
4 Interface
+
±
1A
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8806
SLVSBA3C – JUNE 2012 – REVISED DECEMBER 2015
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
4
4
4
5
5
6
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes........................................ 10
8
Application and Implementation ........................ 13
8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
9 Power Supply Recommendations...................... 15
10 Layout................................................................... 16
10.1 Layout Guidelines ................................................. 16
10.2 Layout Example .................................................... 16
10.3 Thermal Considerations ........................................ 16
11 Device and Documentation Support ................. 18
11.1
11.2
11.3
11.4
11.5
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
18
18
18
18
18
12 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (December 2013) to Revision C
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
Changes from Revision A (November 2013) to Revision B
Page
•
Changed (OPEN-DRAIN to PUSH-PULL in the elec chara table section SDATAOUT OUTPUT ......................................... 5
•
Added another row below VOH - merge the first two columns together (VOH and Output high voltage). The second
row should have test condition "Io = 100 uA, VM = 8.2 V" and be specified as 2.5 V MIN ................................................... 5
•
Added two new rows, ISRC and ISNK in elec chara table, section SDATAOUT OUTPUT........................................................ 5
•
Changed NO. 6 in Timing Requirements table ...................................................................................................................... 6
•
Added a sentence in second paragraph below Figure 2: A pullup resistor......1 kohm is recommended. ........................... 10
Changes from Original (June 2012) to Revision A
Page
•
Added comment to Timing Requirements section.................................................................................................................. 6
•
Changed Functional Block Diagram at SDATOUT................................................................................................................. 8
•
Changed Figure 6 at SDATOUT........................................................................................................................................... 10
•
Changed SDATOUT description in Serial Interface Operation section ................................................................................ 10
2
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5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View
VM
VCLAMP
OUT1
OUT2
GND
OUT3
OUT4
nENBL
1
16
2
15
14
13
3
4
GND
5
6
7
12
11
10
9
8
nFAULT
SDATOUT
SDATIN
SCLK
GND
LATCH
NC
RESET
Pin Functions
PIN
NAME
NO.
I/O (1)
DESCRIPTION
EXTERNAL COMPONENTS
OR CONNECTIONS
POWER AND GROUND
5, 12,
PowerPAD™
—
Device ground
All pins must be connected to GND.
1
—
Device power supply
Connect to motor supply (8.2 V - 40 V).
LATCH
11
I
Latch input
Rising edge latches shift register to output stage,
falling edge latches fault data into output shift
register – internal pulldown
nENBL
8
I
Enable input
Active low enables outputs – internal pulldown
RESET
9
I
Reset input
Active-high reset input initializes internal logic –
internal pulldown
SCLK
13
I
Serial clock
Serial clock input – internal pulldown
SDATIN
14
I
Serial data input
Serial data input – internal pulldown
SDATOUT
15
OD
Serial data output
Serial data output; push-pull structure; see serial
interface section for details
16
OD
Fault
Logic low when in fault condition
(overtemperature, overcurrent, open load) - opendrain output
OUT1
3
O
Output 1
Connect to load 1
OUT2
4
O
Output 2
Connect to load 2
OUT3
6
O
Output 3
Connect to load 3
OUT4
7
O
Output 4
Connect to load 4
VCLAMP
2
—
Output clamp voltage
Connect to VM supply, or zener diode to VM
supply
GND
VM
CONTROL
STATUS
nFAULT
OUTPUT
(1)
Directions: I = input, O = output, OD = open-drain output.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN
MAX
UNIT
VM
Power supply voltage
–0.3
43
V
VOUTx
Output voltage
–0.3
43
V
VCLAMP
Clamp voltage
–0.3
43
V
SDATOUT,
nFAULT
Output current
20
mA
2
A
1
A
Peak clamp diode current
(3)
DC or RMS clamp diode current (3)
SDATOUT,
nFAULT
Digital input pin voltage
–0.5
7
V
Digital output pin voltage
–0.5
7
V
Internally limited
A
Peak motor drive output current, t < 1 μS
Continuous total power dissipation
(3)
See Thermal Information
TJ
Operating virtual junction temperature (3)
–40
150
°C
Tstg
Storage temperature
–60
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
Power dissipation and thermal limits must be observed.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
UNIT
±6000
V
±1000
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
VM
Power supply voltage
VCLAMP
Output clamp voltage (1)
IOUT
(1)
(2)
4
Continuous output current, single channel on, TA = 25°C
(2)
Continuous output current, four channels on, TA = 25°C (2)
NOM
MAX
UNIT
8.2
40
V
0
40
V
2
A
1
A
VCLAMP is not a power supply input pin - it only connects to the output clamp diodes.
Power dissipation and thermal limits must be observed.
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6.4 Thermal Information
DRV8806
THERMAL METRIC (1)
PWP (HTSSOP)
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
39.6
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
24.6
°C/W
RθJB
Junction-to-board thermal resistance
20.3
°C/W
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
20.1
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
2.3
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics
TA = 25°C, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
1.6
3
UNIT
POWER SUPPLIES
IVM
VM operating supply current
VM = 24 V
VUVLO
VM undervoltage lockout
voltage
VM rising
mA
8.2
V
0.8
V
LOGIC-LEVEL INPUTS (SCHMITT TRIGGER INPUTS WITH HYSTERESIS)
VIL
Input low voltage
VIH
Input high voltage
VHYS
Input hysteresis
IIL
Input low current
VIN = 0
IIH
Input high current
VIN = 3.3 V
RPD
Pulldown resistance
2
V
0.45
–20
V
20
μA
100
μA
100
kΩ
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL
Output low voltage
IO = 5 mA
IOH
Output high leakage current
VO = 3.3 V
0.5
V
1
μA
SDATOUT OUTPUT (PUSH-PULL OUTPUT WITH INTERNAL PULLUP)
VOL
Output low voltage
IO = 5 mA
0.5
IO = 100 µA, VM = 11 V - 60 V, peak
V
6.5
IO = 100 µA, VM = 11 V - 60 V, steady state
3.3
IO = 100 µA, VM = 8.2 V - 11 V, steady state
2.5
4.5
5.6
V
VOH
Output high voltage
ISRC
Output source current
VM = 24 V
1
mA
ISNK
Output sink current
VM = 24 V
5
mA
V
LOW-SIDE FETS
RDS(ON)
FET on resistance
IOFF
Open load detect current
VM = 24 V, IO = 700 mA, TJ = 25°C
0.5
VM = 24 V, IO = 700 mA, TJ = 85°C
0.75
0.8
25
50
μA
–50
50
μA
0
Ω
HIGH-SIDE DIODES
VF
Diode forward voltage
VM = 24 V, IO = 700 mA, TJ = 25°C
IOFF
Off state leakage current
VM = 24 V, TJ = 25°C
0.9
V
tR
Rise time
VM = 24 V, IO = 700 mA, Resistive load
50
300
ns
tF
Fall time
VM = 24 V, IO = 700 mA, Resistive load
50
150
ns
3
5
A
OUTPUTS
PROTECTION CIRCUITS
IOCP
Overcurrent protection trip level
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Electrical Characteristics (continued)
TA = 25°C, over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tOCP
Overcurrent protection deglitch
time
3.5
µs
tOL
Open load detect deglitch time
15
µs
tRETRY
Overcurrent protection re-try
time
1.2
ms
TTSD
Thermal shutdown temperature
Die temperature
150
160
180
°C
6.6 Timing Requirements
over operating free-air temperature range (unless otherwise noted) (1)
MIN
NOM
MAX
UNIT
1
tCYC
Clock cycle time
62
ns
2
tCLKH
Clock high time
25
ns
3
tCLKL
Clock low time
25
ns
4
tSU(SDATIN)
Setup time, SDATIN to SCLK
5
ns
5
tH(SDATIN)
Hold time, SDATIN to SCLK
1
ns
6
tD(SDATOUT)
Delay time, SCLK to SDATOUT, no external pullup resistor,
COUT = 100 pF
7
tW(LATCH)
Pulse width, LATCH
8
tOE(ENABLE)
Enable time, nENBL to output low
50
100
200
ns
ns
60
ns
9
tD(LATCH)
Delay time, LATCH to output change
—
tRESET
RESET pulse width
20
µs
10
tD(RESET)
Reset delay before clock
20
µs
11
tSTARTUP
Start-up delay VM applied before clock
55
µs
(1)
200
ns
Not production tested.
10
RESET
nENBL
7
VM
11
1
SCLK
LATCH
2
3
Data in
valid
SDATIN
4
SDATOUT
OUTx
8
5
Data out valid
9
CLK
6
More than 400 ns of delay should exist between the final SCLK rising edge and the LATCH rising edge. This ensures
that the last data bit is shifted into the device properly.
Figure 1. DRV8806 Timing Requirements
6
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2000
2.00
1950
1.95
1900
1.90
Supply Current (mA)
Supply Current (mA)
6.7 Typical Characteristics
1850
1800
1750
1700
1650
1600
1.85
1.80
1.75
1.70
1.65
1.60
1550
9V
24 V
0° C
25° C
85° C
9V
Temperature (ƒC)
Figure 2. Supply Current vs Temperature
600
600
500
500
Rdson (mŸ)
700
400
300
24 V
25° C
400
300
100
43 V
0° C
0° C
8V
C004
Figure 4. RDS(ON) vs Temperature
25° C
85° C
0
85° C
Temperature (ƒC)
C002
200
9V
0
43 V
Figure 3. Supply Current vs Supply Voltage
700
100
24 V
Supply Voltage (V)
C001
200
25° C
85° C
1.50
1500
Rdson (mŸ)
0° C
1.55
43 V
60 V
Supply Voltage (V)
Figure 5. RDS(ON) vs Supply Voltage
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7 Detailed Description
7.1 Overview
The DRV8806 is an integrated 4-channel low-side driver controlled using a serial interface to change the state of
the low-side driver outputs. The low-side driver outputs consist of four N-channel MOSFETs that have a typical
RDS(ON) of 500 mΩ. A single motor supply input VM serves as device power and is internally regulated to power
the low-side gate drive. Data is shifted into a temporary data register in the device through the SDATIN pin, one
bit at each rising edge of SCLK, while LATCH is held low. The outputs of the device can be disabled by pulling
nENBL logic high. Several safety features are integrated in the device including overcurrent protection, thermal
shutdown, undervoltage lockout, and open load protection. The overcurrent protection and open load faults share
a fault bit per channel that is set when one of these conditions occurs.
7.2 Functional Block Diagram
8.2V - 40V
Internal
Reference
Regs
UVLO
VM
LS Gate
Drive
OCP,
Open
load,
Gate
Drive
nENBL
LATCH
8.2V - 40V
Optional
Zener
Int. VCC
VCLAMP
OUT1
Inductive
Load
SDATIN
SDATOUT
Control
Logic
SCLK
OCP,
Open
load,
Gate
Drive
OCP,
Open
load,
Gate
Drive
RESET
OUT2
Inductive
Load
OUT3
Inductive
Load
nFAULT
Thermal
Shut down
OCP,
Open
load,
Gate
Drive
OUT4
Inductive
Load
GND
(multiple pins)
8
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7.3 Feature Description
7.3.1 Output Drivers
The DRV8806 contains four protected low-side drivers. Each output has an integrated clamp diode connected to
a common pin, VCLAMP.
VCLAMP can be connected to the main power supply voltage, VM. It can also be connected to a Zener or TVS
diode to VM, allowing the switch voltage to exceed the main supply voltage VM. This connection can be beneficial
when driving loads that require very fast current decay, such as unipolar stepper motors.
In all cases, the voltage on the outputs must not be allowed to exceed the maximum output voltage specification.
7.3.2 Protection Circuits
The DRV8806 is fully protected against undervoltage, overcurrent and overtemperature events.
7.3.2.1 Overcurrent Protection (OCP)
An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than the tOCP deglitch time (approximately 3.5 µs), the driver will be
disabled and the nFAULT pin will be driven low. The driver will remain disabled for the tRETRY retry time
(approximately 1.2 ms), then the fault will be automatically cleared. The fault will be cleared immediately if either
RESET pin is activated or VM is removed and reapplied.
7.3.2.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all output FETs will be disabled and the nFAULT pin will be driven low.
Once the die temperature has fallen to a safe level, operation will automatically resume.
7.3.2.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled, and internal logic will be reset. Operation will resume when VM rises above the UVLO
threshold.
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7.4 Device Functional Modes
7.4.1 Serial Interface Operation
The DRV8806 is controlled with a simple serial interface. Logically, the interface is shown in Figure 6.
nENBL
LATCH
RESET
SCLK
SDATIN
D
Q
D
OUT1
Q
CLR
CLR
D
Q
D
OUT2
Q
CLR
CLR
D
Q
D
OUT3
Q
CLR
CLR
D
Q
D
OUT4
Q
CLR
CLR
D
Q
CLR
0
SDATOUT
1
from fault register
Figure 6. Serial Interface Operation
Data is shifted into a temporary holding shift register in the part using the SDATIN pin, one bit at each rising
edge of the SCLK pin, while LATCH is low. Data is shifted from the last bit to the SDATOUT pin, so multiple
devices may be daisy-chained together using a single serial interface.
Note that the SDATOUT pin has a push-pull driver, which can support driving another DRV8806 SDATIN pin at
clock frequencies of up to 1 MHz without an external pullup. A pullup resistor can be used between SDATOUT
and an external 5-V logic supply to support higher clock frequencies. TI recommends a resistor value of
approximately 1 kΩ. The SDATOUT pin is capable of approximately 1-mA source and 5-mA sink. To supply logic
signals to a lower-voltage microcontroller, use a resistor divider from SDATOUT to GND.
A rising edge on the LATCH pin latches the data from the temporary shift register into the output stage.
10
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Device Functional Modes (continued)
7.4.2 Fault Output Register
The DRV8806 contains circuitry to detect open or shorted loads. The status of the loads can be read through the
serial interface. The logic is shown in Figure 7.
From output SR
OUT1
OCP,
Open load,
Gate Drive
Open
load
25µA
OCP
S
Q
OCP_FAULT
nFAULT
R
from
other ch.
S
Q
OPEN_FAULT
R
Overtemp
SDATIN
1
0
D
LD
Q
SCLK
CLR
1
from output 2
0
D
LD
Q
CLR
LATCH
D
Q
RESET
1
from output 3
0
CLR
D
LD
Q
CLR
1
from output 4
0
Internal regulator
5.5 V maximum
D
LD
Q
CLR
0
SDATOUT
1
from fault register
Figure 7. Fault Output
To overcome any leakage currents to accurately sense an open load, a small current source is connected to
each output pin. This source pulls approximately 25-µA of current to ground. The voltage on the output pin is
sensed during the time that the output is off, and if the voltage on the pin is less than 1.2 V (indicating that there
is no load connected) after the open load deglitch time, the OPEN_FAULT latch is set. This latch is cleared
whenever the output bit is set.
When the output is turned on, if an overcurrent (OCP) fault is detected, the channel will be turned off and the
OCP_FAULT latch is set. This latch will be cleared whenever the output bit is cleared.
The state of the OCP_FAULT and OPEN_FAULT signals is combined into a single fault bit per channel, and
loaded into a shift register while the LATCH pin is low. When the LATCH pin is taken high, the fault data is
latched into the shift register at the first falling edge of SCLK. Data may then be shifted out on the SDATOUT pin
on each falling edge of the SCLK pin.
Note that the LATCH signal must be high for a minimum of 200 ns before valid data can be clocked out.
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Device Functional Modes (continued)
The nFAULT pin will be driven active low whenever any of the OCP_FAULT or OPEN_FAULT latches are set, as
well as whenever there is an overtemperature condition.
7.4.3 Daisy-Chain Connection
Two or more DRV8806 devices may be connected together to use a single serial interface. The SDATOUT pin of
the first device in the chain is connected to the SDATIN pin of the next device. The SCLK, LATCH, RESET, and
nFAULT pins are connected together.
+
+
DRV8806 “A”
SDATIN
SCLK
LATCH
SDATOUT
SDATIN
SCLK
LATCH
RESET
RESET
nFAULT
nFAULT
DRV8806 “B”
SDATOUT
SDATOUT
SDATIN
SCLK
LATCH
RESET
nFAULT
Figure 8. Daisy-Chain Connection
Figure 9 shows an example of a serial transaction, writing the output bits, and then reading the fault status bits,
using two devices connected together in a daisy-chain.
Note that the LATCH signal must be high for a minimum of 200 ns before valid data can be clocked out.
LATCH
Fault data latched
SCLK
SDATI
SDATO
OUTx
1
OUTB4
2
OUTB3
3
4
OUTB2
5
OUTB1
OUTA4
6
OUTA3
PREVIOUS WRITE DATA
7
OUTA2
8
1
2
3
4
5
6
7
8
OUTA1
FLTB4
FLTB3
FLTB2
OLD OUTPUT
FLTB1
FLTA4
FLTA3
FLTA2
FLTA1
NEW OUTPUT
Figure 9. Daisy-Chain Serial Transaction
7.4.4 nENBL and RESET Operation
The nENBL pin enables or disables the output drivers. nENBL must be low to enable the outputs. nENBL does
not affect the operation of the serial interface logic. Note that nENBL has an internal pulldown.
The RESET pin, when driven active high, resets internal logic, including the OCP fault. All serial interface
registers are cleared. Note that RESET has an internal pulldown. An internal power-up reset is also provided, so
it is not required to drive RESET at power up.
12
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DRV8806 can be used to drive one unipolar stepper motor.
8.2 Typical Application
VM
+
0.1µF
100µF
1
2
t
3
M
+
4
5
+
t
6
7
8
VM
nFAULT
VCLAMP
SDATOUT
OUT1
SDATIN
OUT2 DRV8806 SCLK
GND
GND
OUT3
LATCH
OUT4
NC
nENBL
RESET
16
15
14
13
12
11
10
9
Figure 10. DRV8806 Typical Application
8.2.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Supply voltage, VM
24 V
Motor winding resistance, RL
7.4 Ω/phase
Motor full step angle, θstep
1.8°/step
Motor rated current, IRATED
0.75 A
SCLK frequency, fSCLK
1 MHz
8.2.2 Detailed Design Procedure
8.2.2.1 Motor Voltage
The motor voltage to use will depend on the ratings of the motor selected and the desired torque. A higher
voltage shortens the current rise time in the coils of the stepper motor allowing the motor to produce a greater
average torque. Using a higher voltage also allows the motor to operate at a faster speed than a lower voltage.
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8.2.2.2 Drive Current
The current path is starts from the supply VM, moves through the inductive winding load, and low-side sinking
NMOS power FET. Power dissipation losses in one sink NMOS power FET are shown in Equation 1.
P = I2 × RDS(on)
(1)
The DRV8806 has been measured to be capable of 2-A Single Channel or 1-A Four Channels in a HTSSOP
package at 25°C on standard FR-4 PCBs. The maximum RMS current varies based on PCB design and the
ambient temperature.
8.2.3 Application Curves
16-Ω, 1-mH, RL Load
16-Ω, 1-mH RL Load
Figure 11. Current Ramp With VM = 8.2 V
Output shorted to VM
Figure 12. Current Ramp With VM = 24 V
Output shorted to VM
Figure 13. OCP With 8.2 V
14
Figure 14. OCP With 24 V
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9 Power Supply Recommendations
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance needed depends on a variety of factors, including
• Highest current required by the motor system
• Power supply’s capacitance and ability to source current
• Amount of parasitic inductance between the power supply and motor system
• Acceptable voltage ripple
• Type of motor used (Brushed DC, Brushless DC, Stepper)
• Motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.
Power Supply
Parasitic Wire
Inductance
Motor Drive System
VM
+
+
±
Motor
Driver
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
Figure 15. Example Setup of Motor Drive System
With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
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10 Layout
10.1 Layout Guidelines
The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver
device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used
when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high
current.
Small-value capacitors should be ceramic, and placed closely to device pins.
The high-current device outputs should use wide metal traces.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias help dissipate the
I² x RDS(on) heat that is generated in the device.
10.2 Layout Example
+
VM
nFAULT
VCLAMP
SDATOUT
OUT1
SDATIN
OUT2
SCLK
GND
GND
OUT3
LATCH
OUT4
NC
nENBL
RESET
Figure 16. Layout Recommendation
10.3 Thermal Considerations
The DRV8806 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately
150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
10.3.1 Power Dissipation
Power dissipation in the DRV8806 is dominated by the power dissipated in the output FET resistance, or RDS(ON).
Average power dissipation of each FET when running a static load can be roughly estimated by Equation 2:
P = RDS(ON) · (IOUT)2
where
•
•
•
16
P is the power dissipation of one FET
RDS(ON) is the resistance of each FET
IOUT is equal to the average current drawn by the load
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Thermal Considerations (continued)
Note that at start-up and fault conditions this current is much higher than normal running current; these peak
currents and their duration also must be considered. When driving more than one load simultaneously, the power
in all active output stages must be summed.
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that RDS(ON) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.
10.3.2 Heatsinking
The PowerPAD™ package uses an exposed pad to remove heat from the device. For proper operation, this pad
must be thermally connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane,
this can be accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs
without internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area
is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and
bottom layers.
For details about how to design the PCB, see the TI application report, PowerPAD™ Thermally Enhanced
Package (SLMA002), and TI application brief, PowerPAD™ Made Easy (SLMA004), available at www.ti.com.
In general, the more copper area that can be provided, the more power can be dissipated.
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
• PowerPAD™ Thermally Enhanced Package SLMA002
• PowerPAD™ Made Easy SLMA004
11.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
DRV8806PWP
ACTIVE
HTSSOP
PWP
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8806
DRV8806PWPR
ACTIVE
HTSSOP
PWP
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
DRV8806
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Nov-2014
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Nov-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DRV8806PWPR
Package Package Pins
Type Drawing
SPQ
HTSSOP
2000
PWP
16
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Nov-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DRV8806PWPR
HTSSOP
PWP
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
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