a FEATURES Fast Throughput Rate: 1 MSPS Specified for VDD of 2.7 V to 5.25 V Low Power: 4.5 mW Max at 1 MSPS with 3 V Supplies 10.5 mW Max at 1 MSPS with 5 V Supplies Wide Input Bandwidth: 68 dB SNR at 300 kHz Input Frequency Flexible Power/Serial Clock Speed Management No Pipeline Delays High-Speed Serial Interface SPI™/QSPI™/ MICROWIRE™/DSP-Compatible On-Board Reference 2.5 V (AD7495 Only) Standby Mode: 1 A Max 8-Lead SOIC and SOIC Packages APPLICATIONS Battery-Powered Systems Personal Digital Assistants Medical Instruments Mobile Communications Instrumentation and Control Systems Data Acquisition Systems High-Speed Modems Optical Sensors 1 MSPS, 12-Bit ADCs AD7475/AD7495 FUNCTIONAL BLOCK DIAGRAMS VDD T/H VIN REF IN 12-BIT SUCCESSIVE APPROXIMATION ADC SCLK CONTROL LOGIC CS VDRIVE AD7475 GND VDD VIN T/H 12-BIT SUCCESSIVE APPROXIMATION ADC REF OUT BUF SCLK 2.5V REFERENCE CONTROL LOGIC The conversion process and data acquisition are controlled using CS and the serial clock allowing the devices to interface with microprocessors or DSPs. The input signal is sampled on the falling edge of CS and conversion is also initiated at this point. There are no pipelined delays associated with the part. The AD7475/AD7495 use advanced design techniques to achieve very low power dissipation at high throughput rates. With 3 V supplies and 1 MSPS throughput rate, the AD7475 consumes just 1.5 mA, while the AD7495 consumes 2 mA. With 5 V supplies and 1 MSPS, the current consumption is 2.1 mA for the AD7475 and 2.6 mA for the AD7495. The analog input range for the part is 0 V to REF IN. The 2.5 V reference for the AD7475 is applied externally to the REF IN pin while the AD7495 has an on-board 2.5 V reference. The conversion time is determined by the SCLK frequency. MICROWIRE is a trademark of National Semiconductor Corporation. SPI and QSPI are trademarks of Motorola, Inc. SDATA CS GENERAL DESCRIPTION The AD7475/AD7495 are 12-bit high-speed, low-power, successive-approximation ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput rates up to 1 MSPS. The parts contain a low-noise, wide bandwidth track/hold amplifier that can handle input frequencies in excess of 1 MHz. SDATA VDRIVE AD7495 GND PRODUCT HIGHLIGHTS 1. High throughput with low power consumption. The AD7475 offers 1 MSPS throughput rates with 4.5 mW power consumption. 2. Single-supply operation with VDRIVE function. The AD7475/ AD7495 operate from a single 2.7 V to 5.25 V supply. The VDRIVE function allows the serial interface to connect directly to either 3 V or 5 V processor systems independent of VDD. 3. Flexible power/serial clock speed management. The conversion rate is determined by the serial clock, allowing the conversion time to be reduced through the serial clock speed increase. The part also features shutdown modes to maximize power efficiency at lower throughput rates. This allows the average power consumption to be reduced while not converting. Power consumption is 1 µA when in full shutdown. 4. No pipeline delay. The part features a standard successiveapproximation ADC with accurate control of the sampling instant via a CS input and once off conversion control. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD7475/AD7495–SPECIFICATIONS1 AD7475–SPECIFICATIONS1 (VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V, fSCLK = 20 MHz unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted.) A Version1 B Version1 Unit Test Conditions/Comments 68 68 dB min fIN = 300 kHz Sine Wave, fSAMPLE = 1 MSPS –75 –76 –75 –76 dB max dB max fIN = 300 kHz Sine Wave, fSAMPLE = 1 MSPS fIN = 300 kHz Sine Wave, fSAMPLE = 1 MSPS –78 –78 10 50 8.3 1.3 –78 –78 10 50 8.3 1.3 dB typ dB typ ns typ ps typ MHz typ MHz typ @ 3 dB @ 0.1 dB Differential Nonlinearity 12 ± 1.5 ± 0.5 +1.5/–0.9 12 ±1 ± 0.5 +1.5/–0.9 Bits LSB max LSB typ LSB max Offset Error Gain Error ± 0.5 ±8 ±3 ± 0.5 ±8 ±3 LSB typ LSB max LSB max Parameter DYNAMIC PERFORMANCE Signal to Noise + Distortion Ratio (SINAD) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD) Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity @ 5 V (typ @ 3 V) @ 25°C @ 5 V Guaranteed No Missed Codes to 12 Bits (typ @ 3 V) @ 25°C Typically ± 2.5 LSB ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance ±1 20 REFERENCE INPUT REF IN Input Voltage Range DC Leakage Current Input Capacitance 2.5 ±1 20 2.5 ±1 20 Volts µA max pF typ LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN2 VDRIVE – 1 0.4 ±1 10 VDRIVE – 1 0.4 ±1 10 V min V max µA max pF max LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Floating-State Leakage Current Floating-State Output Capacitance2 Output Coding VDRIVE – 0.2 0.4 0.4 ± 10 ± 10 10 10 Straight (Natural) Binary V min V max µA max pF max ISOURCE = 200 µA; VDRIVE = 2.7 V to 5.25 V ISINK = 200 µA 800 300 325 1 800 300 325 1 ns max ns max ns max MSPS max 16 SCLK Cycles with SCLK at 20 MHz Sine Wave Input Full-Scale Step Input See Serial Interface Section 2.7/5.25 2.7/5.25 2.7/5.25 2.7/5.25 V min/max V min/max 750 2.1 1.5 450 100 1 750 2.1 1.5 450 100 1 A typ mA max mA max µA typ µA max µA max CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD VDRIVE IDD3 Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode Partial Power-Down Mode Full Power-Down Mode 0 to REF IN ±1 20 Volts µA max pF typ –2– ± 1% for Specified Performance Typically 10 nA, VIN = 0 V or VDRIVE Digital I/Ps = 0 V or VDRIVE VDD = 2.7 V to 5.25 V. SCLK On or Off VDD = 4.75 V to 5.25 V. fSAMPLE = 1 MSPS VDD = 2.7 V to 3.6 V. fSAMPLE = 1 MSPS fSAMPLE = 100 kSPS (Static) SCLK On or Off REV. A AD7475/AD7495 AD7475–SPECIFICATIONS (continued) Parameter POWER REQUIREMENTS (continued) Power Dissipation3 Normal Mode (Operational) Partial Power-Down (Static) Full Power-Down A Version1 B Version1 Unit Test Conditions/Comments 10.5 4.5 500 300 5 3 10.5 4.5 500 300 5 3 mW max mW max W max W max W max W max VDD = 5 V. fSAMPLE = 1 MSPS VDD = 3 V. fSAMPLE = 1 MSPS VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V NOTES 1 Temperature ranges as follows: A, B Versions: –40C to +85C. 2 Sample tested @ 25C to ensure compliance. 3 See Power Versus Throughput Rate section. Specifications subject to change without notice. (VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, fSCLK = 20 MHz unless otherwise noted; TA = TMIN to MAX, unless otherwise noted.) AD7495–SPECIFICATIONS1 T A Version1 B Version1 Unit Test Conditions/Comments 68 68 dB min fIN = 300 kHz Sine Wave, fSAMPLE = 1 MSPS –75 –76 –75 –76 dB max dB max fIN = 300 kHz Sine Wave, fSAMPLE = 1 MSPS fIN = 300 kHz Sine Wave, fSAMPLE = 1 MSPS –78 –78 10 50 8.3 1.3 –78 –78 10 50 8.3 1.3 dB typ dB typ ns typ ps typ MHz typ MHz typ @ 3 dB @ 0.1 dB Differential Nonlinearity 12 ± 1.5 ± 0.5 +1.5/–0.9 12 ±1 ± 0.5 +1.5/–0.9 Bits LSB max LSB typ LSB max Offset Error Gain Error ± 0.6 ±8 ±7 ± 0.6 ±8 ±7 LSB typ LSB max LSB max 0 to 2.5 ±1 20 0 to 2.5 ±1 20 Volts µA max pF typ Parameter DYNAMIC PERFORMANCE Signal to Noise + Distortion (SINAD) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise (SFDR) Intermodulation Distortion (IMD) Second Order Terms Third Order Terms Aperture Delay Aperture Jitter Full Power Bandwidth Full Power Bandwidth DC ACCURACY Resolution Integral Nonlinearity ANALOG INPUT Input Voltage Ranges DC Leakage Current Input Capacitance REFERENCE OUTPUT REF OUT Output Voltage 2.4625/2.5375 2.4625/2.5375 REF OUT Impedance 10 10 REF OUT Temperature Coefficient 50 50 V min/max Ω typ ppm/C typ LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN2 VDRIVE – 1 0.4 ±1 10 V min V max µA max pF max LOGIC OUTPUTS Output High Voltage, VOH VDRIVE – 0.2 Output Low Voltage, VOL 0.4 0.4 Floating-State Leakage Current ± 10 ± 10 10 Floating-State Output Capacitance2 10 Output Coding Straight (Natural) Binary V min V max µA max pF max REV. A VDRIVE – 1 0.4 ±1 10 –3– @ 5 V (typ @ 3 V) @ 25°C @ 5 V Guaranteed No Missed Codes to 12 Bits (typ @ 3 V) @ 25°C Typically ± 2.5 LSB Typically ± 2.5 LSB Typically 10 nA, VIN = 0 V or VDRIVE ISOURCE = 200 µA; VDD = 2.7 V to 5.25 V ISINK = 200 µA AD7475/AD7495–SPECIFICATIONS1 AD7495–SPECIFICATIONS (continued) Parameter CONVERSION RATE Conversion Time Track/Hold Acquisition Time Throughput Rate POWER REQUIREMENTS VDD VDRIVE IDD Normal Mode (Static) Normal Mode (Operational) Partial Power-Down Mode Partial Power-Down Mode Full Power-Down Mode Power Dissipation3 Normal Mode (Operational) Partial Power-Down (Static) Full Power-Down A Version1 B Version1 Unit Test Conditions/Comments 800 300 325 1 800 300 325 1 ns max ns max ns max MSPS max 16 SCLK Cycles with SCLK at 20 MHz Sine Wave Input Full-Scale Step Input See Serial Interface Section 2.7/5.25 2.7/5.25 2.7/5.25 2.7/5.25 V min/max V min/max 1 2.6 2 650 230 1 1 2.6 2 650 230 1 mA typ mA max mA max µA typ µA max µA max Digital I/Ps = 0 V or VDRIVE VDD = 2.7 V to 5.25 V. SCLK On or Off VDD = 4.75 V to 5.25 V. fSAMPLE = 1 MSPS VDD = 2.7 V to 3.6 V. fSAMPLE = 1 MSPS fSAMPLE = 100 kSPS (Static) (Static) SCLK On or Off 13 6 1.15 690 5 3 13 6 1.15 690 5 3 mW max mW max mW max µW max µW max µW max VDD = 5 V. fSAMPLE = 1 MSPS VDD = 3 V. fSAMPLE = 1 MSPS VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V NOTES 1 Temperature ranges as follows: A, B Versions: –40C to +85C. 2 Sample tested @ 25C to ensure compliance. 3 See Power Versus Throughput Rate section. Specifications subject to change without notice. TIMING SPECIFICATIONS1 Parameter fSCLK 2 tCONVERT tQUIET t2 t3 3 t4 3 t5 t6 t7 t8 4 t9 4 tPOWER-UP (VDD = 2.7 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REF IN = 2.5 V (AD7475); TA = TMIN to TMAX, unless otherwise noted.) Limit at TMIN, TMAX AD7475/AD7495 10 20 16 × tSCLK 800 100 10 22 40 0.4 tSCLK 0.4 tSCLK 10 10 45 20 20 650 Unit Description kHz min MHz max tSCLK = 1/fSCLK fSCLK = 20 MHz Minimum Quiet Time Required between Conversions CS to SCLK Setup Time Delay from CS Until SDATA 3-State Disabled Data Access Time after SCLK Falling Edge SCLK Low Pulsewidth SCLK High Pulsewidth SCLK to Data Valid Hold Time SCLK Falling Edge to SDATA High Impedance SCLK Falling Edge to SDATA High Impedance CS Rising Edge to SDATA High Impedance Power-Up Time from Full Power-Down AD7475 Power-Up Time from Full Power-Down AD7495 ns max ns min ns min ns max ns max ns min ns min ns min ns min ns max ns max µs max µs max NOTES 1 Sample tested at 25C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DRIVE) and timed from a voltage level of 1.6 V. 2 Mark/Space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.0 V. 4 t8 and t9 are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times, t 8 and t9, quoted in the timing characteristics are the true bus relinquish time of the part and are independent of the bus loading. Specifications subject to change without notice. –4– REV. A AD7475/AD7495 CS tCONVERT t6 t2 1 SCLK 3 2 B 5 4 13 15 14 t5 t7 t8 t4 t3 0 SDATA THREE-STATE 0 0 0 DB11 DB10 tQUIET DB0 DB1 DB2 16 THREE-STATE FOUR LEADING ZEROS Figure 1. Serial Interface Timing Diagram With t2 = 10 ns min, this leaves tacq to be 664 ns. This 664 ns satisfies the requirement of 300 ns for tACQ. From Figure 2, tACQ is comprised of 2.5(1/fSCLK) + t8 + tQUIET, t8 = 45 ns. This allows a value of 119 ns for tQUIET satisfying the minimum requirement of 100 ns. As in this example and with other slower clock values, the signal may already be acquired before the conversion is complete, but it is still necessary to leave 100 ns minimum tQUIET between conversions. In Example 2 the signal should be fully acquired at approximately Point C in Figure 2. Timing Example 1 Having fSCLK = 20 MHz and a throughput of 1 MSPS gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 1 µs. With t2 = 10 ns min, this leaves tACQ to be 365 ns. This 365 ns satisfies the requirement of 300 ns for tACQ. From Figure 2, tACQ comprises of 2.5(1/fSCLK) + t8 + tQUIET, where t8 = 45 ns. This allows a value of 195 ns for tQUIET, satisfying the minimum requirement of 100 ns. Timing Example 2 Having fSCLK = 5 MHz and a throughput of 315 KSPS, gives a cycle time of t2 + 12.5(1/fSCLK) + tACQ = 3.174 s. CS tCONVERT t6 t2 SCLK 1 2 3 4 B 5 13 C 14 15 t5 16 t8 tQUIET 45ns 12.5 (1/fSCLK) tACQUISITION 10ns 1/THROUGHPUT Figure 2. Serial Interface Timing Example 200A TO OUTPUT PIN IOL 1.6V CL 50pF 200A IOH Figure 3. Load Circuit for Digital Output Timing Specifications REV. A –5– AD7475/AD7495 ABSOLUTE MAXIMUM RATINGS 1 PIN CONFIGURATIONS (TA = 25C unless otherwise noted) AD7475 SOIC/SOIC VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VDRIVE to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Analog Input Voltage to GND . . . . . . . . –0.3 V to VDD + 0.3 V Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V VDRIVE to DVDD . . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V Digital Output Voltage to GND . . . . . . –0.3 V to VDD + 0.3 V REF IN to GND . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Input Current to Any Pin Except Supplies2 . . . . . . . 10 mA Operating Temperature Range Commercial (A, B Version) . . . . . . . . . . . . –40C to +85C Storage Temperature Range . . . . . . . . . . . –65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C SOIC, µSOIC Package, Power Dissipation . . . . . . . . 450 mW JA Thermal Impedance . . . . . . . . . . . . . . 157C/W (SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205.9C/W (µSOIC) JC Thermal Impedance . . . . . . . . . . . . . . . 56C/W (SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43.74C/W (µSOIC) Lead Temperature, Soldering Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kV REF IN 1 8 AD7475 VDD CS TOP VIEW GND 3 (Not to Scale) 6 VDRIVE VIN 2 SCLK 4 7 5 SDATA AD7495 SOIC/SOIC REF OUT 1 8 AD7495 VDD CS TOP VIEW GND 3 (Not to Scale) 6 VDRIVE VIN 2 SCLK 4 7 5 SDATA NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. ORDERING GUIDE Model Range AD7495AR AD7495BR AD7495ARM AD7495BRM AD7475AR AD7475BR AD7475ARM AD7475BRM EVAL-AD7495CB3 EVAL-AD7475CB3 EVAL-CONTROL BRD24 –40C to +85C –40C to +85C –40C to +85C –40C to +85C –40C to +85C –40C to +85C –40C to +85C –40C to +85C Evaluation Board Evaluation Board Controller Board Linearity Error (LSB)1 Package Option2 Branding Information ± 1.5 ±1 ± 1.5 ±1 ± 1.5 ±1 ± 1.5 ±1 SO-8 SO-8 RM-8 RM-8 SO-8 SO-8 RM-8 RM-8 AD7495AR AD7495BR CCA CCB AD7475AR AD7475BR C9A C9B NOTES 1 Linearity Error here refers to Integral Linearity Error. 2 SO = SOIC; RM = µSOIC. 3 This can be used as a standalone evaluation board or in conjunction with the EVAL-BOARD CONTROLLER for evaluation/demonstration purposes. 4 This EVALUATION BOARD CONTROLLER is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7475/AD7495 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –6– WARNING! ESD SENSITIVE DEVICE REV. A AD7475/AD7495 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 REF IN Reference Input for the AD7475. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance. A cap of a least 0.1 F should be placed on the REF IN pin. Reference Output for the AD7495. A minimum 100 nF capacitance is required from this pin to GND. The internal reference can be taken from this pin but buffering is required before it is applied elsewhere in a system. Analog Input. Single-ended analog input channel. The input range is 0 to REF IN. Analog Ground. Ground reference point for all circuitry on the AD7475/AD7495. All analog input signals and any external reference signal should be referred to this GND voltage. Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the AD7475/AD7495’s conversion process. Data Out. Logic Output. The conversion result from the AD7475/AD7495 is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four leading zeros followed by the 12 bits of conversion data which is provided MSB first. Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of the AD7475/AD7495 will operate. Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7475/AD7495 and also frames the serial data transfer. Power Supply Input. The VDD range for the AD7475/AD7495 is from 2.7 V to 5.25 V. REF OUT 2 3 VIN GND 4 SCLK 5 SDATA 6 VDRIVE 7 CS 8 VDD TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition. Differential Nonlinearity Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7475/AD7495, it is defined as: THD(dB ) = 20 log V22 + V32 + V42 + V52 + V62 V1 This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics. Offset Error Peak Harmonic or Spurious Noise This is the deviation of the first code transition (00 . . . 000) to (00 . . . 001) from the ideal, i.e., AGND + 0.5 LSB. This is the deviation of the last code transition (111 . . . 110) to (111 . . . 111) from the ideal (i.e., VREF – 1.5 LSB) after the offset error has been adjusted out. Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak. Track/Hold Acquisition Time Intermodulation Distortion The track/hold amplifier returns into track mode on the 13th SCLK rising edge (see Serial Interface section). The Track/Hold Acquisition Time is the minimum time required for the trackand-hold amplifier to remain in track mode for its output to reach and settle to within 0.5 LSB of the applied input signal, given a step change to the input signal. With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n is equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). Gain Error Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02 N + 1.76) dB The AD7475/AD7495 are tested using the CCIF standard where two input frequencies near the top end of the input bandwidth are used. In this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs. Thus for a 12-bit converter, this is 74 dB. REV. A –7– AD7475/AD7495 AD7475/AD7495 TYPICAL PERFORMANCE CURVES CIRCUIT INFORMATION TPC 1 shows a typical FFT plot for the AD7475 at 1 MHz sample rate and 100 kHz input frequency. The AD7475/AD7495 are fast, micropower, 12-bit, single-supply, A/D converters. The parts can be operated from a 2.7 V to 5.25 V supply. When operated from either a 5 V supply or a 3 V supply, the AD7475/AD7495 are capable of throughput rates of 1 MSPS when provided with a 20 MHz clock. 8192 POINT FFT fSAMPLE = 1MSPS fIN = 100kHz SINAD = 70.46dB THD = –87.7dB SFDR = –89.5dB –15 SINAD – dB –35 The AD7475/AD7495 provide the user with an on-chip track/ hold, A/D converter, and a serial interface housed in either an 8-lead SOIC or µSOIC package, which offers the user considerable space-saving advantages over alternative solutions. The AD7495 also has an on-chip 2.5 V reference. The serial clock input accesses data from the part but also provides the clock source for the successive-approximation A/D converter. The analog input range is 0 V to REF IN for the AD7475 and 0 V to REF OUT for the AD7495. –55 –75 –95 –115 0 50 100 150 200 250 300 350 FREQUENCY – kHz 400 450 The AD7475/AD7495 also feature power-down options to allow power saving between conversions. The power-down feature is implemented across the standard serial interface as described in the Modes of Operation section. 500 TPC 1. AD7475 Dynamic Performance CONVERTER OPERATION TPC 2 shows a typical FFT plot for the AD7495 at 1 MHz sample rate and 100 kHz input frequency. 8192 POINT FFT fSAMPLE = 1MSPS fIN = 100kHz SINAD = 69.95dB THD = –89.2dB SFDR = –91.2dB –15 –35 SINAD – dB The AD7475/AD7495 are 12-bit successive approximation analog-to-digital converters based around a capacitive DAC. The AD7475/AD7495 can convert analog input signals in the range 0 V to 2.5 V. Figures 4 and 5 show simplified schematics of the ADC. The ADC comprises of Control Logic, SAR and a Capacitive DAC, which are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. Figure 4 shows the ADC during its acquisition phase. SW2 is closed and SW1 is in Position A. The comparator is held in a balanced condition and the sampling capacitor acquires the signal on VIN. –55 –75 CAPACITIVE DAC –95 –115 0 50 100 150 200 250 300 350 FREQUENCY – kHz 400 450 500 VIN 4k⍀ A SW1 B CONTROL LOGIC SW2 TPC 2. AD7495 Dynamic Performance COMPARATOR AGND TPC 3 shows the signal-to-(noise + distortion) ratio performance versus input frequency for various supply voltages while sampling at 1 MSPS with an SCLK of 20 MHz. Figure 4. ADC Acquisition Phase When the ADC starts a conversion (see Figure 5), SW2 will open and SW1 will move to position B causing the comparator to become unbalanced. The Control Logic and the Capacitive DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The Control Logic generates the ADC output code. Figure 6 shows the ADC transfer function. 71.0 VDD = VDRIVE = 4.75V 70.5 SINAD – dB VDD = VDRIVE = 3.60V 70.0 VDD = VDRIVE = 2.70V CAPACITIVE DAC 69.5 VDD = VDRIVE = 5.25V 69.0 VIN 4k⍀ A SW1 B CONTROL LOGIC SW2 68.5 10 100 INPUT FREQUENCY – kHz 1000 AGND COMPARATOR Figure 5. ADC Conversion Phase TPC 3. AD7495 SINAD vs. Input Frequency at 1 MSPS –8– REV. A AD7475/AD7495 ADC TRANSFER FUNCTION 5V SUPPLY The output coding of the AD7475/AD7495 is straight binary. The designed code transitions occur midway between successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, etc.). The LSB size is = VREF/4096. The ideal transfer characteristic for the AD7475/ AD7495 is shown in Figure 6 below. 0.1F 10F VDD 0V TO 2.5V INPUT SCLK VIN SDATA AD7475 ADC CODE C/P CS VDRIVE GND 111...111 111...110 REF IN 111...000 0.1F 10F 2.5V AD780 0.1F (MIN) 1LSB = VREF/4096 SERIAL INTERFACE 3V SUPPLY 011...111 Figure 7. AD7475 Typical Connection Diagram 000...010 000...001 000...000 Analog Input 0V 0.5LSB Figure 9 shows an equivalent circuit of the analog input structure of the AD7475/AD7495. The two diodes D1 and D2 provide ESD protection for the analog inputs. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 200 mV. This will cause these diodes to become forward-biased and start conducting current into the substrate. 20 mA is the maximum current these diodes can conduct without causing irreversible damage to the part. The capacitor C1 in Figure 9 is typically about 4 pF and can primarily be attributed to pin capacitance. The resistor R1 is a lumped component made up of the on resistance of a switch. This resistor is typically about 100 Ω. The capacitor C2 is the ADC sampling capacitor and has a capacitance of 16 pF typically. For ac applications, removing high frequency components from the analog input signal is recommended by use of an RC low-pass filter on the relevant analog input pin. In applications where harmonic distortion and signal to noise ratio are critical, the analog input should be driven from a low impedance source. Large source impedances will significantly affect the ac performance of the ADC. This may necessitate the use of an input buffer amplifier. The choice of the op amp will be a function of the particular application. VREF –1.5LSB ANALOG INPUT Figure 6. AD7475/AD7495 Transfer Characteristic TYPICAL CONNECTION DIAGRAM Figure 7 and Figure 8 show a typical connection diagram for the AD7475 and AD7495 respectively. In both setups the GND pin is connected to the analog ground plane of the system. In Figure 7 REF IN is connected to a decoupled 2.5 V supply from a reference source, the AD780, to provide an analog input range of 0 V to 2.5 V. Although the AD7475 is connected to a VDD of 5 V, the serial interface is connected to a 3 V microprocessor. The VDRIVE pin of the AD7475 is connected to the same 3 V supply of the microprocessor to allow a 3 V logic interface, see Digital Inputs Section. In Figure 8, the REF OUT pin of the AD7495 is connected to a buffer and then applied to a level-shifting circuit used on the analog input to allow a bipolar signal to be applied to the AD7495. A minimum 100 nF capacitance is required on the REF OUT pin to GND. The conversion result from both ADCs is output in a 16-bit word with four leading zeros followed by the MSB of the 12-bit result. For applications where power consumption is of concern, the power-down modes should be used between conversions or bursts of several conversions to improve power performance. See Modes of Operation section of the data sheet. VDD D1 VIN C1 4pF C2 16pF R1 D2 CONVERSION PHASE–SWITCH OPEN TRACK PHASE–SWITCH CLOSED Figure 9. Equivalent Analog Input Circuit 0.1F 10F 5V SUPPLY SERIAL INTERFACE V 0V V R 0V TO 2.5V INPUT R 3R VDD SCLK VIN AD7495 R SDATA C/P CS VDRIVE GND REF OUT 0.1F 10F 0.1F (MIN) Figure 8. AD7495 Typical Connection Diagram REV. A –9– 3V SUPPLY AD7475/AD7495 When no amplifier is used to drive the analog input, the source impedance should be limited to low values. The maximum source impedance will depend on the amount of total harmonic distortion (THD) that can be tolerated. The THD will increase as the source impedance increases and performance will degrade. Figure 10 shows a graph of the total harmonic distortion versus source impedance for various analog input frequencies. An external reference source should be used to supply the 2.5 V reference to the AD7475. Errors in the reference source will result in gain errors in the AD7475 transfer function and will add the specified full-scale errors on the part. A capacitor of at least 0.1 µF should be placed on the REF IN pin. Suitable reference sources for the AD7475 include the AD780, the AD680, and the AD1852. –20 –30 fIN = 10kHz –40 THD – dB Care should be taken to ensure VDRIVE does not exceed VDD by more than 0.3 V. (See Absolute Maximum Ratings.) Reference Section –10 fIN = 500kHz –50 fIN = 200kHz –60 –70 fIN = 100kHz –80 –90 allows the ADC to easily interface to both 3 V and 5 V processors. For example, if the AD7475/AD7495 were operated with a VDD of 5 V, and the VDRIVE pin could be powered from a 3 V supply. The AD7475/AD7495 has better dynamic performance with a VDD of 5 V while still being able to interface to 3 V digital parts. 1 10 100 1000 SOURCE IMPEDANCE – Ohms 10000 Figure 10. THD vs. Source Impedance for Various Analog Input Frequencies Figure 11 shows a graph of total harmonic distortion versus analog Input frequency for various supply voltages while sampling at 1 MSPS with an SCLK of 20 MHz. The AD7495 contains an on-chip 2.5 V reference. As shown in Figure 12, the voltage that appears at the REF OUT pin is internally buffered before being applied to the ADC, the output impedance of this buffer is typically 10 Ω. The reference is capable of sourcing up to 2 mA. The REF OUT pin should be decoupled to AGND using a 100 nF or greater capacitor. If the 2.5 V internal reference is to be used to drive another device that is capable of glitching the reference at critical times, then the reference will have to be buffered before driving the device. To ensure optimum performance of the AD7495 it is recommended that the Internal Reference not be over driven. If the use of an external reference is required the AD7475 should be used. V REF OUT 25⍀ –75 VDD = VDRIVE = 5.25V –77 160k⍀ VDD = VDRIVE = 2.70V 40k⍀ –79 THD – dB –81 Figure 12. AD7495 Reference Circuit –83 VDD = VDRIVE = 3.60V –85 –87 VDD = VDRIVE = 4.75V –89 –91 –93 –95 10 100 INPUT FREQUENCY – kHz 1000 Figure 11. THD vs. Analog Input Frequency for Various Supply Voltages Digital Inputs The digital inputs applied to the AD7475/AD7495 are not limited by the maximum ratings which limit the analog inputs. Instead, the digital inputs applied can go to 7 V and are not restricted by the VDD + 0.3 V limit as on the analog inputs. Another advantage of SCLK and CS not being restricted by the VDD + 0.3 V limit is the fact that power supply sequencing issues are avoided. If CS or SCLK are applied before VDD, there is no risk of latch-up as there would be on the analog inputs if a signal greater than 0.3 V were applied prior to VDD. VDRIVE The AD7475/AD7495 also has the VDRIVE feature. VDRIVE controls the voltage at which the serial interface operates. VDRIVE MODES OF OPERATION The mode of operation of the AD7475/AD7495 is selected by controlling the (logic) state of the CS signal during a conversion. There are three possible modes of operation, Normal Mode, Partial Power-Down Mode, and Full Power-Down Mode. The point at which CS is pulled high after the conversion has been initiated will determine which power-down mode, if any, the device will enter. Similarly, if already in a power-down mode, CS can control whether the device will return to Normal operation or remain in power-down. These modes of operation are designed to provide flexible power management options. These options can be chosen to optimize the power dissipation/throughput rate ratio for differing application requirements. Normal Mode This mode is intended for fastest throughput rate performance as the user does not have to worry about any power-up times with the AD7475/AD7495 remaining fully powered all the time. Figure 13 shows the general diagram of the operation of the AD7475/AD7495 in this mode. The conversion is initiated on the falling edge of CS as described in the Serial Interface section. To ensure the part remains fully powered up at all times, CS must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CS. If CS is brought high any time after the 10th SCLK falling edge, but –10– REV. A AD7475/AD7495 CS 1 10 16 SCLK SDATA FOUR LEADING ZEROS + CONVERSION RESULT Figure 13. Normal Mode Operation CS 1 2 10 16 SCLK Figure 14. Entering Partial Power-Down Mode THE PART BEGINS TO POWER UP THE PART IS FULLY POWERED UP CS A1 10 16 16 1 SCLK SDATA INVALID DATA VALID DATA Figure 15. Exiting Partial Power-Down Mode before the 16th SCLK falling edge, the part will remain powered up but the conversion will be terminated and SDATA will go back into three-state. Sixteen serial clock cycles are required to complete the conversion and access the conversion result. CS may idle high until the next conversion or may idle low until sometime prior to the next conversion (effectively idling CS low). Once a data transfer is complete (SDATA has returned to three-state), another conversion can be initiated after the quiet time, tQUIET, has elapsed by bringing CS low again. Partial Power-Down Mode This mode is intended for use in applications where slower throughput rates are required; either the ADC is powered down between each conversion, or a series of conversions may be performed at a high throughput rate and then the ADC is powered down for a relatively long duration between these bursts of several conversions. When the AD7475 is in partial power-down, all analog circuitry is powered down except for the bias current generator; and, in the case of the AD7495, all analog circuitry is powered down except for the on-chip reference and reference buffer. To enter partial power-down, the conversion process must be interrupted by bringing CS high anywhere after the second falling edge of SCLK and before the tenth falling edge of SCLK as shown in Figure 14. Once CS has been brought high in this window of SCLKs, the part will enter partial power-down, and the conversion that was initiated by the falling edge of CS will be terminated, and SDATA will go back into three-state. If CS is brought high before the second SCLK falling edge, the part will remain in Normal Mode and will not power down. This will avoid accidental power-down due to glitches on the CS line. In order to exit this mode of operation and power the AD7475/ AD7495 up again, a dummy conversion is performed. On the REV. A falling edge of CS the device will begin to power up, and will continue to power up as long as CS is held low until after the falling edge of the tenth SCLK. The device will be fully powered up once 16 SCLKs have elapsed, and valid data will result from the next conversion as shown in Figure 15. If CS is brought high before the second falling edge of SCLK, the AD7475/AD7495 will go back into partial power-down again. This avoids accidental power-up due to glitches on the CS line; although the device may begin to power up on the falling edge of CS, it will power down again on the rising edge of CS. If in partial power-down and CS is brought high between the second and tenth falling edges of SCLK, the device will enter full power-down mode. Power-Up Time The power-up time of the AD7475/AD7495 from partial powerdown is typically 1 µs, which means that with any frequency of SCLK up to 20 MHz, one dummy cycle will always be sufficient to allow the device to power up from partial power-down. Once the dummy cycle is complete, the ADC will be fully powered up and the input signal will be acquired properly. The quiet time tQUIET must still be allowed from the point where the bus goes back into three-state after the dummy conversion, to the next falling edge of CS. When running at 1 MSPS throughput rate, the AD7475/AD7495 will power up and acquire a signal within ± 0.5 LSB in one dummy cycle, i.e., 1 µs. When powering up from the power-down mode with a dummy cycle, as in Figure 15, the track-and-hold that was in hold mode while the part was powered down, returns to track mode after the first SCLK edge the part receives after the falling edge of CS. This is shown as Point A in Figure 15. Although at any SCLK frequency one dummy cycle is sufficient to power the device up and acquire VIN, it does not necessarily mean that a full dummy –11– AD7475/AD7495 THE PART ENTERS PARTIAL POWER-DOWN THE PART BEGINS TO POWER UP THE PART ENTERS FULL POWER-DOWN CS 1 2 16 10 1 2 10 16 SCLK SDATA INVALID DATA THREE-STATE THREE-STATE INVALID DATA Figure 16. Entering Full Power-Down Mode THE PART BEGINS TO POWER UP THE PART IS FULLY POWERED UP t POWER-UP CS 1 10 16 16 1 SCLK SDATA INVALID DATA VALID DATA Figure 17. Exiting Full Power-Down Mode cycle of 16 SCLKs must always elapse to power up the device and fully acquire VIN; 1 µs will be sufficient to power the device up and acquire the input signal. If, for example, a 5 MHz SCLK frequency was applied to the ADC, the cycle time would be 3.2 s. In one dummy cycle, 3.2 µs, the part would be powered up and V IN fully acquired. However, after 1 µs with a 5 MHz SCLK, only 5 SCLK cycles would have elapsed. At this stage, the ADC would be fully powered up and the signal acquired. So, in this case the CS can be brought high after the tenth SCLK falling edge and brought low again after a time tQUIET to initiate the conversion. Full Power-Down Mode This mode is intended for use in applications where slower throughput rates are required than that in the partial power-down mode, as power up from a full power-down would not be complete in just one dummy conversion. This mode is more suited to applications where a series of conversions performed at a relatively high throughput rate would be followed by a long period of inactivity and hence power-down. When the AD7475/AD7495 is in full power-down, all analog circuitry is powered down. Full power-down is entered in a way similar to partial power-down, except the timing sequence shown in Figure 14 must be executed twice. The conversion process must be interrupted in a similar fashion by bringing CS high anywhere after the second falling edge of SCLK and before the tenth falling edge of SCLK. The device will enter partial power-down at this point. To reach full power-down, the next conversion cycle must be interrupted in the same way as shown in Figure 16. Once CS has been brought high in this window of SCLKs, then the part will power down completely. NOTE: It is not necessary to complete the 16 SCLKs once CS has been brought high to enter a power-down mode. To exit full power-down, and power the AD7475/AD7495 up again, a dummy conversion is performed as when powering up from partial power-down. On the falling edge of CS the device will begin to power up, and will continue to power up as long as CS is held low until after the falling edge of the tenth SCLK. The power-up time is longer than one dummy conversion cycle however, and this time, tPOWER-UP, must elapse before a conversion can be initiated as shown in Figure 17. (See Timing Specifications.) When power supplies are first applied to the AD7475/AD7495, the ADC may power up in either of the power-down modes or normal mode. Because of this, it is best to allow a dummy cycle to elapse to ensure the part is fully powered up before attempting a valid conversion. Likewise, if it is intended to keep the part in the partial power-down mode immediately after the supplies are applied, then two dummy cycles must be initiated. The first dummy cycle must hold CS low until after the tenth SCLK falling edge, Figure 13; in the second cycle CS must be brought high before the tenth SCLK edge but after the second SCLK falling edge, Figure 14. Alternatively, if it is intended to place the part in full power-down mode when the supplies have been applied, then three dummy cycles must be initiated. The first dummy cycle must hold CS low until after the tenth SCLK edge, Figure 13; the second and third dummy cycle place the part in full power-down, Figure 16. See Modes of Operation section. Once supplies are applied to the AD7475/AD7495, enough time must be allowed, for the AD7475, for the external reference to power up and charge the reference capacitor to its final value. For the AD7495, enough time should be allowed for the internal reference buffer to charge the reference capacitor. Then, to place the AD7475/AD7495 in normal mode, a dummy cycle, 1 µs, should be initiated. If the first valid conversion is then performed directly after the dummy conversion, care must be taken to ensure that adequate acquisition time has been allowed. As mentioned earlier, when powering up from the power-down mode, the part will return to track upon the first SCLK edge applied after the falling edge of CS. However, when the ADC powers up initially after supplies are applied, the track-and-hold will already be in track. This means (assuming one has the facility to monitor the ADC supply current) if the ADC powers up –12– REV. A AD7475/AD7495 in the desired mode of operation, and thus a dummy cycle is not required to change mode, then neither is a dummy cycle required to place the track-and-hold into track. If no current monitoring facility is available, the relevant dummy cycle(s) should be performed to ensure the part is in the required mode. POWER VERSUS THROUGHPUT RATE By using the partial power-down mode on the AD7475/AD7495 when not converting, the average power consumption of the ADC decreases at lower throughput rates. Figure 18 shows how, as the throughput rate is reduced, the part remains in its partial power-down state longer and the average power consumption over time drops accordingly. 100 POWER – mW 10 1 AD7495 3V SCLK = 20MHz AD7475 3V SCLK = 20MHz Full power-down mode is intended for use in applications with slower throughput rates than required for the partial powerdown mode. It is necessary to leave 650 µs for the AD7495 to be fully powered up from full power-down before initiating a conversion. Current consumptions between conversions is typically less than 1 µA. Figure 19 shows a typical graph of current versus throughput for the AD7495 while operating in different modes. At slower throughput rates, e.g., 10 SPS to 1 kSPS, the AD7495 was operated in Full Power-Down mode. As the throughput rate increased, up to 100 kSPS, the AD7495 was operated in Partial Power-Down mode, with the part being powered down between conversions. With throughput rates from 100 kSPS to 1 MSPS, the part operated in Normal mode, remaining fully powered up at all times. AD7495 5V SCLK = 20MHz AD7475 5V SCLK = 20MHz remaining 8 µs where the part is in partial power-down. With a throughput rate of 100 kSPS, the average power dissipated during each conversion cycle is (2/10) (6 mW) + (8/10) (0.69 mW) = 1.752 mW. Figure 18 shows the power versus throughput rate when using the partial power-down mode between conversions with both 5 V and 3 V supplies for both the AD7475 and AD7495. For the AD7475, partial power-down current is lower than that of the AD7495. 0.1 0.01 2.0 VDD = 5V 1.8 0.001 50 100 150 200 250 THROUGHPUT – kSPS 300 1.6 350 1.4 CURRENT – mA 0 Figure 18. AD7495 Power vs. Throughput for Partial Power-Down For example if the AD7495 is operated in a continuous sampling mode with a throughput rate of 100 kSPS and an SCLK of 20 MHz (VDD = 5 V), and the device is placed in partial powerdown mode between conversions, then the power consumption is calculated as follows. The maximum power dissipation during normal operation is 13 mW (VDD = 5 V). If the power-up time from partial power-down is one dummy cycle, i.e., 1 µs, and the remaining conversion time is another cycle, i.e., 1 µs, then the AD7495 can be said to dissipate 13 mW for 2 µs during each conversion cycle. For the remainder of the conversion cycle, 8 µs, the part remains in partial power-down mode. The AD7495 can be said to dissipate 1.15 mW for the remaining 8 µs of the conversion cycle. If the throughput rate is 100 kSPS, the cycle time is 10 µs and the average power dissipated during each cycle is (2/10) (13 mW) + (8/10) (1.15 mW) = 3.52 mW. If VDD = 3 V, SCLK = 20 MHz and the device is again in partial powerdown mode between conversions, the power dissipated during normal operation is 6 mW. The AD7495 can be said to dissipate 6 mW for 2 µs during each conversion cycle and 0.69 mW for the 1.2 1.0 0.8 PARTIAL POWER-DOWN FULL POWER-DOWN 0.4 0.2 0 10 100 1k 10k THROUGHPUT – SPS Figure 20 shows the detailed timing diagram for serial interfacing to the AD7475/AD7495. The serial clock provides the conversion clock and also controls the transfer of information from the AD7475/AD7495 during conversion. CS initiates the data transfer and conversion process. The falling edge of CS puts the track and hold into hold mode, takes the bus out of three-state, and the analog input is sampled at this point. t6 1 3 2 B 5 4 13 t5 t7 0 SDATA THREE-STATE 15 14 0 0 0 DB11 DB10 DB2 16 t8 t4 t3 DB1 tQUIET DB0 THREE-STATE FOUR LEADING ZEROS Figure 20. Serial Interface Timing Diagram REV. A 1M SERIAL INTERFACE tCONVERT SCLK 100k Figure 19. Typical AD7495 Current vs. Throughput CS t2 NORMAL 0.6 –13– AD7475/AD7495 CS tCONVERT t6 t2 3 2 1 SCLK 4 B 5 13 15 t7 0 0 0 DB11 DB10 16 tQUIET t4 t3 0 SDATA THREE-STATE 14 t9 DB2 THREE-STATE FOUR LEADING ZEROS Figure 21. Serial Interface Timing Diagram—Conversion Termination The conversion is also initiated at this point and will require 16 SCLK cycles to complete. Once 13 SCLK falling edges have elapsed, the track and hold will go back into track on the next SCLK rising edge as shown in Figure 20 at Point B. On the 16th SCLK falling edge the SDATA line will go back into threestate. If the rising edge of CS occurs before 16 SCLKs have elapsed, the conversion will be terminated and the SDATA line will go back into three-state, as shown in Figure 21, otherwise SDATA returns to three-state on the 16th SCLK falling edge as shown in Figure 20. The connection diagram is shown in Figure 22. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the TMS320C5x/C54x provide equidistant sampling. The VDRIVE pin of the AD7475/ AD7495 takes the same supply voltage as that of the TMS320C5x/ C54x. This allows the ADC to operate at a higher voltage than the serial interface, i.e., TMS320C5x/C54x, if necessary. AD7475/AD7495* SCLK Sixteen serial clock cycles are required to perform the conversion process and to access data from the AD7475/AD7495. CS going low provides the first leading zero to be read in by the microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges beginning with the 2nd leading zero, thus the first falling clock edge on the serial clock has the second leading zero provided. The final bit in the data transfer is valid on the sixteenth falling edge, having being clocked out on the previous (15th) falling edge. In applications with a slower SCLK, it may be possible to read in data on each SCLK rising edge, although the first leading zero will still have to be read on the first SCLK falling edge after the CS falling edge. Therefore, the first rising edge of SCLK after the CS falling edge would provide the second leading zero and the 15th rising SCLK edge would have DB0 provided. This method may not work with most Micros/DSPs, but could possibly be used with FPGAs and ASICs. MICROPROCESSOR INTERFACING The serial interface on the AD7475/AD7495 allows the parts to be directly connected to a range of many different microprocessors. This section explains how to interface the AD7475/AD7495 with some of the more common microcontroller and DSP serial interface protocols. AD7475/AD7495 to TMS320C5x/C54x The serial interface on the TMS320C5x/C54x uses a continuous serial clock and frame synchronization signals to synchronize the data transfer operations with peripheral devices like the AD7475/ AD7495. The CS input allows easy interfacing between the TMS320C5x/C54x and the AD7475/AD7495 without any glue logic required. The serial port of the TMS320C5x/C54x is set up to operate in burst mode with internal CLKX (Tx serial clock) and FSX (Tx frame sync). The serial port control register (SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1 and TXM = 1. The format bit, FO, may be set to 1 to set the word length to 8 bits, in order to implement the power-down modes on the AD7475/AD7495. TMS320C5x/C54x* CLKX CLKR SDATA CS VDRIVE *ADDITIONAL PINS OMITTED FOR CLARITY DR FBX FSR VDD Figure 22. Interfacing to the TMS320C5x/C54x AD7475/AD7495 to ADSP-21xx The ADSP-21xx family of DSPs are interfaced directly to the AD7475/AD7495 without any glue logic required. The VDRIVE pin of the AD7475/AD7495 takes the same supply voltage as that of the ADSP-21xx. This allows the ADC to operate at a higher voltage than the serial interface, i.e., ADSP-21xx, if necessary. The SPORT control register should be set up as follows: TFSW = RFSW = 1, Alternate Framing INVRFS = INVTFS = 1, Active Low Frame Signal DTYPE = 00, Right Justify Data SLEN = 1111, 16-Bit Data Words ISCLK = 1, Internal Serial Clock TFSR = RFSR = 1, Frame Every Word IRFS = 0, ITFS = 1. To implement the power-down modes SLEN should be set to 1001 to issue an 8-bit SCLK burst. The connection diagram is shown in Figure 23. The ADSP21xx has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in Alternate Framing Mode and the SPORT control register is set up as described. The Frame synchronizations signal generated on the TFS is tied to CS and as with all signal processing applications equidistant sampling is necessary. However, in this example, the timer interrupt is used to control the sampling rate of the ADC and under certain conditions, equidistant sampling may not be achieved. –14– REV. A AD7475/AD7495 SCLK SDATA SCLK DR CS RFS VDRIVE TFS *ADDITIONAL PINS OMITTED FOR CLARITY implement the power-down modes on the AD7475/AD7495 then the word length can be changed to eight bits by setting bits WL1 = 0 and WL0 = 0 in CRA. It should be noted that for signal processing applications, it is imperative that the frame synchronization signal from the DSP56xxx provide equidistant sampling. The VDRIVE pin of the AD7475/AD7495 takes the same supply voltage as that of the DSP56xxx. This allows the ADC to operate at a voltage higher than the serial interface, i.e., DSP56xxx, if necessary. ADSP-21xx* AD7475/AD7495* VDD Figure 23. Interfacing to the ADSP-21xx AD7475/AD7495* SCLK The Timer registers etc., are loaded with a value that will provide an interrupt at the required sample interval. When an interrupt is received, a value is transmitted with TFS/DT (ADC control word). The TFS is used to control the RFS and hence the reading of data. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given, (i.e., AX0 = TX0), the state of the SCLK is checked. The DSP will wait until the SCLK has gone high, low, and high before transmission will start. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data may be transmitted or it may wait until the next clock edge. DSP56xxx* SCLK SDATA SRD CS SC2 VDRIVE *ADDITIONAL PINS OMITTED FOR CLARITY VDD Figure 24. Interfacing to the DSP56xxx AD7475/AD7495 to MC68HC16 The Serial Peripheral Interface (SPI) on the MC68HC16 is configured for Master Mode (MSTR = 1), Clock Polarity Bit (CPOL) = 1 and the Clock Phase Bit (CPHA) = 0. The SPI is configured by writing to the SPI Control Register (SPCR), see 68HC16 user manual. The serial transfer will take place as a 16-bit operation when the SIZE bit in the SPCR register is set to SIZE = 1. To implement the power-down modes with an 8-bit transfer set SIZE = 0. A connection diagram is shown in Figure 25. The VDRIVE pin of the AD7475/AD7495 takes the same supply voltage as that of the MC68HC16. This allows the ADC to operate at a higher voltage than the serial interface, i.e., MC68HC16, if necessary. For example, the ADSP-2111 has a master clock frequency of 16 MHz. If the SCLKDIV register is loaded with the value 3, an SCLK of 2 MHz is obtained, and eight master clock periods will elapse for every 1 SCLK period. If the timer registers are loaded with the value 803, 100.5 SCLKs will occur between interrupts and subsequently between transmit instructions. This situation will result in nonequidistant sampling as the transmit instruction is occurring on a SCLK edge. If the number of SCLKs between interrupts is a whole integer figure of N, equidistant sampling will be implemented by the DSP. AD7475/AD7495 to DSP56xxx The connection diagram in Figure 24 shows how the AD7475/ AD7495 can be connected to the SSI (Synchronous Serial Interface) of the DSP56xxx family of DSPs from Motorola. The SSI is operated in Synchronous Mode (SYN bit in CRB = 1) with internally generated 1-bit clock period frame sync for both Tx and Rx (bits FSL1 = 1 and FSL0 = 0 in CRB). Set the word length to 16 by setting bits WL1 = 1 and WL0 = 0 in CRA. To AD7475/AD7495* MC68HC16* SCLK SCLK/PCM2 SDATA MISO/PMC0 CS SS/PMC3 VDRIVE *ADDITIONAL PINS OMITTED FOR CLARITY VDD Figure 25. Interfacing to the MC68HC16 REV. A –15– AD7475/AD7495 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead SOIC (SO-8) 0.1574 (4.00) 0.1497 (3.80) 8 5 1 4 C01684–2.5–4/01(A) 0.1968 (5.00) 0.1890 (4.80) 0.2440 (6.20) 0.2284 (5.80) PIN 1 0.0196 (0.50) ⴛ 45ⴗ 0.0099 (0.25) 0.0500 (1.27) BSC 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 8ⴗ 0.0098 (0.25) 0ⴗ 0.0075 (0.19) 0.020 (0.51) 0.013 (0.33) SEATING PLANE 0.050 (1.27) 0.016 (0.40) CONTROLLING DIMENSIONS ARE IN MILLIMETERS 8-Lead microSOIC (RM-8) 0.122 (3.10) 0.114 (2.90) 8 5 0.199 (5.05) 0.187 (4.75) 0.122 (3.10) 0.114 (2.90) 1 4 PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) 0.120 (3.05) 0.112 (2.84) 0.043 (1.09) 0.037 (0.94) 0.018 (0.46) SEATING 0.008 (0.20) PLANE 33ⴗ 27ⴗ 0.028 (0.71) 0.016 (0.41) PRINTED IN U.S.A. 0.011 (0.28) 0.003 (0.08) –16– REV. A