Sony CXD2588R Cd digital signal processor with built-in digital servo and dac Datasheet

CXD2588Q/R
CD Digital Signal Processor with Built-in Digital Servo and DAC
For the availability of this product, please contact the sales office.
Description
The CXD2588Q/R is a digital signal processor LSI
for CD players. This LSI incorporates a digital servo,
digital filter, zero detection circuit, 1-bit DAC and
analog low-pass filter on a single chip.
Features
Digital Signal Processor (DSP) Block
• Playback mode which supports CAV (Constant
Angular Velocity)
• Frame jitter free
• 0.5× to 4× continuous playback possible
• Allows relative rotational velocity readout
• Supports spindle external control
• Wide capture range playback mode
• Spindle rotational velocity following method
• Supports normal-speed, 4× speed playback
• 16K RAM
• EFM data demodulation
• Enhanced EFM frame sync signal protection
• SEC strategy-based error correction
• Subcode demodulation and Sub Q data error
detection
• Digital spindle servo
• 16-bit traverse counter
• Asymmetry compensation circuit
• CPU interface on serial bus
• Error correction monitor signal, etc. output from a
new CPU interface
• Servo auto sequencer
• Digital audio interface outputs
• Digital level meter, peak meter
• CD TEXT data demodulation
CXD2588Q
100 pin QFP (Plastic)
Applications
CD players
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
–0.3 to +7.0
V
• Supply voltage
VDD
• Input voltage
VI
–0.3 to +7.0
V
(VSS – 0.3V to VDD + 0.3)
• Output voltage
VO
–0.3 to +7.0
V
• Storage temperature Tstg
–40 to +125 °C
• Supply voltage difference
VSS – AVSS –0.3 to +0.3
V
VDD – AVDD –0.3 to +0.3
V
Recommended Operating Conditions
• Supply voltage
VDDNote)
+2.7 to +5.5
V
• Operating temperature Topr
–20 to +75 °C
Note) The VDD for the CXD2588Q/R varies according
to the playback speed selection.
Digital Servo (DSSP) Block
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal
• Auto gain control function for servo loop
• E:F balance, focus bias adjustment functions
• Surf jump function supporting micro two-axis
Digital Filter, DAC and Analog Low-Pass Filter Blocks
• DBB (digital bass boost) function
• Double-speed playback supported
• Digital de-emphasis
• Digital attenuation
• Zero detection function
• 8Fs oversampling digital filter
• S/N: 100dB or more (master clock: 384Fs, typ.)
• Logical value: 109dB
• THD + N: 0.007% or less (master clock: 384Fs, typ.)
• Rejection band attenuation: –60dB or less
CXD2588R
100 pin LQFP (Plastic)
VDD [V]
Playback
speed
CD-DSP block
4×
4.75 to 5.25
1×
3.0 to 5.5
4.5 to 5.5
1×
2.7 to 5.5
2.7 to 5.5
I/O Capacitance
• Input pin
• Output pin
• I/O pin
CI
CO
CI/O
DAC block
11 (Max.)
11 (Max.)
11 (Max.)
pF
pF
pF
Note) Measurement conditions VDD = VI = 0V
fM = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97519-PS
CXD2588Q/R
SYSM
BCKI
PCMDI
LRCKI
EMPHI
BCK
PCMD
LRCK
WDCK
C2PO
WFCK
EMPH
GFS
VCTL
XUGF
V16M
VCKI
XTSL
VPCO
Block Diagram
DAC Block
FSTO
C4M
Error
Corrector
EFM
demodurator
XRST
D/A
Interface
RMUT
Serial-In
Interface
LMUT
ASYI
BIAS
Asymmetry
Corrector
Over Sampling
Digital Filter
16K
RAM
XPCK
FILO
FILI
TES1
TEST
Clock
OSC
Generator
RFAC
ASYO
TES2
XTAI
XTAO
3rd-Order
Noise Shaper
Sub Code
Processor
Digital
PLL
Timing
Logic
Digital
OUT
PWM
PWM
PCO
CLTV
MDP
PWMI
Digital
CLV
LOCK
SENS
DATA
AOUT1
XLAT
CLOK
AIN1
CPU
Interface
Servo
Auto
Sequencer
SPOA
SPOB
LOUT1
AOUT2
AIN2
XLON
LOUT2
SCOR
DOUT
SBSO
SCLK
EXCK
COUT
SQSO
SERVO
Interface
SQCK
FSTI
SSTP
Signal Processor
Block
ATSK
Servo Block
MIRR
MIRR
DFCT
FOK
RFDC
DFCT
FOK
CE
SERVO DSP
TE
SE
OPAmp
Analog SW
A/D
Converter
FE
VC
PWM GENERATOR
FOCUS PWM
GENERATOR
FFDR
FOCUS SERVO
TRACKING
SERVO
TRACKING PWM
GENERATOR
TFDR
SLED SERVO
SLED PWM
GENERATOR
SFDR
ADIO
IGEN
–2–
FRDR
TRDR
SRDR
CXD2588Q/R
SE
NC
TE
CE
RFDC
ADIO
AVSS0
AVDD0
IGEN
ASYO
ASYI
BIAS
RFAC
AVSS3
CLTV
FILO
FILI
PCO
AVDD3
VCTL
VCKI
V16M
VPCO
VSS
TES2
VDD
DOUT
LRCK
LRCKI
PCMD
Pin Configuration (CXD2588Q)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PCMDI 81
50
FE
BCK 82
49
VC
BCKI 83
48
XTSL
EMPH 84
47
TES1
EMPHI 85
46
TEST
XVDD 86
45
VSS
XTAI 87
44
VSS
XTAO 88
43 FRDR
XVSS 89
42
AVDD1 90
FFDR
41 TRDR
AOUT1 91
40
TFDR
AIN1 92
39 SRDR
LOUT1 93
38 SFDR
AVSS1 94
37 FSTI
AVSS2 95
36 FSTO
LOUT2 96
35
SSTP
34 MDP
AIN2 97
AOUT2 98
33 LOCK
MIRR
COUT
C4M
WDCK
SCOR
GFS
C2PO
DATA
XPCK
SYSM
XUGF
XRST
WFCK
EXCK
XLON
SBSO
SPOB
SQCK
–3–
SPOA
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
ATSK
8
VDD
7
VDD
6
PWMI
5
SCLK
4
SENS
3
CLOK
2
XLAT
1
SQSO
31 DFCT
NC
32 FOK
RMUT 100
LMUT
AVDD2 99
CXD2588Q/R
TE
CE
RFDC
ADIO
AVSS0
IGEN
AVDD0
ASYO
ASYI
BIAS
RFAC
AVSS3
CLTV
FILO
FILI
PCO
AVDD3
VCTL
VCKI
V16M
VPCO
VSS
TES2
VDD
DOUT
Pin Configuration (CXD2588R)
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
LRCK 76
50
NC
LRCKI 77
49
SE
PCMD 78
48
FE
PCMDI 79
47
VC
BCK 80
46
XTSL
BCKI 81
45
TES1
EMPH 82
44
TEST
EMPHI 83
43
VSS
XVDD 84
42
VSS
XTAI 85
41
FRDR
XTAO 86
40
FFDR
XVSS 87
39
TRDR
AVDD1 88
38
TFDR
AOUT1 89
37
SRDR
AIN1 90
36
SFDR
LOUT1 91
35
FSTI
AVSS1 92
34
FSTO
AVSS2 93
33
SSTP
LOUT2 94
32
MDP
31 LOCK
AIN2 95
26
WDCK
–4–
C4M
SCOR
GFS
C2PO
XPCK
XUGF
XLON
WFCK
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
SPOB
8
SPOA
7
VDD
6
ATSK
5
VDD
4
PWMI
3
SCLK
2
SENS
1
XLAT
COUT
NC 100
CLOK
LMUT 99
DATA
MIRR
27
SYSM
28
XRST
DFCT
RMUT 98
EXCK
AVDD2 97
SBSO
FOK
29
SQCK
30
SQSO
AOUT2 96
CXD2588Q/R
Pin Description
Pin No.
CXD CXD
2588R 2588Q
Symbol
I/O
Output
values
1, 0
Description
Sub Q 80-bit, PCM peak and level data outputs. CD TEXT data
output.
1
3
SQSO
O
2
4
SQCK
I
3
5
SBSO
O
4
6
EXCK
I
SBSO readout clock input.
5
7
XRST
I
System reset. Reset when low.
6
8
SYSM
I
Mute input. Muted when high.
7
9
DATA
I
Serial data input from CPU.
8
10
XLAT
I
Latch input from CPU. Serial data is latched at the falling edge.
9
11
CLOK
I
Serial data transfer clock input from CPU.
10
12
SENS
O
11
13
SCLK
I
SENS serial data readout clock input.
12
14
PWMI
I
Spindle motor external control input.
13
15
VDD
—
—
Digital power supply.
14
16
VDD
—
—
Digital power supply.
15
17
ATSK
I/O
1, 0
16
18
SPOA
I
Microcomputer extension interface (input A)
17
19
SPOB
I
Microcomputer extension interface (input B)
18
20
XLON
O
1, 0
Microcomputer extension interface (output)
19
21
WFCK
O
1, 0
WFCK output.
20
22
XUGF
O
1, 0
XUGF output. MINT1 or RFCK is output by switching with the command.
21
23
XPCK
O
1, 0
XPCK output. MNT0 is output by switching with the command.
22
24
GFS
O
1, 0
GFS output. MNT3 or XROF is output by switching with the command.
23
25
C2PO
O
1, 0
C2PO output. GTOP is output by switching with the command.
24
26
SCOR
O
1, 0
Outputs a high signal when either subcode sync S0 or S1 is detected.
25
27
C4M
O
1, 0
4.2336MHz output. In CAV-W mode, 1/4 frequency division output for VCKI.
26
28
WDCK
O
1, 0
Word clock output. f = 2Fs.
27
29
COUT
I/O
1, 0
Track count signal input/output.
28
30
MIRR
I/O
1, 0
Mirror signal input/output.
29
31
DFCT
I/O
1, 0
Defect signal input/output.
30
32
FOK
I/O
1, 0
Focus OK signal input/output.
31
33
LOCK
I/O
1, 0
GFS is sampled at 460Hz; when GFS is high, this pin outputs a
high signal. If GFS is low eight consecutive samples, this pin
outputs low. Or input when LKIN = 1.
32
34
MDP
O
1, Z, 0
33
35
SSTP
I
34
36
FSTO
O
SQSO readout clock input.
1, 0
1, 0
Sub Q P to W serial output.
SENS output to CPU.
Anti-shock input/output.
Spindle motor servo control output.
Disc innermost track detection signal input.
1, 0
2/3 frequency division output for XTAI pin.
–5–
CXD2588Q/R
Pin No.
CXD CXD
2588R 2588Q
Symbol
I/O
Output
values
Description
35
37
FSTI
I
36
38
SFDR
O
1, 0
Sled drive output.
37
39
SRDR
O
1, 0
Sled drive output.
38
40
TFDR
O
1, 0
Tracking drive output.
39
41
TRDR
O
1, 0
Tracking drive output.
40
42
FFDR
O
1, 0
Focus drive output.
41
43
FRDR
O
1, 0
Focus drive output.
42
44
VSS
—
—
Digital GND.
43
45
VSS
—
—
Digital GND.
44
46
TEST
I
Test pin. Normally, GND.
45
47
TES1
I
Test pin. Normally, GND.
46
48
XTSL
I
Crystal selection input. Low when the crystal is 16.9344MHz; high
when the crystal is 33.8688MHz.
47
49
VC
I
Center voltage input.
48
50
FE
I
Focus error signal input.
49
51
SE
I
Sled error signal input.
50
52
NC
51
53
TE
I
Tracking error signal input.
52
54
CE
I
Center servo analog input.
53
55
RFDC
I
RF signal input.
54
56
ADIO
O
Analog
55
57
AVSS0
—
—
56
58
IGEN
I
57
59
AVDD0
—
—
58
60
ASYO
O
1, 0
59
61
ASYI
I
Asymmetry comparator voltage input.
60
62
BIAS
I
Asymmetry circuit constant current input.
61
63
RFAC
I
EFM signal input.
62
64
AVSS3
—
63
65
CLTV
I
64
66
FILO
O
65
67
FILI
I
66
68
PCO
O
1, Z, 0
67
69
AVDD3
—
—
68
70
VCTL
I
Wide-band EFM PLL VCO2 control voltage input.
69
71
VCKI
I
Wide-band EFM PLL VCO2 oscillation input.
2/3 frequency division input for XTAI pin.
Test pin. No connected.
Analog GND.
Operational amplifier constant current input.
—
Analog power supply.
EFM full-swing output. (low = Vss, high = VDD)
Analog GND.
Multiplier VCO1 control voltage input.
Analog
Master PLL filter output. (slave = digital PLL)
Master PLL filter input.
Master PLL charge pump output.
Analog power supply.
–6–
CXD2588Q/R
Pin No.
CXD CXD
2588R 2588Q
Symbol
I/O
Output
values
Description
70
72
V16M
O
1, 0
71
73
VPCO
O
1, Z, 0
72
74
VSS
—
—
73
75
TES2
74
76
VDD
—
—
75
77
DOUT
O
1, 0
Digital Out output.
76
78
LRCK
O
1, 0
D/A interface. LR clock output f = Fs.
77
79
KRCKI
I
78
80
PCMD
O
79
81
PCMDI
I
80
82
BCK
O
81
83
BCKI
I
82
84
EMPH
O
83
85
EMPHI
I
84
86
XVDD
—
85
87
XTAI
I
Crystal oscillation circuit input. Master clock is externally input from
this pin.
86
88
XTAO
O
Crystal oscillation circuit output.
87
89
XVSS
—
—
Master clock GND.
88
90
AVDD1
—
—
Analog power supply.
89
91
AOUT1
O
L ch analog output.
90
92
AIN1
I
L ch operational amplifier input.
91
93
LOUT1
O
L ch LINE output.
92
94
AVSS1
—
—
Analog GND.
93
95
AVSS2
—
—
Analog GND.
94
96
LOUT2
O
R ch LINE output.
95
97
AIN2
I
R ch operational amplifier output.
96
98
AOUT2
O
R ch analog output.
97
99
AVDD2
—
—
98
100
RMUT
O
1, 0
R ch zero detection flag.
99
1
LMUT
O
1, 0
L ch zero detection flag.
100
2
NC
I
Wide-band EFM PLL VCO2 oscillation output.
Wide-band EFM PLL charge pump output.
Digital GND.
Test pin. Normally GND.
Digital power supply.
D/A interface. LR clock input.
1, 0
D/A interface. Serial data output.
(two's complement, MSB first)
D/A interface. Serial data input.
(two's complement, MSB first)
1, 0
D/A interface. Bit clock output.
D/A interface. Bit clock input.
1, 0
Outputs a high signal when the playback disc has emphasis, and a
low signal when there is no emphasis.
Inputs a high signal when de-emphasis is on, and a low signal when
de-emphasis is off.
—
Master clock power supply.
Analog power supply.
–7–
CXD2588Q/R
Notes) • PCMD is a MSB first, two's complement output.
• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before
sync protection.
• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.
• C2PO represents the data error status.
• XROF is generated when the 16K RAM exceeds the ±4F jitter margin.
Monitor Pin Output Combinations
Command bit
Output data
MTSL1
MTSL0
0
0
XUGF
XPCK
GFS
C2PO
0
1
MNT1
MNT0
MNT3
C2PO
1
0
RFCK
XPCK
XROF
GTOP
–8–
CXD2588Q/R
Electrical Characteristics
1. DC Characteristics
(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Conditions
Input
voltage (1)
High level input voltage VIH (1)
Input
voltage (2)
High level input voltage VIH (2)
Input
voltage (3)
High level input voltage VIH (3)
Low level input voltage
Low level input voltage
Min.
Low level input voltage
VIL (3)
Input voltage
VIN (4)
Max.
0.7VDD
VIL (1)
VIL (2)
Typ.
V
0.3VDD
Schmitt input
Unit
0.8VDD
V
V
0.2VDD
0.8VDD
V
V
0.2VDD
V
Vss
VDD
V
High level output voltage VOH (1) IOH = –2mA
Output
Avoltage (1) Low level output voltage VOL (1) IOL = 4mA
VDD – 0.8
VDD
V
Vss
0.4
V
High level output voltage VOH (2) IOH = –4mA
Output
Avoltage (2) Low level output voltage VOL (2) IOL = 8mA
VDD – 0.8
VDD
V
Vss
0.4
V
High level output voltage VOH (3) IOH = –6mA
Output
Avoltage (3) Low level output voltage VOL (3) IOL = 4mA
VDD – 0.8
VDD
V
Vss
0.4
V
VDD
V
0.4
V
Input
voltage (4)
Analog input
High level output voltage VOH (4) IOH = –0.28mA VDD – 0.5
Output
Avoltage (4) Low level output voltage VOL (4) IOL = 0.36mA
Vss
Applicable
pins
∗1, ∗11
∗2, ∗12
∗3
∗4, ∗9, ∗10
∗5
∗6
∗7
∗8
Input leak current (1)
ILI (1)
VIN = VSS
or VDD
–10
10
µA
∗1, ∗2
Input leak current (2)
ILI (2)
VIN = VSS
or VDD
–40
40
µA
∗11, ∗12
Input leak current (3)
ILI (3)
VI = 1.5 to 3.5V
–20
20
µA
∗9
Input leak current (4)
ILI (4)
VI = 0 to 5.0V
–40
600
µA
∗10
Applicable pins
∗1 SYSM, DATA, XLAT, PWMI, SSTP, FSTI, XTSL, TEST, TES1, VCKI, TES2
∗2 SQCK, XRST, CLOK
∗3 LRCKI, PCMDI, BCKI, EMPHI
∗4 ASYI, RFAC, CLTV, FILI, VCTL
∗5 SQSO, SBSO, SENS, ATSK, XLON, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, C4M, WDCK, COUT,
MIRR, DFCT, FOK, LOCK, FSTO, SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, ASYO, DOUT, LRCK,
PCMD, BCK, EMPH, RMUT, LMUT
∗6 V16M
∗7 MDP, PCO, VPCO
∗8 FILO
∗9 VC, FE, SE, TE, CE
∗10 RFDC
∗11 EXCK, ATSK, COUT, MIRR, DFCT, FOK, LOCK
∗12 SCLK, SPOA, SPOB
–9–
CXD2588Q/R
2. AC Characteristics
(1) XTAI pin
(a) When using self-excited oscillation
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item
Oscillation
frequency
Symbol
Min.
Typ.
7
fMAX
Max.
Unit
34
MHz
(b) When inputting pulses to XTAI pin
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item
Symbol
Min.
Typ.
Max.
Unit
High level pulse
width
tWHX
13
500
ns
Low level pulse
width
tWLX
13
500
ns
Pulse cycle
tCK
26
1,000
ns
Input high level
VIHX
VDD – 1.0
Input low level
VILX
0.8
V
Rise time, fall
time
tR, tF
10
ns
V
tCX
tWLX
tWHX
VIHX
VIHX × 0.9
VDD/2
XTAI
VIHX × 0.1
VILX
tR
tF
(c) When inputting sine waves to XTAI pin via a capacitor
(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item
Input amplitude
Symbol
Min.
VI
2.0
Typ.
Max.
Unit
VDD + 0.3 Vp-p
– 10 –
CXD2588Q/R
(2) CLOK, DATA, XLAT, COUT, SQCK, and EXCK pins
(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Clock frequency
fCK
Clock pulse width
Latch pulse width
tWCK
tSU
tH
tD
tWL
EXCK, SQCK frequency
fT
Setup time
Hold time
Delay time
Min.
Symbol
Typ.
Max.
Unit
0.65
MHz
750
ns
300
ns
300
ns
300
ns
750
ns
0.65Note)
MHz
750Note)
EXCK, SQCK pulse width fWT
ns
1/fCK
tWCK
tWCK
CLOK
DATA
XLAT
tSU
tH
tD
tWL
EXCK
SQCK
tWT
tWT
1/fT
SBSO
SQSO
tSU
tH
Note) In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCK maximum
operating frequency is 300kHz and its minimum pulse width is 1.5µs.
(3) BCKI, LRCKI and PCMDI pins (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol Conditions
BCK pulse width
tW
tSU
tH
tSU
DATAL, R setup time
DATAL, R hold time
LRCK setup time
Min.
Typ.
Unit
94
ns
18
ns
18
ns
18
ns
tW(BCKI) tW(BCKI)
BCKI
Max.
VDD/2
VDD/2
tSU
tH
(PCMDI) (PCMDI)
PCMDI
tSU
(LRCKI)
LRCKI
– 11 –
CXD2588Q/R
(4) SCLK pin
XLAT
tDLS
tSPW
SCLK
•••
1/fSCLK
Serial Read Out Data
(SENS)
Item
MSB
Symbol
SCLK frequency
fSCLK
SCLK pulse width
tSPW
tDLS
Delay time
Min.
Typ.
•••
Max.
Unit
16
MHz
31.3
ns
15
µs
LSB
(5) COUT, MIRR and DFCT pins
Operating frequency (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol
Min.
Typ.
Max.
Unit
Conditions
COUT maximum
operating frequency
fCOUT
40
kHz
∗1
MIRR maximum
operating frequency
fMIRR
40
kHz
∗2
DFCT maximum
operating frequency
fDFCTH
5
kHz
∗3
∗1 When using a high-speed traverse TZC
∗2
B
A
When the RF signal continuously satisfies the following conditions during the above traverse.
• A = 0.12VDD to 0.26VDD
•
B
= 25%
A+B
∗3 During complete RF signal omission
When settings related to DFCT signal generation are Typ.
– 12 –
CXD2588Q/R
1-bit DAC and LPF Block Analog Characteristics
Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C)
Item
Symbol
Total harmonic
distortion
THD
Signal-to-noise
ratio
S/N
Typ.
Max.
384Fs
0.0050
0.0070
768Fs
0.0045
0.0065
Min.
Crystal
Conditions
1kHz, 0dB data
1kHz, 0dB data
(Using A-weighting filter)
384Fs
96
100
768Fs
96
100
Fs = 44.1kHz in all cases.
The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.
12k
AOUT1 (2)
680p
12k
12k
SHIBASOKU (AM51A)
AIN1 (2)
150p
LOUT1 (2)
Audio Analyzer
22µ
100k
LPF external circuit diagram
768Fs/384Fs
DATA
TEST DISC
Rch
A
Lch
B
RF
CXD2588Q/R
Audio Analyzer
Block diagram of analog characteristics measurement
– 13 –
Unit
%
dB
CXD2588Q/R
(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item
Symbol
Output voltage
VOUT
Load resistance
RL
Min.
Typ.
1.12
8
Max.
Unit
Applicable pins
Vrms
∗1
kΩ
∗1
∗ Measurement is conducted for the LPF external circuit diagram with the sine wave output of 1kHz and 0dB.
Applicable pins
∗1 LOUT1, LOUT2
– 14 –
CXD2588Q/R
Contents
§1. CPU Interface
§1-1. CPU Interface Timing ........................................................................................................................ 16
§1-2. CPU Interface Command Table ........................................................................................................ 16
§1-3. CPU Command Presets .................................................................................................................... 26
§1-4. Description of SENS Signals and Commands ................................................................................... 31
§2. Subcode Interface
§2-1. P to W Subcode Readout .................................................................................................................. 51
§2-2. 80-bit Sub Q Readout ........................................................................................................................ 51
§3. Description of Modes
§3-1. CLV-N Mode ...................................................................................................................................... 56
§3-2. CLV-W Mode ..................................................................................................................................... 56
§3-3. CAV-W Mode ..................................................................................................................................... 56
§4. Description of Other Functions
§4-1. Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 58
§4-2. Frame Sync Protection ...................................................................................................................... 60
§4-3. Error Correction ................................................................................................................................. 60
§4-4. DA Interface ....................................................................................................................................... 61
§4-5. Digital Out .......................................................................................................................................... 63
§4-6. Servo Auto Sequence ....................................................................................................................... 63
§4-7. Digital CLV ......................................................................................................................................... 70
§4-8. CD-DSP Block Playback Speed ........................................................................................................ 71
§4-9. DAC Block Playback Speed .............................................................................................................. 71
§4-10. DAC Block Input Timing .................................................................................................................... 72
§4-11. Description of DAC Block Functions .................................................................................................. 72
§4-12. LPF Block .......................................................................................................................................... 76
§4-13. Asymmetry Compensation ................................................................................................................ 77
§4-14. CD Text Data Demodulation .............................................................................................................. 78
§5. Description of Servo Signal Processing System Functions and Commands
§5-1. General Description of Servo Signal Processing System .................................................................. 80
§5-2. Digital Servo Block Master Clock (MCK) ........................................................................................... 81
§5-3. AVRG Measurement and Compensation .......................................................................................... 81
§5-4. E:F Balance Adjustment Function ..................................................................................................... 83
§5-5. FCS Bias Adjustment Function .......................................................................................................... 83
§5-6. AGCNTL Function ............................................................................................................................. 85
§5-7. FCS Servo and FCS Search ............................................................................................................. 87
§5-8. TRK and SLD Servo Control ............................................................................................................. 88
§5-9. MIRR and DFCT Signal Generation .................................................................................................. 89
§5-10. DFCT Countermeasure Circuit .......................................................................................................... 90
§5-11. Anti-Shock Circuit .............................................................................................................................. 90
§5-12. Brake Circuit ...................................................................................................................................... 91
§5-13. COUT Signal ..................................................................................................................................... 92
§5-14. Serial Readout Circuit ........................................................................................................................ 92
§5-15. Writing to the Coefficient RAM .......................................................................................................... 93
§5-16. PWM Output ...................................................................................................................................... 93
§5-17. Servo Status Changes Produced by the LOCK Signal ..................................................................... 95
§5-18. Description of Commands and Data Sets ......................................................................................... 95
§5-19. List of Servo Filter Coefficients ........................................................................................................ 110
§5-20. Filter Composition ............................................................................................................................ 112
§5-21. TRACKING and FOCUS Frequency Response .............................................................................. 119
§6. Application Circuit .................................................................................................................................. 120
Explanation of abbreviations
AVRG:
AGCNTL:
FCS:
TRK:
SLD:
DFCT:
Average
Auto gain control
Focus
Tracking
Sled
Defect
– 15 –
CXD2588Q/R
§1. CPU Interface
§1-1. CPU Interface Timing
• CPU interface
This interface uses DATA, CLOK and XLAT to set the modes.
The interface timing chart is shown below.
750ns or more
CLOK
DATA
D0
D1
D18
D19
D20
D21
D22
D23
750ns or more
XLAT
Valid
Registers
• The internal registers are initialized by a reset when XRST = 0.
Note) Be sure to set SQCK to high when XLAT is low.
§1-2. CPU Interface Command Table
Total bit length for each register
Register
0 to 2
3
Total bit length
8 bits
8 to 24 bits
4 to 6
8 bits
7
20 bits
8
28 bits
9
24 bits
A
28 bits
B
16 bits
C
8 bits
D
16 bits
E
20 bits
– 16 –
0
TRACKING
CONTROL
FOCUS
CONTROL
1
Command
Register
0001
0000
– 17 –
—
—
—
—
—
—
—
0
—
—
1
—
0
—
—
0
—
—
0
0
—
0
0
1
1
1
0
D18
—
—
1
0
—
—
—
—
1
1
1
0
—
—
D17
Data 1
1
D23 to D20 D19
Address
Command Table ($0X to 1X)
0
1
—
—
—
—
—
—
1
0
—
—
—
—
D16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D15
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D14
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D13
Data 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D12
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D11
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D9
Data 3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D5
Data 4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D1
Data 5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D0
—: Don’t care
TRACKING GAIN UP
FILTER SELECT 2
TRACKING GAIN UP
FILTER SELECT 1
TRACKING GAIN UP
TRACKING GAIN
NORMAL
BRAKE OFF
BRAKE ON
ANTI SHOCK OFF
ANTI SHOCK ON
FOCUS SEACH
VOLTAGE UP
FOCUS SEARCH
VOLTAGE DOWN
FOCUS SERVO OFF,
FOCUS SEARCH
VOLTAGE OUT
FOCUS SERVO OFF,
0V OUT
FOCUS SERVO ON
(FOCUS GAIN
DOWN)
FOCUS SERVO ON
(FOCUS GAIN
NORMAL)
CXD2588Q/R
– 18 –
3
SELECT
Command
TRACKING
MODE
2
Register
Command
Register
0011
0
0
0
0
0
0
0
D18
0
D23 to D20 D19
—
—
—
—
—
—
1
1
—
0
1
—
1
0
Address
0010
0
D18
1
0
1
0
—
—
—
—
D16
1
1
0
0
D17
1
0
1
0
D16
Data 1
1
1
0
0
—
—
—
—
D17
Data 1
0
D23 to D20 D19
Address
Command Table ($2X to 3X)
—
—
—
—
D15
—
—
—
—
—
—
—
—
D15
—
—
—
—
—
—
—
—
D13
—
—
—
—
D14
—
—
—
—
D13
Data 2
—
—
—
—
—
—
—
—
D14
Data 2
—
—
—
—
D12
—
—
—
—
—
—
—
—
D12
—
—
—
—
D11
—
—
—
—
—
—
—
—
D11
—
—
—
—
—
—
—
—
D9
—
—
—
—
D10
—
—
—
—
D9
Data 3
—
—
—
—
—
—
—
—
D10
Data 3
—
—
—
—
D8
—
—
—
—
—
—
—
—
D8
—
—
—
—
D7
—
—
—
—
—
—
—
—
D7
—
—
—
—
—
—
—
—
D5
—
—
—
—
D6
—
—
—
—
D5
Data 4
—
—
—
—
—
—
—
—
D6
Data 4
—
—
—
—
D4
—
—
—
—
—
—
—
—
D4
—
—
—
—
D3
—
—
—
—
—
—
—
—
D3
—
—
—
—
—
—
—
—
D1
—
—
—
—
D2
—
—
—
—
D1
Data 5
—
—
—
—
—
—
—
—
D2
Data 5
—
—
—
—
D0
—
—
—
—
—
—
—
—
D0
—: Don’t care
SLED KICK LEVEL
(±4 × basic value)
SLED KICK LEVEL
(±3 × basic value)
SLED KICK LEVEL
(±2 × basic value)
SLED KICK LEVEL
(±1 × basic value) (Default)
REVERSE SLED MOVE
FORWARD SLED MOVE
SLED SERVO ON
SLED SERVO OFF
REVERSE TRACK JUMP
FORWARD TRACK JUMP
TRACKING SERVO ON
TRACKING SERVO OFF
CXD2588Q/R
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0000
0
0
1
1
1
0
0
0
0
0
– 19 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($340X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K0F)
FOCUS DEFECT HOLD GAIN
KRAM DATA (K0E)
FOCUS PHASE COMPENSATE FILTER A
KRAM DATA (K0D)
FOCUS LOW BOOST FILTER B-L
KRAM DATA (K0C)
FOCUS LOW BOOST FILTER B-H
KRAM DATA (K0B)
FOCUS LOW BOOST FILTER A-L
KRAM DATA (K0A)
FOCUS LOW BOOST FILTER A-H
KRAM DATA (K09)
FOCUS HIGH CUT FILTER B
KRAM DATA (K08)
FOCUS HIGH CUT FILTER A
KRAM DATA (K07)
SLED AUTO GAIN
KRAM DATA (K06)
FOCUS INPUT GAIN
KRAM DATA (K05)
SLED OUTPUT GAIN
KRAM DATA (K04)
SLED LOW BOOST FILTER B-L
KRAM DATA (K03)
SLED LOW BOOST FILTER B-H
KRAM DATA (K02)
SLED LOW BOOST FILTER A-L
KRAM DATA (K01)
SLED LOW BOOST FILTER A-H
KRAM DATA (K00)
SLED INPUT GAIN
CXD2588Q/R
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0001
0
0
1
1
1
0
0
0
0
0
– 20 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($341X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K1F)
TRACKING LOW BOOST FILTER B-L
KRAM DATA (K1E)
TRACKING LOW BOOST FILTER B-H
KRAM DATA (K1D)
TRACKING LOW BOOST FILTER A-L
KRAM DATA (K1C)
TRACKING LOW BOOST FILTER A-H
KRAM DATA (K1B)
TRACKING HIGH CUT FILTER B
KRAM DATA (K1A)
TRACKING HIGH CUT FILTER A
KRAM DATA (K19)
TRACKING INPUT GAIN
KRAM DATA (K18)
FIX
KRAM DATA (K17)
HPTZC / AUTO GAIN LOW PASS FILTER B
KRAM DATA (K16)
ANTI SHOCK HIGH PASS FILTER A
KRAM DATA (K15)
HPTZC / AUTO GAIN HIGH PASS FILTER B
KRAM DATA (K14)
HPTZC / AUTO GAIN HIGH PASS FILTER A
KRAM DATA (K13)
FOCUS AUTO GAIN
KRAM DATA (K12)
ANTI SHOCK INPUT GAIN
KRAM DATA (K11)
FOCUS OUTPUT GAIN
KRAM DATA (K10)
FOCUS PHASE COMPENSATE FILTER B
CXD2588Q/R
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0010
0
0
1
1
1
0
0
0
0
0
– 21 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($342X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K2F)
NOT USED
KRAM DATA (K2E)
NOT USED
KRAM DATA (K2D)
FOCUS GAIN DOWN OUTPUT GAIN
KRAM DATA (K2C)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
KRAM DATA (K2B)
FOCUS GAIN DOWN DEFECT HOLD GAIN
KRAM DATA (K2A)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
KRAM DATA (K29)
FOCUS GAIN DOWN LOW BOOST FILTER B-L
KRAM DATA (K28)
FOCUS GAIN DOWN LOW BOOST FILTER B-H
KRAM DATA (K27)
FOCUS GAIN DOWN LOW BOOST FILTER A-L
KRAM DATA (K26)
FOCUS GAIN DOWN LOW BOOST FILTER A-H
KRAM DATA (K25)
FOCUS GAIN DOWN HIGH CUT FILTER B
KRAM DATA (K24)
FOCUS GAIN DOWN HIGH CUT FILTER A
KRAM DATA (K23)
TRACKING AUTO GAIN
KRAM DATA (K22)
TRACKING OUTPUT GAIN
KRAM DATA (K21)
TRACKING PHASE COMPENSATE FILTER B
KRAM DATA (K20)
TRACKING PHASE COMPENSATE FILTER A
CXD2588Q/R
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0011
0
0
1
1
1
0
0
0
0
0
– 22 –
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($343X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K3F)
NOT USED
KRAM DATA (K3E)
TRACKING GAIN UP OUTPUT GAIN
KRAM DATA (K3D)
TRACKING GAIN UP PHASE COMPENSATE FILTER B
KRAM DATA (K3C)
TRACKING GAIN UP PHASE COMPENSATE FILTER A
KRAM DATA (K3B)
TRACKING GAIN UP2 LOW BOOST FILTER B-L
KRAM DATA (K3A)
TRACKING GAIN UP2 LOW BOOST FILTER B-H
KRAM DATA (K39)
TRACKING GAIN UP2 LOW BOOST FILTER A-L
KRAM DATA (K38)
TRACKING GAIN UP2 LOW BOOST FILTER A-H
KRAM DATA (K37)
TRACKING GAIN UP2 HIGH CUT FILTER B
KRAM DATA (K36)
TRACKING GAIN UP2 HIGH CUT FILTER A
KRAM DATA (K35)
ANTI SHOCK FILTER COMPARATE GAIN
KRAM DATA (K34)
ANTI SHOCK HIGH PASS FILTER B-L
KRAM DATA (K33)
ANTI SHOCK HIGH PASS FILTER B-H
KRAM DATA (K32)
NOT USED
KRAM DATA (K31)
ANTI SHOCK LOW PASS FILTER B
KRAM DATA (K30)
SLED INPUT GAIN (when SFSK = 1 TG up2)
CXD2588Q/R
3
Register
SELECT
Command
Address 2
Address 3
0011
0100
0100
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
D10
– 23 –
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
D9
Address 4
0
D23 to D20 D19 to D16 D15 to D12 D11
Address 1
Command Table ($344X)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
D8
D6
D5
D4
D3
D2
D1
Data 2
D0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
D7
Data 1
KRAM DATA (K4F)
NOT USED
KRAM DATA (K4E)
NOT USED
KRAM DATA (K4D)
FOCUS HOLD FILTER OUTPUT GAIN
KRAM DATA (K4C)
FOCUS HOLD FILTER B-L
KRAM DATA (K4B)
FOCUS HOLD FILTER B-H
KRAM DATA (K4A)
FOCUS HOLD FILTER A-L
KRAM DATA (K49)
FOCUS HOLD FILTER A-H
KRAM DATA (K48)
FOCUS HOLD FILTER INPUT GAIN
KRAM DATA (K47)
NOT USED
KRAM DATA (K46)
TRACKING HOLD INPUT GAIN (when THSK = 1 TG up2)
KRAM DATA (K45)
TRACKING HOLD FILTER OUTPUT GAIN
KRAM DATA (K44)
TRACKING HOLD FILTER B-L
KRAM DATA (K43)
TRACKING HOLD FILTER B-H
KRAM DATA (K42)
TRACKING HOLD FILTER A-L
KRAM DATA (K41)
TRACKING HOLD FILTER A-H
KRAM DATA (K40)
TRACKING HOLD FILTER INPUT GAIN
CXD2588Q/R
3
Register
SELECT
Command
0
1
0
0011
– 24 –
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
0
1
D17
D18
Address
0
0
1
1
D17
D18
0
D23 to D20 D19
0011
0
D23 to D20 D19
Address 1
Command Table ($34FX to 3FX)
1
0
1
0
1
0
1
0
1
0
1
D16
0
0
0
D16
1
1
1
D13
FS5 FS4
FT0
D8
TJ2
TJ1
D6
D5
D4
D3
D2
D1
Data 3
TV5
FB5
D6
D5
Data 3
TV6
FB6
D4
TV4
FB4
D3
TV3
FB3
TV1
FB1
D2
D1
Data 4
TV2
FB2
D0
TV0
—
FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0
D7
TV7
FB7
—
D0
TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0
FS2 FS1 FS0
FS3
D9
D8
TV9 TV8
FB9 FB8
D10
TJ3
D7
Data 2
FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1
D9
Data 2
0
1
0
D10
D11
0
0
1
D11
Data 1
0
0
TLD2 TLD1 TLD0
0
0
0
AGG4 XT4D XT2D
0
DRR2 DRR1 DRR0
0
0
0
0
0
0
0
0
0
0
0
AGHF ASOT Others
—: Don’t care
SLED FILTER
TZC/COUT
BOTTOM/MIRR
Operation for MIRR/
DFCT/FOK
LKIN COIN MDFI MIRI XT1D Filter
0
0
ASFG FTQ LPAS SRO1
0
0
BTS1 BTS0 MRC1 MRC0
F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD
SFID SFSK THID THSK
0
0
SJHD INBK MTI0 FOCUS BIAS
0
TJD0 FPS1 FPS0 TPS1 TPS0
0
COSS COTS CETZ CETF COT2 COT1 MOT2
0
0
0
FBON FBSS FBUP FBV1 FBV0
0
SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT
0
0
SERIAL DATA READ
MODE/SELECT
0
DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0
0
LEVEL/AUTO GAIN/
DFSW/ (Initialize)
FZSL/SLED MOVE/
Voltage/AUTO GAIN
DTZC/TRACK JUMP
VOLTAGE/AUTO GAIN
FOCUS SEARCH SPEED/
VOLTAGE/AUTO GAIN
TRVSC DATA
FOCUS BIAS DATA
FOCUS BIAS LIMIT
VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0
FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT
TJ4
D13
D12
1
1
1
D12
D14
Data 1
1
1
1
D14
TDZC DTZC TJ5
FT1
D15
1
1
1
D15
Address 2
CXD2588Q/R
0
0
0
0
0
0
0
1
1
1
1
Blind (A, E),
Overflow (C)
Brake (B)
KICK (D)
Auto sequence (N)
track jump
count setting
MODE
specification
Function
specification
Audio CTRL
Serial bus
CTRL
Spindle servo
coefficient setting
CLV CTRL
CLV mode
6
7
8
9
A
– 25 –
B
C
D
E
1
1
0
0
1
1
1
1
1
1
0
0
1
0
1
1
0
0
1
1
1
1
1
0
1
0
5
1
0
D1
Auto sequence
D2
4
D3
Address
Command
Register
Instruction Table
0
1
0
1
0
0
1
1
0
1
0
1
0
D0
D2
D1
D0
—
—
—
D3
—
—
—
D2
—
—
—
D1
Data 2
0
0
Mute ATT
Mute ATT
0
SL0 CPUSR
0
0
DSPB
ON/OFF
TB
TP
SYCOF
SYCOF
—
—
ZDPL ZMUT
ZDPL ZMUT
0
—
VCO2
THRU
2
—
—
—
D1
0
—
0
1
—
—
—
D0
0
—
0
—
—
—
—
D3
DCOF
—
0
—
—
—
—
D2
0
—
0
—
—
—
—
D1
Data 5
0
—
0
—
—
—
—
D0
—
—
—
—
D2
—
—
—
—
D1
—
—
—
—
D0
—
—
—
—
—
—
—
—
—
—
—
—
TXON TXOUT OUTL1 OUTL0
—
—
—
—
D3
Data 6
—
0
0
—
Gain Gain
CAV1 CAV0
—
—
—
0
—
—
—
0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FMUT LRWO BSBST BBSL
—
—
0
0
0
0
0
4
—
—
—
D2
Data 4
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
0
0
0
8
—
—
—
D3
Gain
VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0
CLVS
—
16
—
—
—
D0
—
—
32
—
—
—
D1
—
—
0
OPSL2
EMPH SMUT
1
0
OPSL1
MCSL
1
OPSL1
MCSL
0
OPSL2
EMPH SMUT
0
0
64
—
—
—
D2
VCO
KSL3 KSL2 KSL1 KSL0
SEL2
128
—
—
—
D3
Data 3
CM3 CM2 CM1 CM0 EPWM SPDC ICAP SFSL VC2C HIFC LPWR VPON
0
0
0
0
0
SOCT
256
—
—
—
D0
TRMI TRMO MTSL1 MTSL0
0
0
0
0
0
0
DSPB
ON/OFF
0
0
VCO
DOUT DOUT
WSEL
SEL1
Mute ON/OFF
Gain Gain Gain Gain
MDP1 MDP0 MDS1 MDS0
SL1
0
0
0
0
CDROM
32768 16384 8192 4096 2048 1024 512
11.6ms 5.8ms 2.9ms 1.45ms
0.36ms 0.18ms 0.09ms 0.05ms
0.18ms 0.09ms 0.05ms 0.02ms
AS3 AS2 AS1 AS0
D3
Data 1
CXD2588Q/R
Command
Register
SELECT
0010
TRACKING
MODE
2
3
0001
TRACKING
CONTROL
1
0
0
0
– 26 –
0011
0
D18
0
0
0
D18
0
1
D18
0
1
0
D16
0
D17
0
D17
0
D16
0
D16
Data 1
0
0
0
D17
Data 1
Address 1
0
D23 to D20 D19
0011
D23 to D20 D19
Address
0000
FOCUS
CONTROL
0
D23 to D20 D19
Command
Register
Address
Command Preset Table ($0X to 34X)
§1-3. CPU Command Presets
0
D15
—
D15
—
—
—
D15
—
—
—
D13
—
D13
D14
D13
Address 2
—
D14
Data 2
—
—
—
D14
Data 2
D12
—
D12
—
—
—
D12
D11
—
D11
—
—
—
D11
—
—
—
D9
—
D9
D9
D8
—
D8
—
—
—
D8
—
—
—
D5
D6
D5
Data 1
D6
D7
—
—
—
D5
Data 4
—
—
—
D6
D7
—
—
—
D7
Data 4
D4
—
D4
—
—
—
D4
See "Coefficient ROM Preset Values Table".
D10
Address 3
—
D10
Data 3
—
—
—
D10
Data 3
D3
—
D3
—
—
—
D3
—
—
—
D1
—
D0
D2
D0
Data 2
—
D2
Data 5
—
—
—
D2
Data 5
D0
—
D0
—
—
—
D0
—: Don’t care
KRAM DATA
($3400XX to $344fXX)
SLED KICK LEVEL
(±1 × basic value) (Default)
TRACKING SERVO OFF
SLED SERVO OFF
TRACKING GAIN UP
FILTER SELECT 1
FOCUS SERVO OFF,
0V OUT
CXD2588Q/R
3
Register
SELECT
Command
0
1
0
0011
– 27 –
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
0
1
D17
D18
Address
0
0
1
1
D17
D18
0
D23 to D20 D19
0011
0
D23 to D20 D19
Address 1
Command Preset Table ($34FX to 3FX)
1
0
1
0
1
0
1
0
1
0
1
D16
0
0
0
D16
1
1
1
D13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
D11
0
0
0
0
1
0
1
D12
0
0
1
D11
1
0
0
0
0
0
0
D13
1
1
1
D12
1
0
0
0
1
0
1
D14
Data 1
1
1
1
D14
1
0
0
0
0
0
0
D15
1
1
1
D15
Address 2
0
0
0
D9
0
0
0
0
0
0
0
0
0
1
0
D10
0
0
0
0
0
0
0
0
0
1
0
D9
Data 2
0
1
0
D10
0
0
0
0
0
0
0
0
0
0
0
D8
0
0
0
D8
Data 1
0
0
0
1
0
0
0
0
1
0
0
D7
0
0
0
D7
0
0
0
D5
0
0
0
0
1
0
0
0
0
0
0
D6
0
0
0
0
0
0
0
0
1
1
1
D5
Data 3
0
0
0
D6
Data 2
0
0
0
0
1
0
0
0
1
0
0
D4
0
0
0
D4
0
0
0
0
0
0
0
0
1
1
1
D3
0
0
0
D3
0
0
0
D1
0
0
0
0
0
0
0
0
0
1
1
D2
0
0
0
0
0
0
0
0
1
1
0
D1
Data 4
0
0
0
D2
Data 3
0
0
0
0
0
0
0
0
0
0
1
D0
0
0
0
D0
Others
Filter
—: Don’t care
SLED FILTER
TZC/COUT
BOTTOM/MIRR
Operation for MIRR/
DFCT/FOK
FOCUS BIAS
SERIAL DATA READ
MODE/SELECT
LEVEL/AUTO GAIN/
DFSW/ (Initialize)
FZSL/SLED MOVE/
Voltage/AUTO GAIN
DTZC/TRACK JUMP
VOLTAGE AUTO GAIN
FOCUS SEARCH SPEED/
VOLTAGE AUTO GAIN
TRVSC DATA
FOCUS BIAS DATA
FOCUS BIAS LIMIT
CXD2588Q/R
1
1
1
1
Spindle servo
coefficient setting
CLV CTRL
CLV mode
C
D
E
1
Function
specification
9
Serial bus
CTRL
1
MODE
specification
8
B
0
Auto sequence (N)
track jump
count setting
7
1
0
KICK (D)
6
Audio CTRL
0
Blind (A, E),
Overflow (C)
Brake (B)
5
A
0
Auto sequence
4
D3
Command
Register
Reset Initialization
– 28 –
1
1
1
0
0
0
0
1
1
1
1
D2
1
0
0
1
1
0
0
1
1
0
0
D1
Address
0
1
0
1
0
1
0
1
0
1
0
D0
0
0
0
0
0
0
0
0
0
0
0
D3
0
0
1
0
0
0
0
0
1
1
0
D2
0
0
1
1
1
0
0
0
1
0
0
D1
Data 1
0
0
0
0
1
0
0
0
1
1
0
D0
0
1
—
0
0
0
0
0
—
—
—
D3
0
1
—
1
0
0
0
0
—
—
—
D2
0
1
—
0
0
0
0
0
—
—
—
D1
Data 2
0
0
—
0
0
0
0
1
—
—
—
D0
0
0
—
0
0
0
0
0
—
—
—
D3
0
0
—
0
1
0
0
0
—
—
—
D2
0
0
—
0
0
0
1
0
—
—
—
D1
Data 3
0
0
—
0
0
0
0
0
—
—
—
D0
0
—
—
—
0
0
0
0
—
—
—
D3
0
—
—
—
0
0
0
0
—
—
—
D2
0
—
—
—
0
0
0
0
—
—
—
D1
Data 4
0
—
—
—
0
0
0
0
—
—
—
D0
—
—
—
—
0
0
0
—
—
—
—
D3
—
—
—
—
0
0
0
—
—
—
—
D2
—
—
—
—
0
0
0
—
—
—
—
D1
Data 5
—
—
—
—
0
0
0
—
—
—
—
D0
—
—
—
—
0
—
0
—
—
—
—
D3
—
—
—
—
0
—
0
—
—
—
—
D2
—
—
—
—
0
—
0
—
—
—
—
D1
Data 6
—
—
—
—
0
—
0
—
—
—
—
D0
CXD2588Q/R
CXD2588Q/R
<Coefficient ROM Preset Values Table (1)>
ADDRESS
DATA
K00
K01
K02
K03
K04
K05
K06
K07
K08
K09
K0A
K0B
K0C
K0D
K0E
K0F
E0
81
23
7F
6A
10
14
30
7F
46
81
1C
7F
58
82
7F
SLED INPUT GAIN
SLED LOW BOOST FILTER A-H
SLED LOW BOOST FILTER A-L
SLED LOW BOOST FILTER B-H
SLED LOW BOOST FILTER B-L
SLED OUTPUT GAIN
FOCUS INPUT GAIN
SLED AUTO GAIN
FOCUS HIGH CUT FILTER A
FOCUS HIGH CUT FILTER B
FOCUS LOW BOOST FILTER A-H
FOCUS LOW BOOST FILTER A-L
FOCUS LOW BOOST FILTER B-H
FOCUS LOW BOOST FILTER B-L
FOCUS PHASE COMPENSATE FILTER A
FOCUS DEFECT HOLD GAIN
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K1A
K1B
K1C
K1D
K1E
K1F
4E
32
20
30
80
77
80
77
00
F1
7F
3B
81
44
7F
5E
FOCUS PHASE COMPENSATE FILTER B
FOCUS OUTPUT GAIN
ANTI SHOCK INPUT GAIN
FOCUS AUTO GAIN
HPTZC / Auto Gain HIGH PASS FILTER A
HPTZC / Auto Gain HIGH PASS FILTER B
ANTI SHOCK HIGH PASS FILTER A
HPTZC / Auto Gain LOW PASS FILTER B
Fix∗
TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K2A
K2B
K2C
K2D
K2E
K2F
82
44
18
30
7F
46
81
3A
7F
66
82
44
4E
1B
00
00
TRACKING PHASE COMPENSATE FILTER A
TRACKING PHASE COMPENSATE FILTER B
TRACKING OUTPUT GAIN
TRACKING AUTO GAIN
FOCUS GAIN DOWN HIGH CUT FILTER A
FOCUS GAIN DOWN HIGH CUT FILTER B
FOCUS GAIN DOWN LOW BOOST FILTER A-H
FOCUS GAIN DOWN LOW BOOST FILTER A-L
FOCUS GAIN DOWN LOW BOOST FILTER B-H
FOCUS GAIN DOWN LOW BOOST FILTER B-L
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
FOCUS GAIN DOWN DEFECT HOLD GAIN
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
FOCUS GAIN DOWN OUTPUT GAIN
NOT USED
NOT USED
CONTENTS
∗ Fix indicates that normal preset values should be used.
– 29 –
CXD2588Q/R
<Coefficient ROM Preset Values Table (2)>
ADDRESS
DATA
CONTENTS
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K3A
K3B
K3C
K3D
K3E
K3F
80
66
00
7F
6E
20
7F
3B
80
44
7F
77
86
0D
57
00
SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.)
ANTI SHOCK LOW PASS FILTER B
NOT USED
ANTI SHOCK HIGH PASS FILTER B-H
ANTI SHOCK HIGH PASS FILTER B-L
ANTI SHOCK FILTER COMPARATE GAIN
TRACKING GAIN UP2 HIGH CUT FILTER A
TRACKING GAIN UP2 HIGH CUT FILTER B
TRACKING GAIN UP2 LOW BOOST FILTER A-H
TRACKING GAIN UP2 LOW BOOST FILTER A-L
TRACKING GAIN UP2 LOW BOOST FILTER B-H
TRACKING GAIN UP2 LOW BOOST FILTER B-L
TRACKING GAIN UP PHASE COMPENSATE FILTER A
TRACKING GAIN UP PHASE COMPENSATE FILTER B
TRACKING GAIN UP OUTPUT GAIN
NOT USED
K40
K41
K42
K43
K44
K45
K46
K47
K48
K49
K4A
K4B
K4C
K4D
K4E
K4F
04
7F
7F
79
17
6D
00
00
02
7F
7F
79
17
54
00
00
TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is a accessed with THSK = 1.)
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
– 30 –
CXD2588Q/R
§1-4. Description of SENS Signals and Commands
SENS output
Microcomputer serial register
(latching not required)
SENS output
$0X
FZC
—
$1X
As (Anti Shock)
—
$2X
TZC
—
$30 to 37
SSTP
—
$38
AGOK
—
$38
XA VEBSY
—
$3904
TE Avrg Reg.
9bit
$3908
FE Avrg Reg.
9bit
$390C
VC Avrg Reg.
9bit
$391C
TRVSC Reg.
9bit
$391D
FB Reg.
9bit
$391F
RFDC Avrg. Reg.
8bit
$3A
FBIAS count STOP
—
$3B to 3F
SSTP
—
$4X
XBUSY
—
$5X
FOK
—
$6X, 7X, 8X, 9X
0
—
$AX
GFS
—
$BX
0
—
$CX
COUT frequency division
—
$DX
0
—
$EX
OV64
—
$FX
0
—
Output data length
The SENS output can be read from the SQSO pin when SOUT = 0, SL1 = 1 and SL0 = 0.
$38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement.
SSTP is output in all other cases.
Description of SENS Signals
SENS output
Contents
XBUSY
Low while the auto sequencer is in operation, high when operation terminates.
FOK
Outputs the same signal as the FOK pin.
High for "focus OK".
GFS
High when the regenerated frame sync is obtained with the correct timing.
COUT
frequency
division
Counts the number of tracks with frequency division ratio set by $B.
High when $C is latched, and toggles each time COUT is counted just for the frequency
division ratio set by $B.
OV64
Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing
through the sync detection filter.
– 31 –
CXD2588Q/R
The meaning of the data for each address is explained below.
$4X commands
AS3
AS2
AS1
AS0
CANCEL
0
0
0
0
FOCUS-ON
0
1
1
1
1 TRACK JUMP
1
0
0
RXF
10 TRACK JUMP
1
0
1
RXF
2 NTRACK JUMP
1
1
0
RXF
N TRACK MOVE
1
1
1
RXF
Command
RXF = 0 FORWARD
RXF = 1 REVERSE
• When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.
• When the Track jump/Move commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is
interrupted.
$5X commands
Auto sequence timer setting
Set timers: A, E, C, B
Command
D23
D22
D21
D20
Blind (A, E), Over flow (C)
0.18ms
0.09ms
0.05ms
0.02ms
Brake (B)
0.36ms
0.18ms
0.09ms
0.05ms
e.g.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset)
A = E = C = 0.11ms
B = 0.23ms
$6X commands
Auto sequence timer setting
Set timer: D
Command
KICK (D)
D23
D22
D21
D20
11.6ms
5.8ms
2.9ms
1.45ms
e.g.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset)
D = 10.15ms
$7X commands
Auto sequence track jump/move count setting (N)
Data 1
Command
Data 2
Data 3
Data 4
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Auto sequence track jump
215 214 213 212 211 210
count setting
29
28
27
26
25
24
23
22
21
20
This command is used to set N when a 2N-track jump or N-track move is executed for auto sequence.
• The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count
depends on the mechanical limitations of the optical system.
• The number of tracks jumped is counted according to the COUT signals.
– 32 –
CXD2588Q/R
$8X commands
Command
Data 1
D3
D2
D1
Data 2
D0
D3
DOUT DOUT
VCO
Mode
CDROM
WSEL
Mute
ON/OFF
SEL1
specification
Data 3
D2
D1
D0
D3
D2
D1
D0
0
SOCT
VCO
SEL2
KSL3
KSL2
KSL1
KSL0
See "$BX Commands".
Data 4
Data 5
Data 6
D3
D2
D1
D0
D3
D2
D1
D0
0
0
VCO2
THRU
0
0
0
0
0
D3
D2
D1
D0
TXON TXOUT OUTL1 OUTL0
Command bit
C2PO timing
Processing
CDROM = 1
See Timing
Chart 1-1.
CDROM mode; average value interpolation and pre-value hold
are not performed.
CDROM = 0
See Timing
Chart 1-1.
Audio mode; average value interpolation and pre-value hold
are performed.
Command bit
Processing
DOUT Mute = 1
Digital Out output is muted. (DA output is not muted.)
DOUT Mute = 0
If other mute conditions are not set, Digital Out is not muted.
Command bit
Processing
DOUT ON/OFF = 1
Digital Out is output from the DOUT pin.
DOUT ON/OFF = 0
Digital Out is not output from the DOUT pin.
WSEL = 1
Sync protection window width
±26 channel clock∗1
Anti-rolling is enhanced.
WSEL = 0
±6 channel clock
Sync window protection is enhanced.
Command bit
Application
∗1 In normal-speed playback, channel clock = 4.3218MHz.
– 33 –
CXD2588Q/R
Command bit
Processing
VCOSEL1
KSL3
KSL2
0
0
0
Multiplier PLL VCO1 is set to normal speed, and the output is 1/1
frequency-divided.
0
0
1
Multiplier PLL VCO1 is set to normal speed, and the output is 1/2
frequency-divided.
0
1
0
Multiplier PLL VCO1 is set to normal speed, and the output is 1/4
frequency-divided.
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Multiplier PLL VCO1 is set to normal speed, and the output is 1/8
frequency-divided.
Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/1
frequency-divided.
Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/2
frequency-divided.
Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/4
frequency-divided.
Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/8
frequency-divided.
∗1 Approximately twice the normal speed
Command bit
Processing
VCOSEL2
KSL1
KSL0
0
0
0
Wide-band PLL VCO2 is set to normal speed, and the output is 1/1
frequency-divided.
0
0
1
Wide-band PLL VCO2 is set to normal speed, and the output is 1/2
frequency-divided.
0
1
0
Wide-band PLL VCO2 is set to normal speed, and the output is 1/4
frequency-divided.
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Wide-band PLL VCO2 is set to normal speed, and the output is 1/8
frequency-divided.
Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/1
frequency-divided.
Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/2
frequency-divided.
Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/4
frequency-divided.
Wide-band PLL VCO2 is set to high speed∗2, and the output is 1/8
frequency-divided.
∗2 Approximately twice the normal speed
– 34 –
CXD2588Q/R
Command bit
Processing
VCO2 THRU = 0
V16M output is internally connected to VCKI. Set VCKI to low.
VCO2 THRU = 1
V16M output is not internally connected. Input the clock from VCKI.
∗ These bits select the internal or external connection for the VCO2 used in CAV-W mode.
Command bit
Processing
TXON = 0
When CD TEXT data is not demodulated, set TXON to 0.
TXON = 1
When CD TEXT data is demodulated, set TXON to 1.
∗ See "$4-14. CD TEXT Data Demodulation"
Command bit
Processing
TXOUT = 0
Various signals except for CD TEXT is output from the SQSO pin.
TXOUT = 1
CD TEXT data is output from the SQSO pin.
∗ See "$4-14. CD TEXT Data Demodulation"
Command bit
Processing
OUTL1 = 0
WFCK, XPCK C4M, WDCK and FSTO are output. The signal input to FSTI is supplied
to the digital servo block.
OUTL1 = 1
WFCK, XPCK C4M, WDCK and FSTO outputs are set to low. FSTO and FSTI are
internally connected. Set FSTI to low.
Command bit
Processing
OUTL0 = 0
PCMD, BCK, LRCK and EMPH are output.
OUTL0 = 1
PCMD, BCK, LRCK and EMPH outputs are low.
PCMD and PCMDI, BCK and BCKI, LRCK and LRCKI and EMPH and EMPHI are
internally connected. Set PCMDI, BCKI, LRCKI and EMPHI to low.
– 35 –
– 36 –
C2PO
CDROM = 1
C2PO
CDROM = 0
LRCK
Timing Chart 1-1
C2 Pointer for lower 8bits
Rch C2 Pointer
C2 Pointer for upper 8bits
Rch 16bit C2 Pointer
C2 Pointer for lower 8bits
Lch C2 Pointer
C2 Pointer for upper 8bits
Lch 16bit C2 Pointer
If C2 Pointer = 1,
data is NG
CXD2588Q/R
CXD2588Q/R
∗ Data 2 D0 and subsequent data are for DF/DAC function settings.
$9X commands (OPSL1= 0)
Data 1
Command
Function
specification
D3
D2
D1
0
DSPB
ON/OFF
0
Data 2
D0 D3 to D1 D0
0
Data 4
Data 3
000 SYCOF
D3
D2
D1
D0
0
MCSL
0
0
D3
ZDPL ZMUT
OPSL1
Function
specification
Data 1
D3
D2
D1
0
DSPB
ON/OFF
0
D1
D0
—
—
Data 5
D3
D2
D1
D0
—
—
—
—
∗ Data 2 D0 and subsequent data are for DF/DAC function settings.
$9X commands (OPSL1= 1)
Command
D2
Data 3
Data 2
D0 D3 to D1 D0
0
000 SYCOF
Data 4
D3
D2
D1
D0
1
MCSL
0
0
D3
D2
ZDPL ZMUT
OPSL1
DSPB = 1
Double-speed playback (CD-DSP block)
DSPB = 0
Normal-speed playback (CD-DSP block)
SYCOF = 1
LRCK asynchronous mode
SYCOF = 0
Normal operation
D1
D0
0
DCOF
0
0
Processing
OPSL1 = 1
DCOF can be set.
OPSL1 = 0
DCOF cannot be set.
Command bit
Processing
MCSL = 1
DF/DAC block master clock selection. Crystal = 768Fs (33.8688MHz)
MCSL = 0
DF/DAC block master clock selection. Crystal = 384Fs (16.9344MHz)
– 37 –
0
D2
∗ Set SYCOF = 0 in advance when setting the $AX command LRWO to 1.
Command bit
0
D3
Processing
Command bit
D0
Data 5
Processing
Command bit
D1
CXD2588Q/R
Processing
Command bit
ZDPL = 1
LMUT and RMUT pins are high when muted.
ZDPL = 0
LMUT and RMUT pins are low when muted.
∗ See "Mute flag output" for the mute flag output conditions.
Processing
Command bit
ZMUT = 1
Zero detection mute is on.
ZMUT = 0
Zero detection mute is off.
Processing
Command bit
DCOF = 1
DC offset is off.
DCOF = 0
DC offset is on.
∗ DCOF can be set when OPSL1 = 1.
∗ Set DC offset to off when zero detection mute is on.
∗ Data 2 and subsequent data are for DF/DAC function settings.
$AX commands (OPSL2 = 0)
Command
Audio CTRL
Data 1
Data 3
Data 2
D3
D2
D1
D0
D3
D2
D1
0
0
Mute
ATT
0
0
0
D0
D3
EMPH SMUT
D2
0
OPSL2
Data 3
Data 4
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
∗ Data 2 and subsequent data are for DF/DAC function settings.
$AX commands (OPSL2 = 1)
Command
Audio CTRL
Data 6
Data 5
Data 3
Data 2
Data 1
D3
D2
D1
D0
D3
D2
D1
0
0
Mute
ATT
0
0
1
D0
D3
EMPH SMUT
D2
0
OPSL2
Data 3
Data 4
Data 6
Data 5
D1
D0
D3
D2
D1
D0
D3
D2
D1
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
– 38 –
D0
D3
D2
D1
D0
AD0 FMUT LRWO BSBST BBSL
CXD2588Q/R
Processing
Command bit
Mute = 1
CD-DSP block mute is on. 0 data is output from the CD-DSP block.
Mute = 0
CD-DSP block mute is off.
Processing
Command bit
ATT = 1
CD-DSP block output is attenuated (–12dB).
ATT = 0
CD-DSP block output attenuation is off.
Meaning
Command bit
OPSL2 = 1
FMUT, LRWO, BSBST and BBSL can be set.
OPSL2 = 0
FMUT, LRWO, BSBST and BBSL cannot be set.
Processing
Command bit
EMPH = 1
De-emphasis is on.
EMPH = 0
De-emphasis is off.
∗ If either the EMPHI pin or EMPH is high, de-emphasis is on.
Processing
Command bit
SMUT = 1
Soft mute is on.
SMUT = 0
Soft mute is off.
∗ If either the SMUT pin or SMUT is high, soft mute is on.
Meaning
Command bit
AD10 to 0
Attenuation data.
The attenuation data consists of 11 bits, and is set as follows.
Attenuation data
Audio output
400h
0dB
3FEh
3FDh
:
001h
–0.0085dB
–0.0170dB
000h
The attenuation data (AD10 to AD0) consists of 11bits,
and can be set in 1024 different ways in the range of
000h to 400h.
The audio output from 001h to 400h is obtained using
the following equation.
–60.206dB
–∞
Audio output = 20log
– 39 –
Attenuation data
[dB]
1024
CXD2588Q/R
Command bit
Meaning
FMUT = 1
Forced mute is on.
FMUT = 0
Forced mute is off.
∗ FMUT can be set when OPSL2 = 1.
Meaning
Command bit
LRWO = 1
Forced synchronization mode Note)
LRWO = 0
Normal operation.
∗ LRWO can be set when OPSL2 = 1.
Note) Synchronization is performed at the first falling edge of LRCK during reset, so there is normally no need
to set this mode. However, synchronization can be forcibly performed by setting LRWO = 1.
Processing
Command bit
BSBST = 1
Bass boost is on.
BSBST = 0
Bass boost is off.
∗ BSBST can be set when OPSL2 = 1.
Processing
Command bit
BBSL = 1
Bass boost is Max.
BBSL = 0
Bass boost is Mid.
∗ BBSL can be set when OPSL2 = 1.
– 40 –
1
0
0
0
1
1
– 41 –
1
0
1
0
1
0
1
0
0
L1
SPOB
L0
mode D
Peak meter
PER1
PER0
mode C
PER2
VF1
PER1
C
B
A
SubQ
D
SENS
L2
0
PER2
VF2
PER3
Peak meter
SubQ
mode
CPUSR
D1
VF0
SPOA
D2
SL0
SL0
PER0
SL1
D3
Data 1
mode B
mode A
SQCK
XLAT
1
1
0
1
0
0
1
0
0
1
SL1
SOCT
Serial bus
CTRL
Command
$BX commands
L3
WFCK
PER3
VF3
PER4
0
D0
D2
D1
D0
L4
SCOR
PER4
VF4
PER5
L5
GFS
PER5
VF5
PER6
L6
GTOP
PER6
VF6
PER7
L7
EMPH
PER7
VF7
C1F1
R0
FOK
0
ALOCK
C1F2
R1
LOCK
C1F1
C1F1
0
0
0
C2F2
R2
R3
RFCK XRAOF
C1F2
C1F2
C2F1
R4
C1F1
C2F1
C2F1
0
R5
C1F2
C2F2
C2F2
FOK
R6
C2F1
0
0
GFS
R7
C2F2
FOK
FOK
LOCK
to the register when they are set at the falling edge of
XLAT. Sub Q is loaded to the register with each SCOR,
and Peak meter is loaded when a peak is detected.
The SQSO pin output can be switched to the various
signals by setting the SOCT command of $8X and the SL1
and SL0 commands of $BX. Set SQCK to high at the
falling edge of XLAT.
Except for Sub Q and peak meter, the signals are loaded
TRM1 TRM0 MTSL1 MTSL0
D3
Data 2
GFS
GFS
LOCK
LOCK
EMPH ALOCK
EMPH
EMPH
VF0
VF1
VF2
VF3
VF4
VF5
VF6
VF7
CXD2588Q/R
CXD2588Q/R
Signal
Description
PER0 to 7
RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.
FOK
Focus OK
GFS
High when the frame sync and the insertion protection timing match.
LOCK
GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight
consecutive samples, a low signal is output.
EMPH
High when the playback disc has emphasis.
ALOCK
GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is
output. If GFS is low eight consecutive samples, a low signal is output.
VF0 to 7
Used in CAV-W mode. Results of measuring the disc rotational velocity. (See Timing Chart 2-3.)
VF0 = LSB, VF7 = MSB.
SPOA, B
SPOA and B pin inputs.
WFCK
Write frame clock output.
SCOR
High when either subcode sync S0 or S1 is detected.
GTOP
High when the sync protection window is open.
RFCK
Read frame clock output.
XRAOF
Low when the built-in 16K RAM exceeds the ±4 frame jitter margin.
L0 to L7,
R0 to R7
Peak meter register output. L0 to 7 are the left-channel and R0 to 7 are the right-channel peak
data. L0 and R0 are LSB.
C1F1
C1F2
0
0
1
1
C1 correction status
C2F1
C2F2
No Error
0
0
No Error
0
Single Error Correction
1
0
Single Error Correction
1
Irretrievable Error
1
1
Irretrievable Error
Processing
Command bit
CPUSR = 1
XLON pin is high.
CPUSR = 0
XLON pin is low.
– 42 –
C2 correction status
CXD2588Q/R
Peak meter
XLAT
SQCK
SQSO
L0
L1
L2
L3
L4
L5
L6
L7
R0
R1
R2
R3
R4
R5
R6
R7
(Peak meter)
Setting the SOCT command of $8X to 0 and the SL1 and SL0 commands of $BX to 0 and 1, respectively,
results in peak detection mode. The SQSO output is connected to the peak register. The maximum PCM data
values (absolute value, upper 8bits) for the left and right channels can be read from SQSO by inputting 16
clocks to SQCK. Peak detection is not performed during SQCK input, and the peak register does not change
during readout. This SQCK input judgment uses a retriggerable monostable multivibrator with a time constant
of 270µs to 400µs. The time during which SQCK input is high should be 270µs or less. Also, peak detection is
restarted 270µs to 400µs after SQCK input.
The peak register is reset with each readout (16 clocks input to SQCK).
The maximum value in peak detection mode is detected and held in this status until the next readout. When
switching to peak detection mode, readout should be performed one time initially to reset the peak register.
Peak detection can also be performed for previous value hold and average value interpolation data.
Traverse monitor count value setting
These bits are set when monitoring the traverse condition of the SENS output according to the COUT
frequency division.
Command bit
Processing
TRM1
TRM0
0
0
1/64 frequency division
0
1
1/128 frequency division
1
0
1/256 frequency division
1
1
1/512 frequency division
Monitor output switching
The monitor output can be switched to the various signals by setting the MTSL1 and MTSL0 commands of $B.
Output data
Symbol
Command bit
XUGF
XPCK
GFS
C2PO
MTSL1
MTSL0
0
0
XUGF
XPCK
GFS
C2PO
0
1
MNT1
MNT0
MNT3
C2PO
1
0
RFCK
XPCK
XROF
GTOP
– 43 –
CXD2588Q/R
$CX commands
Command
Servo coefficient setting
D3
D2
D1
D0
Gain
MDP1
Gain
MDP0
Gain
MDS1
Gain
MDS0
Gain
CLVS
CLV CTRL ($DX)
• CLV mode gain setting: GCLVS
Gain
MDS1
Gain
MDS0
Gain
CLVS
GCLVS
0
0
0
–12dB
0
0
1
–6dB
0
1
0
–6dB
0
1
1
0dB
1
0
0
0dB
1
0
1
+6dB
• CLVP mode gain setting: GMDP: GMDS
Gain
MDP1
Gain
MDP0
GMDP
Gain
MDS1
Gain
MDS0
GMDS
0
0
–6dB
0
0
–6dB
0
1
0dB
0
1
0dB
1
0
+6dB
1
0
+6dB
– 44 –
CXD2588Q/R
$DX commands
Data 1
Command
CLV CTRL
Data 3
Data 2
D3
D2
D1
D0
D3
D2
D1
D0
D3
D2
D1
D0
0
TB
TP
Gain
CLVS
VP7
VP6
VP5
VP4
VP3
VP2
VP1
VP0
See the $CX commands.
Command bit
Description
TB = 0
Bottom hold at a cycle of RFCK/32 in CLVS mode.
TB = 1
Bottom hold at a cycle of RFCK/16 in CLVS mode.
TP = 0
Peak hold at a cycle of RFCK/4 in CLVS mode.
TP = 1
Peak hold at a cycle of RFCK/2 in CLVS mode.
Command bit
VP0 to 7 = F0 (H)
:
VP0 to 7 = E0 (H)
:
VP0 to 7 = C0 (H)
The rotational velocity R of the spindle can be
expressed with the following equation.
Description
Playback at half (normal) speed
to
Playback at normal (double)
speed
to
Playback at (quadruple) speed
R=
256 – n
32
R: Relative velocity at normal speed = 1
n: VP0 to 7 setting value
Note) • Values in parentheses are for when DSPB is 1.
• Values when crystal is 16.9344MHz and XTSL is low or when crystal is 33.8688MHz and XTSL is high.
• VP0 to 7 setting values are valid in CAV-W mode.
4
R – Relative velocity [multiple]
3.5
3
2.5
2
PB
=1
DS
1.5
1
DSP
B=0
0.5
F0
E0
VP0 to 7 setting value [HEX]
Fig. 1-1
– 45 –
D0
C0
CXD2588Q/R
$EX commands
Data 1
Command
CLV mode
Data 2
D3
D2
D1
CM3
CM2
CM1
D0
D2
D3
Data 3
D1
D0
CM0 EPWM SPDC ICAP
Command bit
Mode
D3
SFSL VC2C
D2
D1
D0
HIFC LPWR VPON
Description
CM3
CM2
CM1
CM0
0
0
0
0
STOP
Spindle stop mode.∗1
1
0
0
0
KICK
Spindle forward rotation mode.∗1
1
0
1
0
BRAKE
Spindle reverse rotation mode. Valid only when LPWR = 0
in any mode.∗1
1
1
1
0
CLVS
Rough servo mode. When the RF-PLL circuit isn't locked,
this mode is used to pull the disc rotations within the RFPLL capture range.
1
1
1
1
CLVP
PLL servo mode.
0
1
1
0
CLVA
Automatic CLVS/CLVP switching mode.
Used for normal playback.
∗1 See Timing Charts 1-2 to 1-6.
Command bit
EPWM SPDC
Mode
ICAP
SFSL
VC2C
HIFC
LPWR VPON
Description
0
0
0
0
0
0
0
0
CLV-N
Crystal reference CLV servo.
0
0
0
0
1
1
0
0
CLV-W
Used for normal-speed
playback in CLV-W mode.∗2
0
1
1
0
0
1
0
1
CAV-W
Spindle control with VP0 to 7.
1
0
1
0
0
1
0
1
CAV-W
Spindle control with the external
PWM.
∗2 Figs. 3-1 and 3-2 show the control flow with the microcomputer software in CLV-W mode.
– 46 –
CXD2588Q/R
Data 4
Command
SPD mode
D3
D2
Gain Gain
CAV1 CAV0
Gain
CAV1
Gain
CAV0
Gain
0
0
0dB
0
1
–6dB
1
0
–12dB
1
1
–18dB
Mode
CLV-N
LPWR
0
0
CLV-W
1
0
CAV-W
1
D1
D0
0
0
• This sets the gain when controlling the spindle with the phase comparator
in CAV-W mode.
Command
Timing chart
KICK
1-2 (a)
BRAKE
1-2 (b)
STOP
1-2 (c)
KICK
1-3 (a)
BRAKE
1-3 (b)
STOP
1-3 (c)
KICK
1-4 (a)
BRAKE
1-4 (b)
STOP
1-4 (c)
KICK
1-5 (a)
BRAKE
1-5 (b)
STOP
1-5 (c)
KICK
1-6 (a)
BRAKE
1-6 (b)
STOP
1-6 (c)
Mode
LPWR
Timing chart
CLV-N
0
1-7
0
1-8
1
1-9
0
1-10 (EPWM = 0)
1
1-11 (EPWM = 0)
0
1-12 (EPWM = 1)
1
1-13 (EPWM = 1)
CLV-W
CAV-W
– 47 –
CXD2588Q/R
Timing Chart 1-2
CLV-N mode LPWR = 0
KICK
BRAKE
Z
H
MDP
STOP
MDP
Z
MDP
L
(a) KICK
(b) BRAKE
Z
(c) STOP
Timing Chart 1-3
CLV-W mode (when following the spindle rotational velocity) LPWR = 0
KICK
MDP
BRAKE
STOP
Z
H
MDP
Z
MDP
L
(b) BRAKE
(a) KICK
Z
(c) STOP
Timing Chart 1-4
CLV-W mode (when following the spindle rotational velocity) LPWR = 1
KICK
BRAKE
H
MDP
Z
MDP
Z
(a) KICK
STOP
MDP
(b) BRAKE
Z
(c) STOP
Timing Chart 1-5
CAV-W mode LPWR = 0
KICK
BRAKE
STOP
H
MDP
MDP
(a) KICK
L
MDP
(b) BRAKE
Z
(c) STOP
Timing Chart 1-6
CAV-W mode LPWR = 1
KICK
MDP
H
(a) KICK
BRAKE
MDP
Z
(b) BRAKE
– 48 –
STOP
MDP
Z
(c) STOP
CXD2588Q/R
Timing Chart 1-7
CLV-N mode LPWR = 0
n · 236 (ns) n = 0 to 31
Acceleration
MDP
Z
132kHz
Deceleration
7.6µs
Timing Chart 1-8
CLV-W mode LPWR = 0
Acceleration
MDP
Z
264kHz
3.8µs
Deceleration
Timing Chart 1-9
CLV-W mode LPWR = 1
Acceleration
MDP
Z
264kHz
3.8µs
The BRAKE pulse is masked when LPWR = 1.
Timing Chart 1-10
CAV-W mode EPWM = LPWR = 0
Acceleration
MDP
Z
264kHz
3.8µs
Deceleration
Timing Chart 1-11
CAV-W mode EPWM = LPWR = 1
Acceleration
MDP
Z
264kHz
3.8µs
The BRAKE pulse is masked when LPWR = 1.
– 49 –
CXD2588Q/R
Timing Chart 1-12
CAV-W mode EPWM = 1, LPWR = 0
H
PWMI
L
Acceleration
H
MDP
L
Deceleration
Timing Chart 1-13
CAV-W mode EPWM = LPWR = 1
H
PWMI
L
Acceleration
H
MDP
Z
The BRAKE pulse is masked when LPWR = 1.
– 50 –
CXD2588Q/R
§2. Subcode Interface
This section explains the subcode interface.
There are two methods for reading out a subcode externally.
The 8-bit subcodes P to W can be read from SBSO by inputting EXCK to the CXD2588Q/R.
Sub Q can be readout after checking the CRC of the 80 bits in the subcode frame.
Sub Q can be readout from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes
correctly and CRCF is high.
§2-1. P to W Subcode Readout
Data can be readout by inputting EXCK immediately after WFCK falls. (See Timing Chart 2-1.)
§2-2. 80-bit Sub Q Readout
Fig. 2-1 shows the peripheral block of the 80-bit Sub Q register.
• First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check
circuit.
• 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are
loaded into the parallel/serial register.
When SQSO goes high 400µs (monostable multivibrator time constant) or more after subcode readout, the
CPU determines that new data (which passed the CRC check) has been loaded.
• The CRCF reset is performed by inputting SQCK. When the subcode data is discontinuous after track jump,
etc. CRCF is reset by inputting SQCK. Then, if CRCF =1, the CPU determines that the new data has been
loaded.
• When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result,
although the sequence of bytes is the same, the bits within the bytes are now ordered LSB first.
• Once the 80-bit data load is confirmed, SQCK is input so that the data can be read.
The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.
• The retriggerable monostable multivibrator has a time constant from 270µs to 400µs. When the duration
when SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this
interval, the serial/parallel register is not loaded into the parallel/serial register.
• While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register.
In other words, while reading out with a clock cycle shorter than this time constant, the register will not be
rewritten by CRCOK and others. (See Timing Chart 2-2.)
• The high and low intervals for SQCK should be between 750ns and 120µs.
– 51 –
CXD2588Q/R
Timing Chart 2-1
Internal
PLL clock
4.3218 ± ∆MHz
WFCK
SCOR
EXCK
400ns max
SBSO
S0 · S1
Q
R
WFCK
SCOR
EXCK
SBSO
S0·S1 Q R S T U V W S0·S1
Same
P1
Q R S T U V W
P1
Same
Sub Code P.Q.R.S.T.U.V.W Read Timing
– 52 –
P2
P3
SUBQ
SI
LD
H G F E D C B A
A B C D E F G H
SIN
Order
Inversion
– 53 –
CRCC
SUBQ
8
LD
8
(AMIN)
80-bit P/S Register
8
80-bit S/P Register
Mono/Multi
LD
(ASEC)
SHIFT
LD
(AFRAM)
8
8
8
8
LD
Mix
CRCF
8
SHIFT
SQSO
8
ADDRS CTRL
LD
Fig. 2-1. Block Diagram
SQCK
SO
CXD2588Q/R
LD
LD
– 54 –
SQSO
SQCK
CRCF
Mono/multi (Internal)
SQCK
SQSO
SCOR
WFCK
Timing Chart 2-2
CRCF1
1
2
Order
Inversion
ADR1
3
2
1
94
Determined by mode
93
92
91
ADR2
ADR3
CTL0
270µs to 400µs for SQCK = High
Registere load forbidder
80 clocks
750ns to 120µs
300ns max
ADR0
3
95
L
CTL1
96
CTL2
97
CTL3
CRCF2
98
CXD2588Q/R
CXD2588Q/R
Timing Chart 2-3
Measurement interval (approximately 3.8µs)
Reference window
(132.2kHz)
Measurement pulse
(VCKI/2)
Measurement counter
Load
m
VF0 to 7
The relative velocity R of the disc can be expressed with the following equation.
R=
m+1
32
(R: Relative velocity, m: Measurement results)
VF0 to 7 is the result obtained by counting VCKI/2 pulses while the reference signal (132.2kHz) generated
from the crystal (384Fs) is high. This count is 31 when the disc is rotating at normal speed and 63 when it is
rotating at double speed (when DSPB is low).
– 55 –
CXD2588Q/R
§3. Description of Modes
This LSI has three basic operating modes using a combination of spindle control and the PLL. The operations
for each mode are described below.
§3-1. CLV-N Mode
This mode is compatible with the CXD2507AQ, and operation is the same as for the conventional control. The
PLL capture range is ±150kHz.
§3-2. CLV-W Mode
This is the wide capture range mode. This mode allows the PLL to follow the rotational velocity of the disc. This
rotational following control has two types: using the built-in VCO2 or providing an external VCO. The spindle is
the same CLV servo as for the conventional series. Operation using the built-in VCO2 is described below.
(When using an external VCO, input the signal from the VPCO pin to the low-pass filter, use the output from
the low-pass filter as the control voltage for the external VCO, and input the oscillation output from the VCO to
the VCKI pin.)
When starting to rotate the disc and/or speeding up to the lock range from the condition where the disc is
stopped, CAV-W mode should be used. Specifically, first send $E6650 to set CAV-W mode and kick the disc,
then send $E60C0 to set CLV-W mode if ALOCK is high, which can be readout serially from the SQSO pin.
CLV mode can be used while ALOCK is high. The microcomputer monitors the serial data output, and must
return the operation to the speed adjusting state (CAV-W mode) when ALOCK becomes low. The control flow
according to the microcomputer software is shown in Fig. 3-2.
In CLV-W mode (normal), low power consumption is achieved by setting LPWR to high. Control was formerly
performed by applying acceleration and deceleration pulses to the spindle motor. However, when LPWR is set
to high, deceleration pulses are not output, thereby achieving low power consumption mode.
Note) The capture range for CLV-W mode has theoretically the range up to the signal processing limit.
§3-3. CAV-W Mode
This is CAV mode. In this mode, the external clock is fixed and it is possible to control the spindle to variable
rotational velocity. The rotational velocity is determined by the VP0 to 7 setting values or the external PWM.
When controlling the spindle with VP0 to 7, setting CAV-W mode with the $E6650 command and controlling
VP0 to 7 with the $DX commands allows the rotational velocity to be varied from low speed to double speed.
(See the $DX commands.) Also, when controlling the spindle with the external PWM, the PWMI pin is binary
input which becomes KICK during high intervals and BRAKE during low intervals.
The microcomputer can know the rotational velocity using V16M. The reference for the velocity measurement
is a signal of 132.2kHz obtained by 1/128-frequency dividing the crystal (384Fs). The velocity is obtained by
counting V16M/2 pulses while the reference is high, and the result is output from the new CPU interface as
8 bits (VF0 to 7). These measurement results are 31 when the disc is rotating at normal speed or 63 when it is
rotating at double speed. These values match those of the 256-n for control with VP0 to 7.
In CAV-W mode, the spindle is set to the desired rotational velocity and the operation speed for the entire
system follows this rotational velocity. Therefore, the cycles for the Fs system clock, PCM data and all other
output signals from this LSI change according to the rotational velocity of the disc.
Note) The capture range for this mode is theoretically up to the signal processing limit.
– 56 –
CXD2588Q/R
CAV-W
CLV-W
Operation mode
Rotational velocity
CLVS
CLVP
Spindle mode
Target velocity
KICK
Time
LOCK
ALOCK
Fig. 3-1. Disc Stop to Normal Condition in CLV-W Mode
CLV-W Mode
CLV-W MODE
START
KICK
$E8000
Mute OFF $A0XXXXX
CAV-W $E6650
(CLVA)
NO
ALOCK = H ?
YES
CLV-W $E60C0
(CLVA)
(WFCK PLL)
YES
ALOCK = L ?
NO
Fig. 3-2. CLV-W Mode Flow Chart
– 57 –
CXD2588Q/R
§4. Description of Other Functions
§4-1. Channel Clock Regeneration by the Digital PLL Circuit
• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.
Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to
11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result,
T, that is the channel clock, is necessary.
In an actual player, the PLL is necessary to regenerate the channel clock because the fluctuation in the
spindle rotation alters the width of the EFM signal pulses.
The block diagram of this PLL is shown in Fig. 4-1.
The CXD2588Q/R has a built-in three-stage PLL.
• The first-stage PLL is for the wide-band PLL. When the internal VCO2 is used, an external LPF is necessary;
when not using the internal VCO2, external LPF and VCO are required.
The output of this first-stage PLL is used as a reference for all clocks within the LSI.
• The second-stage PLL generates the high-frequency clock needed by the third-stage digital PLL.
• The third-stage PLL is a digital PLL that regenerates the actual channel clock.
• A new digital PLL has been provided for CLV-W mode to follow the rotational velocity of the disc in addition
to the conventional secondary loop.
– 58 –
CXD2588Q/R
Block Diagram 4-1
CLV-W
CAV-W
Spindle rotation information
1/32
XTSL
1/2
1/n
Phase comparator
1/2
Selector
OSC
VPCO
CLV-N
CLV-W
CAV-W /CLV-N
Microcomputer
control
n = 1 to 256
(VP7 to 0)
1/K
(KSL1, 0)
LPF
VCOSEL2
VCTL
VCO2
V16M
2/1 MUX
VCKI
VPON
1/M
1/N
Phase comparator
X'tal
PCO
FILI
FILO
1/K
(KSL3, 2)
CLTV
VCO1
VCOSEL1
Digital PLL
RFPLL
CXD2588Q/R
– 59 –
CXD2588Q/R
§4-2. Frame Sync Protection
• In normal-speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is
used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be
recognized, the data is processed as error data because the data cannot be recognized. As a result,
recognizing the frame sync properly is extremely important for improving playability.
• In the CXD2588Q/R, window protection and forward protection/backward protection have been adopted for
frame sync protection. These functions achieve very powerful frame sync protection. There are two window
widths: one for cases where a rotational disturbance affects the player and the other for cases where there is
no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the
backward protection counter to 3. Concretely, when the frame sync is being played back normally and then
cannot be detected due to scratches etc., a maximum of 13 frames are inserted. If the frame sync cannot be
detected for 13 frames or more, the window opens to resynchronize the frame sync.
In addition, immediately after the window opens and the resynchronization is executed, if a proper frame
sync cannot be detected within 3 frames, the window opens immediately.
§4-3. Error Correction
• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code
is created with 28-byte information and 4-byte C1 parity.
For C2 correction, the code is created with 24-byte information and 4-byte parity.
Both C1 and C2 are Reed-Solomon codes with a minimum distance of 5.
• The CXD2588Q/R's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to
achieve high playability.
• The correction status can be monitored externally.
See Table 4-2.
• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an
average value interpolation was made for the data.
MNT3
MNT1
MNT0
Description
0
0
0
No C1 errors
0
0
1
One C1 error corrected
0
1
1
C1 correction impossible
1
0
0
No C2 errors
1
0
1
One C2 error corrected
1
1
0
C2 correction impossible
Table 4-2.
– 60 –
CXD2588Q/R
Timing Chart 4-3
Normal-speed PB
t = Dependent on error
condition
MNT3
C1 correction
C2 correction
MNT1
MNT0
Strobe
Strobe
§4-4. DA Interface
• The CXD2588Q/R DA interface is as described below.
This interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first. When LRCK is
high, the data is for the left channel.
– 61 –
R0
1
2
3
– 62 –
PCMD
BCK
(4.23M)
LRCK
(88.2k)
R0
1
2
4
5
Lch MSB (15)
Lch MSB (15)
48-bit slot Double-Speed Playback
PCMD
BCK
(2.12M)
LRCK
(44.1k)
48-bit slot Normal-Speed Playback
Timing Chart 4-4
6
7
8
9
L14
10
L13
11
L12
12
L0
24
L11
L9
Rch MSB
L10
L8
L7
L6
L5
L4
L3
L2
L1
L0
24
RMSB
CXD2588Q/R
CXD2588Q/R
§4-5. Digital Out
There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use,
and the type 2 form 2 format for the manufacture of software.
The CXD2588Q/R supports type 2 form 1.
Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3)
of the channel status.
Digital Out C bit
0
0
ID0
16
1
2
3
From sub Q
0
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0/1
0
0
ID1 COPY Emph
0
0
0
32
48
0
176
Bits 0 to 3 Sub Q control bits that matched twice with CRCOK
Bit 29
1 when VPON = 1
Table 4-5.
§4-6. Servo Auto Sequence
This function performs a series of controls, including auto focus and track jumps. When the auto sequence
command is received from the CPU, auto focus, 1-track jump, 2N-track jump and N-track move are executed
automatically.
The commands which enable transfer to the CXD2588Q/R during the execution of auto sequence are $4X to
$EX.
When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of
100µs after that point.
– 63 –
CXD2588Q/R
(a) Auto focus ($47)
Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on.
If $47 is received from the CPU, the focus servo is turned on according to Fig. 4-3. The auto focus starts with
focus search-up, and note that the pickup should be lowered beforehand (focus search down). In addition,
blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling
edge of FZC after FZC has been continuously high for a longer time than E.
Auto focus
Focus search up
FOK=H
NO
YES
(Check whether FZC is continuously high
for the period of time E set with register 5.)
FZC = H
NO
YES
FZC = L
NO
YES
Focus servo ON
END
Fig. 4-6-(a). Auto Focus Flow Chart
– 64 –
CXD2588Q/R
$47latch
XLAT
FOK
(FZC)
BUSY
Command for
DSSP
Blind E
$08
$03
Fig. 4-6-(b). Auto Focus Timing Chart
(b) Track jump
1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled
servos are on. Note that tracking gain-up and braking-on should be sent beforehand because they are not
involved in this sequence.
• 1-track jump
When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance
with Fig. 4-7. Set blind A and brake B with register 5.
• 10-track jump
When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance
with Fig. 4-8. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the
actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when
the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than
the overflow C set with register 5), the tracking and sled servos are turned on.
• 2N-track jump
When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance
with Fig. 4-9. The track jump count N is set with register 7. Although N can be set to 216 tracks, note that the
setting is actually limited by the actuator. COUT is used for counting the number of jumps.
Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is
that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.
• N-track move
When $4E ($4F for REV) is received from the CPU, a FWD (REV) N-track move is performed in accordance
with Fig. 4-10. N can be set to 216 tracks. COUT is used for counting the number of jumps. The N-track move
is executed only by moving the sled, and is therefore suited for moving across several thousand to several
ten-thousand tracks.
– 65 –
CXD2588Q/R
Track
(REV kick for
REV jump)
Track FWD kick
sled servo OFF
WAIT
(Blind A)
COUT =
NO
YES
Track REV
kick
(FWD kick for
REV jump)
WAIT
(Brake B)
Track, sled
servo ON
END
Fig. 4-7-(a). 1-Track Jump Flow Chart
$48 (REV = $49) latch
XLAT
COUT
BUSY
Brake B
Blind A
Command for
DSSP
$28 ($2C)
$2C ($28)
Fig. 4-7-(b). 1-Track Jump Timing Chart
– 66 –
$25
CXD2588Q/R
10 Track
Track, sled
FWD kick
WAIT
(Blind A)
COUT = 5 ?
NO
(Counts COUT × 5)
NO
(Check whether the COUT cycle
is longer than overflow C.)
YES
Track, REV
kick
C = Overflow ?
YES
Track sled
servo ON
END
Fig. 4-8-(a). 10-Track Jump Flow Chart
$4A (REV = $4B) latch
XLAT
COUT
BUSY
Blind A
COUT 5 count
Overflow C
Command for
DSSP
$2E ($2B)
$2A ($2F)
Fig. 4-8-(b). 10-Track Jump Timing Chart
– 67 –
$25
CXD2588Q/R
2N Track
Track, sled
FWD kick
WAIT
(Blind A)
COUT = N
NO
YES
Track REV
kick
C = Overflow
NO
YES
Track servo
ON
WAIT
(Kick D)
Sled servo
ON
END
Fig. 4-9-(a). 2N-Track Jump Flow Chart
$4C (REV = $4D) latch
XLAT
COUT
BUSY
Blind A
Command for
DSSP
$2A ($2F)
COUT N count
Overflow C
$2E ($2B)
$26 ($27)
Fig. 4-9-(b). 2N-Track Jump Timing Chart
– 68 –
Kick D
$25
CXD2588Q/R
N Track move
Track servo OFF
Sled FWD kick
WAIT
(Blind A)
COUT = N
NO
YES
Track, sled
servo OFF
END
Fig. 4-10-(a). N-Track Move Flow Chart
$4E (REV = $4F) latch
XLAT
COUT
BUSY
Blind A
Command for
DSSP
COUT N count
$20
$22 ($23)
Fig. 4-10-(b). N-Track Move Timing Chart
– 69 –
CXD2588Q/R
§4-7. Digital CLV
Fig. 4-11 shows the block diagram. Digital CLV outputs MDS error and MDP error with PWM, with the
sampling frequency increased up to 130Hz during normal-speed playback in CLVS, CLVP and other modes.
In addition, the digital spindle servo gain is variable.
Digital CLV
CLVS U/D
MDS Error
MDP Error
Measure
Measure
Oversampling
Filter-1
2/1 MUX
CLV P/S
Gain
MDS
Gain
MDP
1/2
MUX
CLV P/S
Oversampling
Filter-2
Noise Shape
KICK, BRAKE, STOP
Modulation
PWMI
Mode Select
DCLVMD, LPWR
MDS
CLVS U/D
MDS error
MDP error
PWMI
:
:
:
:
MDP
Up/down signal from CLVS servo
Frequency error for CLVP servo
Phase error for CLVP servo
Spindle drive signal from the microcomputer
Fig. 4-11. Block Diagram
– 70 –
CXD2588Q/R
§4-8. CD-DSP Block Playback Speed
In the CXD2588Q/R, the following playback modes can be selected through different combinations of the
crystal, XTSL pin and the DSPB command of $9X.
CD-DSP block playback speed
Crystal
XTSL
DSPB
768Fs
0
1
CD-DSP block playback speed
4×∗1
768Fs
1
0
1×
768Fs
1
1
2×
384Fs
0
0
1×
384Fs
0
1
384Fs
1
1
2×
1×∗2
Fs = 44.1kHz.
∗1 In 4× speed playback, the timer value for the auto sequence is halved.
∗2 Low power consumption mode. The CD-DSP processing speed is halved, allowing power consumption
to be reduced.
§4-9. DAC Block Playback Speed
The operation speed for the DAC block is determined by the crystal and the MCSL command of $9X
regardless of the CD-DSP operating conditions noted above. This allows the playback modes for the DAC and
CD-DSP blocks to be set independently.
1-bit DAC block playback speed
Crystal
MCSL
DAC block playback speed
768Fs
1
1×
768Fs
0
2×
384Fs
0
1×
Fs = 44.1kHz.
– 71 –
CXD2588Q/R
§4-10. DAC Block Input Timing
Timing Chart 4-12 shows the DAC block input timing chart.
In the CXD2588Q/R, the data can be transferred from the CD signal processor block to the DAC block via the
outside of the LSI. This allows the data to be sent to the DAC block via the audio DSP, etc.
As for the data input to the DAC block without using the audio DSP, there are two methods: one is to connect
directly EMPH, LRCK, BCK and PCMD with EMPHI, LRCKI, BCKI and PCMDI outside the LSI; and the other
is to set OUTL0 of $8X to 1. Note that the outputs of EMPH, LRCK, BCK and PCMD become low when OUTL0
of $8X is set to 0 .
§4-11. Description of DAC Block Functions
Zero data detection
When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or
all "1" has continued about for 300ms, zero data is detected. Zero data detection is performed independently
for the left and right channels.
Mute flag output
The LMUT and RMUT pins go active when any one of the following conditions is met.
The polarity can be selected with the ZDPL command of $9X.
• When zero data is detected
• When a high signal is input to the SYSM pin
• When the SMUT command of $AX is set
Attenuation operation
Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and Y3
(Y1 > Y3 > Y2). First, X1 is sent, followed by X2. If X2 is sent before X1 reaches Y1 (A in the figure), X1
continues approaching Y2. Next, if X3 is sent before X1 reaches Y2 (B or C in the figure), X1 then approaches
Y3 from the value (B or C in the figure) at that point.
0dB
7F (H)
A
Y1
B
Y3
C
Y2
–∞
00 (H)
23.2 [ms]
– 72 –
CXD2588Q/R
DAC block mute operation
Soft mute
Soft mute results and the input data is attenuated to zero when any one of the following conditions is met.
• When attenuation data of "000" (high) is set
• When the SMUT command of $AX is set to 1
• When a high signal is input to the SYSM input pin
Soft mute off
Soft mute on
Soft mute off
0dB
– ∞dB
23.2 [ms]
23.2 [ms]
Forced mute
Forced mute results when the FMUT command of $AX is set to 1.
Forced mute fixes the PWM output that is input to the LPF block to low.
∗ When setting FMUT, set OPSL2 to 1. (See the $AX commands.)
Zero detection mute
Forced mute is applied when the ZMUT command of $9X is set to 1 and the zero data is detected for the
left and right channels.
(See "Zero data detection".)
When the ZMUT command of $9X is set to 1, the forced mute is applied even if the mute flag output
condition is met. When the zero detection mute is on, set the DCOF command of $9X to 1.
– 73 –
1
– 74 –
PCMDI
BCKI
(4.23M)
LRCKI
(88.2k)
R0
1
2
2
3
Lch MSB (15)
Double-Speed Playback
PCMDI R0
BCKI
(2.12M)
LRCKI
(44.1k)
Normal-Speed Playback
Timing Chart 4-12
5
Lch MSB (15)
4
6
7
8
9
L13
11
L12
12
L0
24
L11
Rch MSB
L10
Input Timing DAC Block
L14
10
L9
L8
L7
L6
L5
L4
L3
L2
L1
L0
24
RMSB
CXD2588Q/R
CXD2588Q/R
LRCK Synchronization
Synchronization is performed at the first falling edge of the LRCK input during reset.
After that, synchronization is lost when the LRCK input frequency changes and resynchronization must be
performed.
The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed
changes such as the following cases.
• When the XTSL pin switches between high and low
• When the DSPB command of $9X setting changes
• When the MCSL command of $9X setting changes
LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC
block. Resynchronization must be performed in this case as well.
For resynchronization, set the LRWO command of $AX to 1, wait for one LRCK cycle or more, and then set
LRWO to 0.
∗ When setting LRWO, set OPSL2 to 1. (See the $AX commands.)
SYCOF
When LRCK, PCMD and BCK are connected directly with LRCKI, PCMDI and BCKI, respectively, playback
can be performed easily in CAV-W mode by setting SYCOF of address 9 to 1.
Normally, the memory proof, etc. is used for playback in CAV-W mode.
In CAV-W mode, the LRCK output conforms not to the crystal but to the VCO. Therefore, synchronization is
frequently lost.
Setting SYCOF of address 9 to 1 ignores that the LRCKI input synchronization is lost, facilitating playback.
However, the playback is not perfect because pre-value hold or data skip occurs due to the wow flutter in the
LRCKI input.
∗ Set SYCOF to 0 except when connecting LRCK, PCMD and BCK directly with LRCKI, PCMDI and BCKI,
respectively, and performing playback in CAV-W mode.
Digital Bass Boost
Bass boost without external parts is possible using the built-in digital filter. The boost strength has two levels:
Mid. and Max. BSBST and BBSL of address A are used for the setting.
See Graph 4-13 for the digital bass boost frequency response.
10.00
8.00
Normal
6.00
DBB MID
4.00
DBB MAX
2.00
[dB]
0.00
–2.00
–4.00
–6.00
–8.00
–10.00
–12.00
–14.00
10
30
100
300
1k
3k
Digital Bass Boost Frequency Response [Hz]
Graph 4-13.
– 75 –
10k
30k
CXD2588Q/R
§4-12. LPF Block
The CXD2588Q/R contains an initial-stage secondary active LPF with numerous resistors and capacitors and
an operational amplifier with reference voltage.
The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly.
The reference voltage (VC) is (AVDD – AVSS) × 0.43.
The LPF block application circuit is shown below.
In this circuit, the cut-off frequency is fc ≈ 40kHz.
The external capacitors' values when fc = 30kHz and 50kHz are noted below as a reference.
The resistors' values do not change at this time.
• When fc ≈ 30kHz:
C1 = 200pF, C2 = 910pF
• When fc ≈ 50kHz:
C1 = 120pF, C2 = 560pF
LPF Block Application Circuit
12k
AOUT1 (2)
C2
680p
12k
AIN1 (2)
Vc
C1
150p
12k
Analog out
LOUT1 (2)
Fig. 4-14. LPF External Circuit
– 76 –
CXD2588Q/R
§4-13. Asymmetry Compensation
Fig. 4-15 shows the block diagram and circuit example.
CXD2588Q/R
ASYO
R1
RFAC
R1
R2
R1
ASYI
R1
BIAS
R1
2
=
R2
5
Fig. 4-15. Asymmetry Compensation Application Circuit
– 77 –
CXD2588Q/R
§4-14. CD TEXT Data Demodulation
• In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to 1. During TXON = 1,
connect EXCK to low and do not use the data output from SBSO because the CD TEXT demodulation circuit
uses EXCK and the SBSO pin exclusively.
It requires 26.7ms (max.) to demodulate the CD TEXT data correctly after TXON is set to 1.
• The CD TEXT data is output by switching the SQSO pin with the command. The CD TEXT data output is
enabled by setting the command $8 Data 6 D2 TXOUT to 1. To read data, the readout clock should be input
to SQCK.
• The readable data are the CRC counting results for the each pack and the CD TEXT data (16 bytes) except
for CRC data.
• When the CD TEXT data is read, the order of the MSB and LSB is inverted within each byte. As a result,
although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.
• Data which can be stored in the LSI is 1 packet (4 packs).
TXON
CD TEXT
Decoder
EXCK
SBSO
Subcode
Decoder
SQCK
SQSO
TXOUT
Fig. 4-16. Block Diagram of CD TEXT Demodulation Circuit
– 78 –
– 79 –
TXOUT
(command)
SQCK
SQSO
TXOUT
(command)
SQCK
SQSO
SCOR
4
3
2
1
CRC CRC CRC CRC
CRC Data
CRCF
0
0
80 Clock
Subcode Q Data
0
S2
R2 W1 V1 U1
S1
R1 U3
T3
520 Clock
Pack2
16Byte
MSB LSB
Pack1
16Byte
T1
ID1 (Pack1)
0
4bit
Fig. 4-17. CD TEXT Data Timing Chart
0
LSB
CRC
4bit
S3
U2
Pack4
16Byte
R3 W2 V2
ID2 (Pack1)
Pack3
16Byte
T2 W4 V4
MSB LSB
U4
T4
ID3 (Pack1)
CRCF
S4
CXD2588Q/R
CXD2588Q/R
§5. Description of Servo Signal Processing System Functions and Commands
§5-1. General Description of Servo Signal Processing System (VDD: Supply voltage)
Focus servo
Sampling rate:
88.2kHz (when MCK = 128Fs)
Input range:
0.3VDD to 0.7VDD
Output format:
7-bit PWM
Others:
Offset cancel
Focus bias adjustment
Focus search
Gain-down function
Defect countermeasure
Auto gain control
Tracking servo
Sampling rate:
Input range:
Output format:
Others:
Sled servo
Sampling rate:
Input range:
Output format:
Others:
88.2kHz
0.3VDD to 0.7VDD
7-bit PWM
Offset cancel
E:F balance adjustment
Track jump
Gain-up function
Defect countermeasure
Drive cancel
Auto gain control
Vibration countermeasure
345Hz (MCK = 128Fs)
0.3VDD to 0.7VDD
7-bit PWM
Sled move
FOK, MIRR, DFCT signals generation
RF signal sampling rate:
1.4MHz (MCK = 128Fs)
Input range:
0.43VDD to VDD
Others:
RF zero level automatic measurement
– 80 –
CXD2588Q/R
§5-2. Digital Servo Block Master Clock (MCK)
The internal master clock (MCK) is generated by dividing the frequency of the signal input to FSTI. The
frequency division ratio is 1, 1/2 or 1/4.
Table 5-1 below shows the hypothetical case where the crystal clock generated from the digital signal
processor block is 2/3 frequency-divided and input to the FSTI pin by externally connecting the FSTI pin and
the FSTO pin. By setting $8X command D1 OUTL1 to 1, FSTI and FSTO can be internally connected. (See
$8X commands.)
The XT4D and XT2D command settings can be made with D13 and D12 of $3F, and XT1D with D1 of $3E.
(Default = 0)
The digital servo block is designed with an MCK frequency of 5.6448MHz.
Mode
Crystal
FSTO (FSTI)
XTSL XT4D XT2D XT1D
Frequency division ratio
MCK
1
384Fs
256Fs
∗
∗
∗
1
1
256Fs
2
384Fs
256Fs
∗
∗
1
0
1/2
128Fs
3
384Fs
256Fs
0
0
0
0
1/2
128Fs
4
768Fs
512Fs
∗
∗
∗
1
1
512Fs
5
768Fs
512Fs
∗
∗
1
0
1/2
256Fs
6
768Fs
512Fs
∗
1
0
0
1/4
128Fs
7
768Fs
512Fs
1
0
0
0
1/4
128Fs
Fs = 44.1kHz, ∗: Don't care
Table 5-1.
§5-3. AVRG (Average) Measurement and Compensation
The CXD2588Q/R has a circuit that measures the average of RFDC, VC, FE, and TE and a circuit that
compensates them to control servo effectively.
AVRG measurement and compensation is necessary to initialize the CXD2588Q/R, and is able to cancel the
offset.
The level applied to the VC, FE, RFDC and TE pins can be measured by setting D15 (VLCM), D13 (FLM), D11
(RFLM) and D4 (TCLM) of $38 respectively to 1.
AVRG measurement consists of digitally measuring the level applied to each analog input pin by taking the
average of 256 samples, and then loading these values into the AVRG register.
AVRG measurement requires approximately 2.9ms to 5.8ms after the command is received.
During AVRG measurement, if the upper 8 bits of the command register are 38 (Hex), the completion of AVRG
measurement operation can be confirmed through the SENS pin. (See Timing Chart 5-2.)
XLAT
2.9 to 5.8ms
SENS
(= XAVEBSY)
Max. 1µs
Completion of AVRG measurement
Timing Chart 5-2.
– 81 –
CXD2588Q/R
<Measurement>
• VC AVRG
The offset can be canceled by measuring the VC level which is the center voltage for the system and using
that value to apply compensation to each input error signal.
• FE AVRG
The FE signal DC level is measured. In addition, compensation is applied to the FZC comparator level output
from the SENS pin during FCS SEARCH (focus search) using these measurement results.
• TE AVRG
The TE signal DC level is measured.
• RF AVRG
The MIRR, DFCT and FOK signals are generated from the RF signal. Since the FOK signal is generated by
comparing the RF signal at a certain level, it is necessary to establish a zero level which becomes the
comparator level reference. Therefore, the RF signal is measured before playback, and is compensated to
take this level as the zero level.
An example of sending AVRG measurement and compensation commands is shown below.
(Example) $380800 (RF AVRG measurement on)
$382000 (FE AVRG measurement on)
$380010 (TE AVRG measurement on)
$388000 (VC AVRG measurement on)
(Complete each AVRG measurement before starting the next.)
$38140A (RFLC, FLC0, FLC1 and TLC1 commands on)
(The required compensation should be turned on together; see Fig. 5-3.)
An interval of 5.8ms (when MCK = 128Fs) or more must be maintained between each command, or the SENS
pin must be monitored to confirm that the previous command has been completed before the next AVRG
command is sent.
<Compensation>
See Fig. 5-3 for the contents of each compensation below.
• RFLC
The difference by which the RF signal exceeds the RF AVRG value is input to the RF In register.
(00 is input when the RF signal is lower than the RF AVRG value.)
• TCL0
The value obtained by subtracting the VC AVRG value from the TE signal is input to the TRK In register.
• TCL1
The value obtained by subtracting the TE AVRG value from the TE signal is input to the TRK In register.
• VCLC
The value obtained by subtracting the VC AVRG value from the FE signal is input to the FCS In register.
• FLC1
The value obtained by subtracting the FE AVRG value from the FE signal is input to the FCS In register.
• FLC0
The value obtained by subtracting the FE AVRG value from the FE signal is input to the FZC register.
– 82 –
CXD2588Q/R
§5-4. E:F Balance Adjustment Function
When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search),
the traverse waveform appears in the TE signal due to disc eccentricity.
In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold
filter by setting D5 (TBLM) of $38 to 1.
The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC
register value is established when TBLM returns to 0.
Next, setting D2 (TLC2) of $38 to 1 compensates TE and SE values with the TRVSC register value
(subtraction), resulting the E:F balance offset to be adjusted. (See Fig. 5-3.)
§5-5. FCS Bias (Focus Bias) Adjustment Function
The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See
Fig. 5-3.)
When the FBIAS register value is set when D11 = 0 and D10 = 1 with $34F, data can be written using the 9-bit
value of D9 to D1 (D9: MSB).
In addition, the RF jitter can be monitored by setting the SOCT command of $8 to 1. (See "DSP Block Timing
Chart".)
The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions
as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0.
The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A.
When using the FBIAS register as a counter, the counter stops if the FBIAS value and the value set
beforehand in FBL9 to 1 of $34 matches. Also, if the upper 8 bits of the command register are $3A at this time,
SENS becomes high and the counter stop can be monitored.
A
B
C
FBIAS setting value (FB9 to 1)
LIMIT value (FBL9 to 1)
Here, assume the FBIAS setting value FB9 to 1
and the FBIAS LIMIT value FBL9 to 1 like status
A. For example, if command registers FBUP = 0,
FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from
this status, down count starts from status A and
approaches the set LIMIT value. When the
FBIAS value matches FBL9 to 1, the counter
stops and the SENS pin goes to high. Note that
the up/down counter counts at each sampling
cycle of the focus servo filter. The number of
steps by which the count value changes can be
selected from 1, 2, 4 or 8 steps by FBV1 and
FBV0. When converted to FE input, 1 step
corresponds to 1/512 × VDD × 0.4.
A: Register mode
B: Counter mode
C: Counter mode (when stopped)
SENS pin
– 83 –
– 84 –
FE from A/D
VC AVRG
resister
TE from A/D
SE from A/D
RFDC from A/D
VCLC
TLC0
TLC0 · TLD0
–
–
–
FE AVRG
resister
TE AVRG
resister
RF AVRG
resister
Fig. 5-3.
FLC0
FLC1
TLC1
TLC1 · TLD1
RFLC
–
–
–
–
–
FBIAS
resister
TRVSC
resister
FBON
TLC2
TLC2 · TLD2
–
–
to FZC register
to FCS In register
to TRK In register
to SLD In register
to RF In register
CXD2588Q/R
CXD2588Q/R
§5-6. AGCNTL (Automatic Gain Control) Function
The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate gain with
the servo loop. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but
also obtains the optimal gain for each disc.
The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of
the command register are 38 (Hex), the completion of AGCNTL operation can be confirmed through the SENS
pin. (See Timing Chart 5-4 and "Description of SENS Signals".)
Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation.
Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described
hereafter) must be disabled.
XLAT
Max. 11.4µs
SENS
(= AGOK)
AGCNTL completion
Timing Chart 5-4.
Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking
AGCNTL) due to AGCNTL.
These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written
externally.
After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from
the SENS pin with the serial readout function (described hereafter).
AGCNTL related settings
The following settings can be changed with $35, $36 and $37.
FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex)
TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex)
AGS;
Self-stop on/off
AGJ;
Convergence completion judgment time
AGGF;
Internally generated sine wave amplitude (AGF)
AGGT;
Internally generated sine wave amplitude (AGT)
AGV1;
AGCNTL sensitivity 1 (during rough adjustment)
AGV2;
AGCNTL sensitivity 2 (during fine adjustment)
AGHS;
Rough adjustment on/off
AGHT;
Fine adjustment time
Note) Converging servo loop gain values can be changed with the FG6 to 0 and TG6 to 0 setting values. In
addition, these setting values must be within the effective setting range. The default settings aim for 0
dB at 1kHz. However, since convergence values vary according to the characteristics of each
constituent element of the servo loop, FG and TG values should be set as necessary.
– 85 –
CXD2588Q/R
AGCNTL and default operation have two stages.
In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select
256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value.
The sensitivity at this time can be selected from two types with AGV1.
In the second stage, the AGCNTL coefficient is finely adjusted to approach more appropriate value with
relatively low sensitivity. The sensitivity for the second stage can be selected from two types with AGV2. In the
second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops
changing, the CXD2588Q/R confirms that the AGCNTL coefficient has not changed for a certain period of time
(select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode)
This self-stop mode can be canceled by setting AGS to 0.
In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0.
An example of AGCNTL coefficient transitions during AGCNTL in various settings are shown in Fig. 5-5.
Initial value
Slope AGV1
AGCNTL
coefficient value
Slope AGV2
Convergence value
AGJ
AGHT
AGCNTL
Start
AGCNTL
completion
SENS
Fig. 5-5.
Note) Fig. 5-5 shows the example where the AGCNTL coefficient value converges to the smaller value from
the initial value.
– 86 –
CXD2588Q/R
§5-7. FCS Servo and FCS Search (Focus Search)
The FCS servo is controlled by the 8-bit serial command $0X. (See Table 5-6.)
Register name Command
FOCUS
CONTROL
0
D23 to D20
0 0 0 0
D19 to D16
1 0 ∗ ∗
FOCUS SERVO ON (FOCUS GAIN NORMAL)
1 1 ∗ ∗
FOCUS SERVO ON (FOCUS GAIN DOWN)
0 ∗ 0 ∗
FOCUS SERVO OFF, 0V OUT
0 ∗ 1 ∗
FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT
0 ∗ 1 0
FOCUS SEARCH VOLTAGE DOWN
0 ∗ 1 1
FOCUS SEARCH VOLTAGE UP
∗: Don’t care
Table 5-6.
FCS Search
FCS search is required in the course of turning on the FCS servo.
Fig. 5-7 shows the signals for sending commands $00 → $02 → $03 and performing only FCS search operation.
Fig. 5-8 shows the signals for sending $08 (FCS on) after that.
$00 $02 $03
$00 $02 $03
0
FCSDRV
FCSDRV
RF
RF
FOK
FOK
FZC comparator level
FE
FE
0
0
FZC
FZC
Fig. 5-7.
Fig. 5-8.
– 87 –
$08
CXD2588Q/R
§5-8. TRK (Tracking) and SLD (Sled) Servo Control
The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 5-9.)
When the upper 4 bits of the serial data are 2 (Hex), TZC is output to the SENS pin.
Register name Command
2
TRACKING
MODE
D23 to D20
0 0 1 0
D19 to D16
0 0 ∗ ∗
TRACKING SERVO OFF
0 1 ∗ ∗
TRACKING SERVO ON
1 0 ∗ ∗
FORWARD TRACK JUMP
1 1 ∗ ∗
REVERSE TRACK JUMP
∗ ∗ 0 0
SLED SERVO OFF
∗ ∗ 0 1
SLED SERVO ON
∗ ∗ 1 0
FORWARD SLED MOVE
∗ ∗ 1 1
REVERSE SLED MOVE
∗: Don’t care
Table 5-9.
TRK Servo
The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36.
In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode.
The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the
anti-shock circuit (described hereafter) enabled.
CXD2588Q/R has 2 types of filters in TRK gain-up mode which can be selected by setting D16 of $1. (See
Table 5-17.)
SLD Servo
The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by
multiplying this value by 1×, 2×, 3× or 4× magnification set using D17 and D16 when D18 = D19 = 0 is set with
$3. (See Table 5-10.)
SLD MOV must be performed continuously for 50µs or more. In addition, if the LOCK input signal goes low
when the SLD servo is on, the SLD servo turns off.
Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off
by the default. These operations are disabled by setting D6 (LKSW) of $38 to 1.
Register name Command
3
SELECT
D23 to D20
0 0 1 1
D19 to D16
0 0 0 0
SLED KICK LEVEL (basic value × ±1)
0 0 0 1
SLED KICK LEVEL (basic value × ±2)
0 0 1 0
SLED KICK LEVEL (basic value × ±3)
0 0 1 1
SLED KICK LEVEL (basic value × ±4)
Table 5-10.
– 88 –
CXD2588Q/R
§5-9. MIRR and DFCT Signal Generation
The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and
loaded. The MIRR and DFCT signals are generated from this RF signal.
MIRR Signal Generation
The loaded RF signal is applied to peak hold and bottom hold circuits.
An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is
generated from the average of this envelope waveform.
The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value
from the peak hold value with this MIRR comparator level. (See Fig. 5-11.)
The bottom hold speed and mirror sensitivity can be selected from 4 values using D7 and 6, and D5 and 4,
respectively, of $3C.
RF
Peak Hold
Bottom Hold
Peak Hold
– Bottom Hold
MIRR Comp
(Mirror comparator level)
H
MIRR
L
Fig. 5-11.
DFCT Signal Generation
The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is
generated by comparing the difference between these two peak hold waveforms with the DFCT comparator
level. (See Fig. 5-12.)
The DFCT comparator level can be selected from four values using D13 and D12 of $3B.
RF
Peak Hold1
Peak Hold2
Peak Hold2
– Peak Hold1
SDF
(Defect comparator level)
H
DFCT
L
Fig. 5-12.
– 89 –
CXD2588Q/R
§5-10. DFCT Countermeasure Circuit
The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become
easily dislocated due to scratches or defects on discs.
Specifically, these operations are achieved by detecting scratch and defect with the DFCT signal generation
circuit, and when DFCT goes high, applying the low-frequency component of the error signal before DFCT
went high to the FCS and TRK servo filter inputs. (See Fig. 5-13.)
In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38
to 1.
Hold Filter
Error signal
Hold register
Input register
EN
DFCT
Servo Filter
Fig. 5-13.
§5-11. Anti-Shock Circuit
When vibrations occurs in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the
servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures.
Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is
increased. (See Fig. 5-14.)
The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator
level is practically variable by adjusting the value of the anti-shock filter output coefficient K35.
This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See
Table 5-17.)
This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up
mode by inputting high level to the ATSK pin.
When the upper 4 bits of the command register are 1 (Hex), vibration detection can be monitored from the
SENS pin. It also can be monitored from the ATSK pin by setting the ASOT command of $3F.
ATSK
TE
Anti Shock
Filter
SENS
Comparator
TRK Gain Up
Filter
TRK
PWM Gen
TRK Gain Normal
Filter
Fig. 5-14.
– 90 –
CXD2588Q/R
§5-12. Brake Circuit
Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to
turn on.
The brake circuit prevents these phenomenon.
The brake circuit is to use tracking drive as a brake by cutting unnecessary portions of it utilizing the 180°
offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the
track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 5-15 and 5-16.)
Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by
loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal.
The brake circuit can be turned on and off by D18 of $1. (See Fig. 5-17.)
Inner track
Outer track
Outer track
FWD REV Servo ON
JMP JMP
REV FWD Servo ON
JMP JMP
TRK
DRV
TRK
DRV
RF
Trace
RF
Trace
MIRR
MIRR
TE
0
TE
TZC
Edge
TZC
Edge
TRKCNCL
TRKCNCL
TRK
DRV
TRK
DRV
0
SENS
TZC out
0
0
SENS
TZC out
Fig. 5-15.
Register name Command
1
Inner track
TRACKING
CONTROL
D23 to D20
0 0 0 1
Fig. 5-16.
D19 to D16
1 0 ∗ ∗
ANTI SHOCK ON
0 ∗ ∗ ∗
ANTI SHOCK OFF
∗ 1 ∗ ∗
BRAKE ON
∗ 0 ∗ ∗
BRAKE OFF
∗ ∗ 0 ∗
TRACKING GAIN NORMAL
∗ ∗ 1 ∗
TRACKING GAIN UP
∗ ∗ ∗ 1
TRACKING GAIN UP FILTER SELECT 1
∗ ∗ ∗ 0
TRACKING GAIN UP FILTER SELECT 2
∗: Don’t care
Fig. 5-17.
– 91 –
CXD2588Q/R
§5-13. COUT Signal
The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by
loading the MIRR signal at both edges of the TZC signal. And the used TZC signal can be selected among
three different phases for each COUT signal application.
• HPTZC: For 1-track jumps
Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a
cut-off 1kHz digital HPF; when MCK = 128Fs.)
• STZC: For COUT signal generation when MIRR is externally input and for applications other than
COUT generation.
This is generated from sampling TE at 700kHz. (when MCK = 128Fs)
• DTZC: For high-speed traverse
Reliable COUT signal generation with a delayed phase STZC signal.
Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance
with the MIRR signal delay during high-speed traverse.
The COUT signal output method is switched with D15 and 14 of $3C.
When D15 = 1
: STZC
When D15 = 0 and D14 = 0 : HPTZC
When D15 = 0 and D14 = 1 : DTZC
When the DTZC is selected, the delay can be selected from two values with D14 of $36.
§5-14. Serial Readout Circuit
The following measurement and adjustment results can be readout from the SENS pin by inputting the readout
clock to the SCLK pin by $39. (See Fig. 5-18, Table 5-19 and "Description of SENS Signals".)
Specified commands
$390C: VC AVRG measurement result
$3908: FE AVRG measurement result
$3904: TE AVRG measurement result
$391F: RF AVRG measurement result
$3953: FCS AGCNTL coefficient result
$3963: TRK AGCNTL coefficient result
$391C: TRVSC adjustment result
$391D: FBIAS register value
XLAT
tSPW
tDLS
•••
SCLK
1/fSCLK
Serial Readout Data
(SENS)
MSB
LSB
•••
Fig. 5-18.
Item
Symbol
Min.
Typ.
Max.
Unit
16
MHz
SCLK frequency
fSCLK
SCLK pulse width
tSPW
31.3
ns
Delay time
tDLS
15
µs
Table 5-19.
During readout, the upper 8 bits of the command register must be 39 (Hex).
– 92 –
CXD2588Q/R
§5-15. Writing to the Coefficient RAM
The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and
transfer from the ROM to the RAM is completed approximately 40µs (when MCK = 128Fs) after the XRST pin
rises. (The coefficient RAM cannot be rewritten during this period.)
After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address
of the coefficient RAM.
The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and
D7 to D0 as data. Coefficient rewriting is completed 11.3µs (when MCK = 128Fs) after the command is
received. When rewriting multiple coefficients, be sure to wait 11.3µs (when MCK = 128Fs) before sending the
next rewrite command.
§5-16. PWM Output
FCS, TRK and SLD outputs are output as PWM waveforms.
In particular, FCS and TRK permit accurate drive by using a double oversampling noise shaper.
Timing Chart 5-20 and Fig. 5-21 show examples of output waveforms and drive circuits.
MCK
(5.6448MHz) ↑ ↑ ↑ ↑ ↑ ↑ ↑
Output value +A
Output value –A
Output value 0
64tMCK
64tMCK
64tMCK
SLD
SFDR
AtMCK
SRDR
AtMCK
FCS/TRK
32tMCK
FFDR/
TFDR
A tMCK
2
32tMCK
32tMCK
A tMCK
2
FRDR/
TRDR
tMCK =
32tMCK
A tMCK
2
1
≈ 180ns
5.6448MHz
A tMCK
2
Timing Chart 5-20.
– 93 –
32tMCK
32tMCK
CXD2588Q/R
Example of Driver Circuit
VCC
22k
22k
DRV
RDR
FDR
22k
22k
VEE
Fig. 5-21. Driver Circuit
– 94 –
CXD2588Q/R
§5-17. Servo Status Changes Produced by the LOCK Signal
When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off
in order to prevent SLD free-running.
Setting D6 (LKSW) of $38 to 1 deactivates this function.
In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low.
This enables microcomputer control.
§5-18. Description of Commands and Data Sets
The following description contains portions which convert internal voltages into the values when they are
output externally and describe them as input conversion or output conversion.
Input conversion converts these voltages into the voltages entering input pins before A/D conversion.
Output conversion converts PWM output values into analog voltage values.
– 95 –
CXD2588Q/R
$34
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
KA6
KA5
KA4
KA3
KA2
KA1
KA0
KD7
KD6
KD5
KD4
KD3
KD2
KD1
KD0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
When D15 = 0
KA6 to KA0: Coefficient address
KD7 to KD0: Coefficient data
D15
D14
D13
D12
D11
D10
1
1
1
1
1
0
FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1
—
When D15 = D14 = D13 = D12 = D11 = 1 ($34F)
D10 = 0
FBIAS LIMIT register write
FBL9 to FBL1: Data; data compared with FB9 to 1, FBL9 = MSB.
When using the FBIAS register in counter mode, counter operation stops when the
value of FB9 to 1 matches with FBL9 to 1.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
0
1
FB9
FB8
FB7
FB6
FB5
FB4
FB3
FB2
FB1
—
When D15 = D14 = D13 = D12 = 1 ($34F)
D11 = 0, D10 = 1
FBIAS register write
FB9 to FB1: Data; FB9 is MSB two's complement data.
For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256 × VDD/5 and
FB9 to FB1 = 100000000 to –256/256 × VDD/5 respectively. (VDD: supply voltage)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
1
0
0
TV9
TV8
TV7
TV6
TV5
TV4
TV3
TV2
TV1
TV0
When D15 = D14 = D13 = D12 = 1 ($34F)
D11 = 0, D10 = 0
TRVSC register write
TV9 to TV0: Data; TV9 is MSB two's complement data.
For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256 × VDD/5
and TV9 to TV0 = 1100000000 to –256/256 × VDD/5 respectively. (VDD: supply voltage)
Note) • When the TRVSC register is readout, the data length is 9 bits. At this time, data corresponding to
each bit TV8 to TV0 during external write are readout.
• When reading out internally measured values and then writing these values externally, set TV9 the
same as TV8.
– 96 –
CXD2588Q/R
$35 (preset: $35 58 2D)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FT1
FT0
FS5
FS4
FS3
FS2
FS1
FS0
FTZ
FG6
FG5
FG4
FG3
FG2
FG1
FG0
FT1, FT0, FTZ: Focus search-up speed
Default value: 010 (0.673 × VDD V/s)
Focus drive output conversion
∗
FT1
FT0
FTZ
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
Focus search speed [V/s]
1.35 × VDD
0.673 × VDD
0.449 × VDD
0.336 × VDD
1.79 × VDD
1.08 × VDD
0.897 × VDD
0.769 × VDD
∗: preset, VDD: PWM driver supply voltage
FS5 to FS0:
Focus search limit voltage
Default value: 011000 (±24/64 × VDD, VDD: PWM driver supply voltage)
Focus drive output conversion
FG6 to FG0: AGF convergence gain setting value
Default value: 0101101
$36 (preset: $36 0E 2E)
D15
D14
D13
D12
D11
D10
D9
D8
D7
TDZC DTZC TJ5
TJ4
TJ3
TJ2
TJ1
TJ0 SFJP TG6
TDZC:
D6
D5
D4
D3
D2
D1
D0
TG5
TG4
TG3
TG2
TG1
TG0
Selects the TZC signal for generating the TRKCNCL signal during brake circuit operation.
TDZC = 0: the edge of the HPTZC or STZC signal, whichever has the faster phase, is used.
TDZC = 1: the edge of the HPTZC or STZC signal or the tracking drive signal zero-cross,
whichever has the faster phase, is used. (See §5-12.)
DTZC:
DTZC delay (8.5/4.25µs, when MCK = 128Fs)
Default value: 0 (4.25µs)
TJ5 to TJ0:
Track jump voltage
Default value: 001110 (≈ ±14/64 × VDD, VDD: PWM driver supply voltage)
Tracking drive output conversion
SFJP:
Surf jump mode on/off
The tracking PWM output is made by adding the tracking filter output and TJReg (TJ5 to 0), by
setting D7 to 1 (on)
TG6 to TG0: AGT convergence gain setting value
Default value: 0101110
– 97 –
CXD2588Q/R
$37 (preset: $37 50 BA)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT
FZSH, FZSL: FZC (Focus Zero Cross) slice level
Default value: 01 (1/8 × VDD × 0.4, VDD: supply voltage); FE input conversion
∗
FZSH
FZSL
Slice level
0
0
1
1
0
1
0
1
1/4 × VDD × 0.4
1/8 × VDD × 0.4
1/16 × VDD × 0.4
1/32 × VDD × 0.4
∗: preset
SM5 to SM0: Sled move voltage
Default value: 010000 (≈ ±16/64 × VDD, VDD: PWM driver supply voltage)
Sled drive output conversion
AGS:
AGCNTL self-stop on/off
Default value: 1 (on)
AGJ:
AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms,
when MCK = 128Fs)
Default value: 0 (63ms)
AGGF:
Focus AGCNTL internally generated sine wave amplitude (small/large)
Default value: 1 (large)
AGGT:
Tracking AGCNTL internally generated sine wave amplitude (small/large)
Default value: 1 (large)
FE/TE input conversion
AGGF
0 (small)
1 (large)∗
1/32 × VDD × 0.4
1/16 × VDD × 0.4
AGGT
0 (small)
1 (large)∗
1/16 × VDD × 0.4
1/8 × VDD × 0.4
∗: preset
AGV1:
AGV2:
AGHS:
AGHT:
AGCNTL convergence sensitivity during high sensitivity adjustment; high/low
Default value: 1 (high)
AGCNTL convergence sensitivity during low sensitivity adjustment; high/low
Default value: 0 (low)
AGCNTL high sensitivity adjustment on/off
Default value: 1 (on)
AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs)
Default value: 0 (256ms)
– 98 –
CXD2588Q/R
$38 (preset: $38 00 00)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0
VCLM:
VCLC:
FLM:
FLC0:
RFLM:
RFLC:
AGF:
AGT:
DFSW:
LKSW:
TBLM:
TCLM:
FLC1:
TLC2:
TLC1:
TLC0:
VC level measurement (on/off)
VC level compensation for FCS In register (on/off)
Focus zero level measurement (on/off)
Focus zero level compensation for FZC register (on/off)
RF zero level measurement (on/off)
RF zero level compensation (on/off)
Focus auto gain adjustment (on/off)
Tracking auto gain adjustment (on/off)
Defect disable switch (on/off)
Setting this switch to 1 (on) disables the defect countermeasure circuit.
Lock switch (on/off)
Setting this switch to 1 (on) disables the sled free-running prevention circuit.
Traverse center measurement (on/off)
Tracking zero level measurement (on/off)
Focus zero level compensation for FCS In register (on/off)
Traverse center compensation (on/off)
Tracking zero level compensation (on/off)
VC level compensation for TRK/SLD In register (on/off)
Note) Commands marked with
are accepted every 2.9ms. (when MCK = 128Fs)
All commands are on when set to 1.
– 99 –
CXD2588Q/R
$39
D15
D14
D13
D12
D11
D10
D9
D8
DAC SD6
SD5
SD4
SD3
SD2
SD1
SD0
DAC:
Serial data readout DAC mode (on/off)
SD6 to SD0: Serial readout data select
SD6
1
0
SD5
Readout data
Coefficient RAM data for address = SD5 to SD0
1
Data RAM data for address = SD4 to SD0
SD4
1
0
0
0
Readout data length
8 bits
16 bits
SD3 to SD0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
RF AVRG register
RFDC input signal
FBIAS register
TRVSC register
RFDC envelope (bottom)
RFDC envelope (peak)
RFDC envelope
(peak) – (bottom)
8 bits
8 bits
9 bits
9 bits
8 bits
8 bits
8 bits
$399F
$399E
$399D
$399C
$3993
$3992
$3991
1
1
0
0
0
0
0
1
0
1
0
0
0
0
∗
∗
∗
1
1
0
0
∗
∗
∗
1
0
1
0
VC AVRG register
FE AVRG register
TE AVRG register
FE input signal
TE input signal
SE input signal
VC input signal
9 bits
9 bits
9 bits
8 bits
8 bits
8 bits
8 bits
$398C
$3988
$3984
$3983
$3982
$3981
$3980
Note) Coefficients K40 to K4F cannot be readout.
See the description for SRO1 of $3F concerning readout methods for the above data.
– 100 –
∗: Don't care
CXD2588Q/R
$3A (preset: $3A 00 00)
D15
0
D14
D13
D12
D11
D10
FBON FBSS FBUP FBV1 FBV0
D9
0
D8
D7
D6
D5
D4
TJD0 FPS1 FPS0 TPS1 TPS0
D3
0
D2
D1
D0
SJHD INBK MTI0
FBON:
FBIAS (focus bias) register addition (on/off)
The FBIAS register value is added to the signal loaded into the FCS In register by FBON = 1
(on).
FBSS:
FBIAS (focus bias) register/counter switching
FBSS = 0: register, FBSS = 1: counter.
FBUP:
FBIAS (focus bias) counter up/down operation switching
This performs counter up/down control when FBSS = 1. FBUP = 0: down counter,
FBUP = 1: up counter.
FBV1, FBV0: FBIAS (focus bias) counter voltage switching
The number of FCS BIAS count-up/-down steps per cycle is decided by these bits.
∗
FBV1
FBV0
Number of steps per cycle
0
0
1
0
1
2
1
0
4
1
1
8
The counter changes once for each
sampling cycle of the focus servo filter.
When MCK is 128Fs, the sampling
frequency is 88.2kHz. When converted
to FE input, 1 step is approximately 1/29
× VDD × 0.4, VDD = supply voltage.
∗: preset
TJD0:
This sets the tracking servo filter data RAM to 0 when switched from track jump to servo on
only when SFJP = 1 (during surf jump operation).
FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block.
TPS1, TPS0: Gain setting when transferring data from the tracking filter to the PWM block.
This is effective for increasing the overall gain in order to widen the servo band.
Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However,
6dB, 12dB and 18dB can be selected independently for focus and tracking by setting the
relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00.
∗
FPS1
FPS0
0
0
0
Relative gain
TPS1
TPS0
Relative gain
0dB
0
0
0dB
1
+6dB
0
1
+6dB
1
0
+12dB
1
0
+12dB
1
1
+18dB
1
1
+18dB
∗
∗: preset
SJHD:
INBK:
MTI0:
This holds the tracking filter output at the value when surf jump starts during surf jump.
When INBK = 0 (off), the brake circuit masks the tracking drive signal with TRKCNCL which is
generated by taking the MIRR signal at the TZC edge. When INBK = 1 (on), the tracking filter
input is masked instead of the drive output.
The tracking filter input is masked when the MIRR signal is high by setting MTI0 = 1 (on).
– 101 –
CXD2588Q/R
$3B (preset: $3B E0 50)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT
SFOX, SFO2, SFO1: FOK slice level
Default value: 011 (28/256 × VDD × 0.57, VDD = supply voltage)
RFDC input conversion
∗
SFOX
SFO2
SFO1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Slice level
16/256 × VDD × 0.57
20/256 × VDD × 0.57
24/256 × VDD × 0.57
28/256 × VDD × 0.57
32/256 × VDD × 0.57
40/256 × VDD × 0.57
48/256 × VDD × 0.57
50/256 × VDD × 0.57
∗: preset
– 102 –
D2
D1
D0
0
0
0
CXD2588Q/R
SDF2, SDF1: DFCT slice level
Default value: 10 (0.0313 × VDD × 1.14V)
RFDC input conversion
∗
SDF2
SDF1
0
0
1
1
0
1
0
1
Slice level
0.0156 × VDD × 1.14
0.0234 × VDD × 1.14
0.0313 × VDD × 1.14
0.0391 × VDD × 1.14
∗: preset, VDD: supply voltage
MAX2, MAX1: DFCT maximum time (MCK = 128Fs)
Default value: 00 (no timer limit)
∗
MAX2
MAX1
0
0
1
1
0
1
0
1
DFCT maximum time
No timer limit
2.00ms
2.36
2.72
∗: preset
BTF:
D2V2, D2V1:
Bottom hold double-speed count-up mode for MIRR signal generation
On/off (default: off)
On when set to 1.
Peak hold 2 for DFCT signal generation
Count-down speed setting
Default value: 01 (0.086 × VDD × 1.14V/ms, 44.1kHz)
[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the
operating frequency of the internal counter.
Count-down speed
∗
D2V2
D2V1
0
0
1
1
0
1
0
1
[V/ms]
[kHz]
0.0431 × VDD × 1.14
0.0861 × VDD × 1.14
0.172 × VDD × 1.14
0.344 × VDD × 1.14
22.05
44.1
88.2
176.4
∗: preset, VDD: supply voltage
D1V2, D1V1:
Peak hold 1 for DFCT signal generation
Count-down speed setting
Default value: 01 (0.688 × VDD × 1.14V/ms, 352.8kHz)
[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the
operating frequency of the internal counter.
Count-down speed
∗
D2V2
D2V1
0
0
1
1
0
1
0
1
[V/ms]
[kHz]
0.344 × VDD × 1.14
0.688 × VDD × 1.14
1.38 × VDD × 1.14
2.75 × VDD × 1.14
176.4
352.8
705.6
1411.2
∗: preset, VDD: supply voltage
RINT:
This initializes the initial-state registers of the circuits which generate MIRR, DFCT and FOK.
– 103 –
CXD2588Q/R
$3C (preset: $3C 00 80)
D15
D14
D13
D12
D11
D10
D9
COSS COTS CETZ CETF COT2 COT1 MOT2
D8
0
D7
D6
D5
D4
BTS1 BTS0 MRC1 MRC0
D3
D2
D1
D0
0
0
0
0
COSS, COTS: These select the TZC signal used when generating the COUT signal.
Preset = HPTZC.
COSS
COTS
1
0
0
—
0
1
∗
TZC
STZC
HPTZC
DTZC
∗: preset, —: don't care
STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)
DTZC is the delayed phase STZC. (The delay amount can be selected by D14 of $36.)
HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz.
See §5-13.
CETZ:
The input from the TE pin normally enters the TRK filter and is used to generate the TZC
signal. However, the input from the CE pin can also be used. This function is for the center
error servo.
When CETZ = 0, the TZC signal is generated by using the TE input signal.
When CETZ = 1, the TZC signal is generated by using the CE input signal.
When CETF = 0, the signal input to the TE pin is input to the TRK servo filter.
When CETF = 1, the signal input to the CE pin is input to the TRK servo filter.
CETF:
These commands output the TZC signal.
COT2, COT1: This outputs the TZC signal from the COUT pin.
COT2
COT1
1
0
0
—
1
0
∗
COUT pin output
STZC
HPTZC
COUT
∗: preset, —: don't care
MOT2:
The STZC signal is output from the MIRR pin by setting MOT2 to 1.
These commands set the MIRR signal generation circuit.
BTS1, BTS0: This sets the count-up speed for the bottom hold value of the MIRR generation circuit.
The time per step is approximately 708 ns (when MCK = 128Fs). The preset value is BTS1 = 1,
BTS0 = 0. However, this is valid only when BTF of $3B is 0.
MRC1, MRC0: This sets the minimum pulse width for masking the MIRR signal of the MIRR generation circuit.
As noted in §5-9, the MIRR signal is generated by comparing the waveform obtained by
subtracting the bottom hold value from the peak hold value with the MIRR comparator level.
Strictly speaking, however, for MIRR to become high, these levels must be compared
continuously for a certain time. This sets that time.
The preset value is MRC1 = 0, MRC0 = 0.
BTS1 BTS0
∗
0
0
1
1
0
1
0
1
Number of count-up steps per cycle
1
2
4
8
MRC1 MRC0
0
0
1
1
0
1
0
1
Setting time [µs]
5.669 ∗
11.338
22.675
45.351
∗: preset (when MCK = 128Fs)
– 104 –
CXD2588Q/R
$3D (preset: $3D 00 00)
D15
D14
D13
D12
SFID SFSK THID THSK
D11
0
D10
D9
D8
TLD2 TLD1 TLD0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
SFID:
SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK
filter second-stage output.
When the low-frequency component of the tracking error signal obtained from the RF amplifier
is attenuated, the low frequency can be amplified and input to the SLD servo filter.
SFSK:
Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally
the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain
up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal
transmitted to M00 can be kept uniform by adjusting the K30 value even during the above
switching.
THID:
TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK
filter second-stage output.
When signals other than the tracking error signal from the RF amplifier are input to the SE input
pin, the signal transmitted from the TE pin can be obtained as TRK hold filter input.
THSK:
Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally
the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up
2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted
to M18 can be kept uniform by adjusting the K46 value even during the above switching.
∗ Please refer to § 5-21. Filter Composition, for further information on SFID, SFSK, THID and
THSK commands.
TLD0 to 2:
SLD filter correction turns on and off independently of the TRK filter.
Please refer also to $38 (TLC0 to 2) and Figure 5-3.
TLC2
∗
0
1
TLC1
∗
0
1
TLC0
∗
0
1
TLD2
Traverse center correction
TRK filter
SLD filter
—
OFF
OFF
0
ON
ON
1
ON
OFF
TLD1
Tracking zero level correction
TRK filter
SLD filter
—
OFF
OFF
0
ON
ON
1
ON
OFF
TLD0
VC level correction
TRK filter
SLD filter
—
OFF
OFF
0
ON
ON
1
ON
OFF
∗: preset, — : Don't care
– 105 –
CXD2588Q/R
• Input coefficient inversion when SFID = 1 and THID = 1
The preset coefficients for the TRK filter are negative for input and positive for output. With this, the error input
and servo that outputs reversed phase drive can be hypothesized.
Negative input coefficient
Positive output coefficient
TRK Filter
TE
Negative input coefficient
Positive output coefficient
SLD Filter
SE
Positive input coefficient
Positive output coefficient
TRK Hold Filter
TRK Hold
When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so invert the SLD input
coefficient (K00) code.
For the same reason, when THID = 1, invert the TRK hold input coefficient (K40) code.
Negative input coefficient
TE
Positive output coefficient
TRK Filter
M0D
Positive input coefficient
SE
Positive output coefficient
SLD Filter
Negative input coefficient
TRK Hold
Positive output coefficient
TRK Hold Filter
Please refer also to § 5-20. Filter Composition.
– 106 –
CXD2588Q/R
$3E (preset: $3E 00 00)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD
D5
0
D4
D3
D2
D1
D0
LKIN COIN MDFI MIRI XT1D
F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage
On when set to 1; default = 0.
F1NM: Gain normal
F1DM: Gain down
T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage
On when set to 1; default = 0.
T1NM: Gain normal
T1UM: Gain up
F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage
On when set to 1; default = 0.
Generally, the advance amount of the phase becomes large by partially setting the FCS servo
third-stage filter which is used as the phase compensation filter to double accuracy.
F3NM: Gain normal
F3DM: Gain down
T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage
On when set to 1; default = 0.
Generally, the advance amount of the phase becomes large by partially setting the TRK servo
third-stage filter which is used as the phase compensation filter to double accuracy.
T3NM: Gain normal
T3UM: Gain up
Note) Filter first- and third-stage quasi double accuracy settings can be set individually.
See "Filter Composition" at the end of this specification concerning quasi double accuracy.
DFIS:
FCS hold filter input extraction node selection
0: M05 (Data RAM address 05); default
1: M04 (Data RAM address 04)
This command masks the TLC2 command set by D2 of $38 only when FOK is low.
On when set to 1; default = 0
When 0, the internally generated LOCK signal is output to the LOCK pin. (default)
When 1, the LOCK signal can be input from an external source to the LOCK pin.
When 0, the internally generated COUT signal is output to the COUT pin. (default)
When 1, the COUT signal can be input from an external source to the COUT pin.
The MIRR, DFCT and FOK signals can also be input from an external source.
When 0, the MIRR, DFCT and FOK signals are generated internally. (default)
When 1, the MIRR, DFCT and FOK signals can be input from an external source through the
MIRR, DFCT and FOK pins.
When 0, the MIRR signal is generated internally. (default)
When 1, the MIRR signal can be input from an external source through the MIRR pin.
TLCD:
LKIN:
COIN:
MDFI:
MIRI:
∗
MDFI
MIRI
0
0
MIRR, DFCT and FOK are all generated internally.
0
1
MIRR only is input from an external source.
1
—
MIRR, DFCT and FOK are all input from an external source.
∗: preset, —: don't care
XT1D:
The clock input from FSTI can be used without being frequency-divided as the master clock for
the servo block by setting D0 to 1. This command takes precedence over the XTSL pin, XT2D
and XT4D. See the description of $3F for XT2D and XT4D.
– 107 –
CXD2588Q/R
$3F (preset: $3F 00 00)
D15
0
D14
D13
D12
D11
AGG4 XT4D XT2D
AGG4:
0
D10
D9
D8
DRR2 DRR1 DRR0
D7
0
D6
D5
D4
D3
ASFG FTQ LPAS SRO1
D2
0
D1
D0
AGHF ASOT
This varies the amplitude of the internally generated sine wave using the AGGF and AGGT
commands during AGC.
When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below.
AGGF (MSB)
AGGT (LSB)
0
0
1/64 × VDD × 0.4 [V]
0
1
1/32 × VDD × 0.4
1
0
1/16 × VDD × 0.4
1
1
1/8 × VDD × 0.4
∗
These settings are the same for
both focus auto gain control and
tracking auto gain control.
TE/FE input conversion
∗: preset
XT4D, XT2D: MCK (digital servo master clock) frequency division setting
This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is
generated from the signal input to the FSTI pin. See the description of $3E for XT1D.
∗
XT1D
XT2D
XT4D
Frequency division ratio
0
0
0
According to XTSL
1
—
—
1/1
0
1
—
1/2
0
0
1
1/4
∗: preset, —: don't care
DRR2 to DRR0: Partially clears the Data RAM values (0 write).
The following values are cleared when set to 1 (on) respectively; default = 0
DRR2: M08, M09, M0A
DRR1: M00, M01, M02
DRR0: M00, M01, M02 only when LOCK = low
Note) Set DRR1 and DRR0 on for 50µs or more.
ASFG:
When vibration detection is performed during anti-shock circuit operation, FCS servo filter is
forcibly set to gain normal status.
On when set to 1; default = 0
LPAS:
Built-in analog buffer low-current consumption mode
This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE
input analog buffers by using a single operational amplifier.
On when set to 1; default = 0
Note) When using this mode, first check whether each error signal is properly A/D converted
using the SRO1 and SRO0 commands of $3F.
SRO1:
These commands are used to output various data externally continuously which have been
specified with the $39 command. (However, D15 (DAC) of $39 must be set to 1.)
Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting
these commands to 1 respectively. The default is 0, 0. (no readout)
The output pins for each case are shown below.
SRO1 = 1
SOCK
XOLT
SOUT
LMUT pin
WFCK pin
RMUT pin
(See "Description of Data Readout" on the following page.)
AGHF:
FTQ:
ASOT:
This halves the frequency of the internally generated sine wave during AGC.
The slope of the output during focus search is a quarter of the conventional output slope. ON
when set to 1, default = 0.
The anti-shock signal, which is internally detected, is output from the ATSK pin. Output when
set to 1; default = 0.
Vibration detection when a high signal is output for the anti-shock signal output.
– 108 –
CXD2588Q/R
Description of Data Readout
SOCK
(5.6448MHz)
···
···
···
···
XOLT
(88.2kHz)
SOUT
MSB
···
LSB
MSB
16-bit register for
serial/parallel
conversion
SOUT
···
LSB
16-bit register
for latch
LSB
LSB
To the 7-segment LED
•
•
•
•
•
•
To the 7-segment LED
MSB
MSB
SOCK
CLK
CLK
Data is connected to the 7-segment LED by
4-bits at a time. This enables Hex display
using four 7-segment LEDs.
XOLT
SOUT
Serial data input
D/A
Analog
output
SOCK
Clock input
XOLT
Latch enable input
To an oscilloscope, etc.
Offset adjustment,
gain adjustment
Waveforms can be monitored with an oscilloscope using
a serial input-type D/A converter as shown above.
– 109 –
CXD2588Q/R
§5-19. List of Servo Filter Coefficients
<Coefficient Preset Value Table (1)>
ADDRESS
DATA
K00
K01
K02
K03
K04
K05
K06
K07
K08
K09
K0A
K0B
K0C
K0D
K0E
K0F
E0
81
23
7F
6A
10
14
30
7F
46
81
1C
7F
58
82
7F
SLED INPUT GAIN
SLED LOW BOOST FILTER A-H
SLED LOW BOOST FILTER A-L
SLED LOW BOOST FILTER B-H
SLED LOW BOOST FILTER B-L
SLED OUTPUT GAIN
FOCUS INPUT GAIN
SLED AUTO GAIN
FOCUS HIGH CUT FILTER A
FOCUS HIGH CUT FILTER B
FOCUS LOW BOOST FILTER A-H
FOCUS LOW BOOST FILTER A-L
FOCUS LOW BOOST FILTER B-H
FOCUS LOW BOOST FILTER B-L
FOCUS PHASE COMPENSATE FILTER A
FOCUS DEFECT HOLD GAIN
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K1A
K1B
K1C
K1D
K1E
K1F
4E
32
20
30
80
77
80
77
00
F1
7F
3B
81
44
7F
5E
FOCUS PHASE COMPENSATE FILTER B
FOCUS OUTPUT GAIN
ANTI SHOCK INPUT GAIN
FOCUS AUTO GAIN
HPTZC / Auto Gain HIGH PASS FILTER A
HPTZC / Auto Gain HIGH PASS FILTER B
ANTI SHOCK HIGH PASS FILTER A
HPTZC / Auto Gain LOW PASS FILTER B
Fix∗
TRACKING INPUT GAIN
TRACKING HIGH CUT FILTER A
TRACKING HIGH CUT FILTER B
TRACKING LOW BOOST FILTER A-H
TRACKING LOW BOOST FILTER A-L
TRACKING LOW BOOST FILTER B-H
TRACKING LOW BOOST FILTER B-L
K20
K21
K22
K23
K24
K25
K26
K27
K28
K29
K2A
K2B
K2C
K2D
K2E
K2F
82
44
18
30
7F
46
81
3A
7F
66
82
44
4E
1B
00
00
TRACKING PHASE COMPENSATE FILTER A
TRACKING PHASE COMPENSATE FILTER B
TRACKING OUTPUT GAIN
TRACKING AUTO GAIN
FOCUS GAIN DOWN HIGH CUT FILTER A
FOCUS GAIN DOWN HIGH CUT FILTER B
FOCUS GAIN DOWN LOW BOOST FILTER A-H
FOCUS GAIN DOWN LOW BOOST FILTER A-L
FOCUS GAIN DOWN LOW BOOST FILTER B-H
FOCUS GAIN DOWN LOW BOOST FILTER B-L
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
FOCUS GAIN DOWN DEFECT HOLD GAIN
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
FOCUS GAIN DOWN OUTPUT GAIN
NOT USED
NOT USED
CONTENTS
∗ Fix indicates that normal preset values.
– 110 –
CXD2588Q/R
<Coefficient Preset Value Table (2)>
ADDRESS
DATA
CONTENTS
K30
K31
K32
K33
K34
K35
K36
K37
K38
K39
K3A
K3B
K3C
K3D
K3E
K3F
80
66
00
7F
6E
20
7F
3B
80
44
7F
77
86
0D
57
00
SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.)
ANTI SHOCK LOW PASS FILTER B
NOT USED
ANTI SHOCK HIGH PASS FILTER B-H
ANTI SHOCK HIGH PASS FILTER B-L
ANTI SHOCK FILTER COMPARATE GAIN
TRACKING GAIN UP2 HIGH CUT FILTER A
TRACKING GAIN UP2 HIGH CUT FILTER B
TRACKING GAIN UP2 LOW BOOST FILTER A-H
TRACKING GAIN UP2 LOW BOOST FILTER A-L
TRACKING GAIN UP2 LOW BOOST FILTER B-H
TRACKING GAIN UP2 LOW BOOST FILTER B-L
TRACKING GAIN UP PHASE COMPENSATE FILTER A
TRACKING GAIN UP PHASE COMPENSATE FILTER B
TRACKING GAIN UP OUTPUT GAIN
NOT USED
K40
K41
K42
K43
K44
K45
K46
K47
K48
K49
K4A
K4B
K4C
K4D
K4E
K4F
04
7F
7F
79
17
6D
00
00
02
7F
7F
79
17
54
00
00
TRACKING HOLD FILTER INPUT GAIN
TRACKING HOLD FILTER A-H
TRACKING HOLD FILTER A-L
TRACKING HOLD FILTER B-H
TRACKING HOLD FILTER B-L
TRACKING HOLD FILTER OUTPUT GAIN
TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is accessed with THSK = 1.)
NOT USED
FOCUS HOLD FILTER INPUT GAIN
FOCUS HOLD FILTER A-H
FOCUS HOLD FILTER A-L
FOCUS HOLD FILTER B-H
FOCUS HOLD FILTER B-L
FOCUS HOLD FILTER OUTPUT GAIN
NOT USED
NOT USED
– 111 –
CXD2588Q/R
§5-20. Filter Composition
The internal filter composition is shown below.
K∗∗ and M∗∗ indicate coefficient RAM and Data RAM address values respectively.
FCS Servo Gain Normal fs = 88.2kHz
FCS
Hold Reg 2
FCS
In Reg
DFCT
2–1
K06
AGFON
Sin ROM
K06
K0F
M03
M04
Z–1
M05
Z–1
K08
FCS
AUTO Gain
FCS
Hold Reg 1
M06
Z–1
K09
K0A
K0C
2–7
K11
M07
Z–1
K0E
K10
27
2–7
K0B
K13
FCS PWM
K0D
FCS SRCH
Note) Set the MSB bit of the K0B and K0D coefficients to 0.
FCS Servo Gain Down fs = 88.2kHz
FCS
Hold Reg 2
FCS
In Reg
DFCT
2–1
K06
K2B
M03
M04
Z–1
M05
Z–1
K24
K25
Z–1
K26
K28
2–7
K27
FCS
AUTO Gain
FCS
Hold Reg 1
M06
K2D
M07
K13
Z–1
K2A
K2C
27
2–7
FCS PWM
K29
FCS SRCH
Note) Set the MSB bit of the K27 and K29 coefficients to 0.
– 112 –
CXD2588Q/R
TRK Servo Gain Normal fs = 88.2kHz
TRK
Hold Reg
TRK
In Reg
DFCT
2–1
K19
AGTON
Sin ROM
K19
To SLD Servo, TRK Hold
M0B
M0C
Z–1
M0D
Z–1
K1A
K1B
M0E
Z–1
K1C
K1E
2–7
K1D
TRK
AUTO Gain
K22
M0F
K23
Z–1
K20
K21
27
2–7
TRK PWM
K1F
TRK JMP
Note) Set the MSB bit of the K1D and K1F coefficients to 0.
TRK Servo Gain Up 1 fs = 88.2kHz
TRK
Hold Reg
TRK
In Reg
DFCT
2–1
K19
TRK
AUTO Gain
M0B
M0C
M0E
Z–1
Z–1
Z–1
K3E
M0F
27
K23
TRK PWM
TRK JMP
K1A
K1B
K3C
K3D
– 113 –
CXD2588Q/R
TRK Servo Gain Up 2 fs = 88.2kHz
TRK
Hold Reg
TRK
In Reg
DFCT
2–1
K19
TRK
AUTO Gain
To SLD Servo, TRK Hold
M0B
M0D
M0C
Z–1
Z–1
K36
K37
M0E
Z–1
K38
K3A
2–7
M0F
K3E
Z–1
K3C
K3D
27
2–7
K39
K23
TRK PWM
K3B
TRK JMP
Note) Set the MSB bit of the K39 and K3B coefficients to 0.
SLD Servo fs = 345Hz
TRK SERVO FILTER
Second-stage output
K30
M0D
SLD
In Reg
2–1
TRK
AUTO Gain
SFSK (only when TGUP2 is used)
SFID
M00
M01
Z–1
Z–1
K00
K05
M02
2–7
K07
SLD PWM
SLD MOV
K01
K03
2–7
2–7
K02
K04
Note) Set the MSB bit of the K02 and K04 coefficients to 0.
HPTZC/Auto Gain fs = 88.2kHz
FCS
In Reg
TRK
In Reg
Sin ROM
2–1
Slice
TZC Reg
AGFON
2–1
AGTON
AGFON
M08
M09
Z–1
M0A
Z–1
K14
K15
– 114 –
Z–1
K17
Slice
AUTO Gain
Reg
CXD2588Q/R
Anti Shock fs = 88.2kHz
TRK
In Reg
2–1
K12
M08
M09
M0A
Z–1
Z–1
Z–1
K31
K16
Comp
K35
Anti Shock
Reg
K33
2–7
K34
Note) Set the MSB bit of the K34 coefficient to 0.
The comparator input is 1/16 the maximum amplitude of the comparator input.
AVRG fs = 88.2kHz
2–1
2–7
M08
VC, TE, FE,
RFDC
AVRG Reg
Z–1
TRK Hold fs = 345Hz
TRK SERVO FILTER
Second-stage output
K46
M0D
SLD
In Reg
THSK (only when TGUP2 is used)
THID
2–1
M18
M19
Z–1
Z–1
K40
K41
K45
TRK
Hold Reg
K43
2–7
2–7
K42
K44
Note) Set the MSB bit of the K42 and K44 coefficients to 0.
FCS Hold fs = 345Hz
FCS
Hold Reg 1
K48
M10
M11
Z–1
Z–1
K49
K4D
FCS
Hold Reg 2
K4B
2–7
2–7
K4A
K4C
Note) Set the MSB bit of the K4A and K4C coefficients to 0.
– 115 –
CXD2588Q/R
FCS Servo Gain Normal; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EAXX0)
FCS
Hold Reg 2
DFCT
2–1
FCS
In Reg
K06
AGFON
Sin ROM
K06
K0F
M03
M04
Z–1
M05
Z–1
∗
K0A
2–7
K08
K11
M07
K13
Z–1
∗
7FH
2–7
M06
Z–1
∗
81H
FCS
AUTO Gain
FCS
Hold Reg 1
K0C
2–7
K09
80H
2–7
K0B
K10
27
2–7
K0D
FCS PWM
K0E
FCS SRCH
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K08, K09
and K0E coefficients during quasi double accuracy to 0.
FCS Servo Gain Down; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3E5XX0)
FCS
Hold Reg 2
FCS
In Reg
DFCT
2–1
K06
K2B
M03
Z–1
M04
∗
81H
7FH
2–7
K24
M05
Z–1
∗
Z–1
K26
2–7
K28
2–7
K25
K27
FCS
Hold Reg 1
FCS
AUTO Gain
M06
M07
80H
K2C
27
2–7
K29
K13
Z–1
∗
2–7
K2D
FCS PWM
K2A
FCS SRCH
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25
and K2A coefficients during quasi double accuracy to 0.
– 116 –
CXD2588Q/R
TRK Servo Gain Normal; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EXAX0)
TRK
Hold Reg
DFCT
2–1
TRK
In Reg
K19
AGTON
Sin ROM
K19
TRK
AUTO Gain
M0B
M0C
M0D
Z–1
Z–1
Z–1
∗
K1C
K1E
2–7
K1A
M0F
K23
∗
7FH
2–7
K22
Z–1
∗
81H
M0E
2–7
K1B
K1D
80H
2–7
K21
27
2–7
K1F
TRK PWM
K20
TRK JMP
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K1D and K1F coefficients during normal operation, and of the K1A, K1B
and K20 coefficients during quasi double accuracy to 0.
TRK Servo Gain up 1; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0)
TRK
Hold Reg
TRK
In Reg
DFCT
2–1
K19
TRK
AUTO Gain
M0B
Z–1
∗
M0E
Z–1
Z–1
∗
81H
2–7
K1A
M0C
∗
7FH
80H
K1B
K3C
2–7
K3E
M0F
27
K23
TRK PWM
TRK JMP
K3D
2–7
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0.
– 117 –
CXD2588Q/R
TRK Servo Gain up 2; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0)
TRK
Hold Reg
TRK
In Reg
DFCT
2–1
K19
TRK
AUTO Gain
M0B
Z–1
∗
M0D
Z–1
Z–1
∗
81H
7FH
2–7
K36
M0C
K38
2–7
K3A
2–7
K37
K39
M0E
M0F
80H
K3D
27
2–7
K3B
K23
Z–1
∗
2–7
K3E
TRK PWM
K3C
TRK JMP
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and of the K36, K37
and K3C coefficients during quasi double accuracy to 0.
– 118 –
CXD2588Q/R
§5-21. TRACKING and FOCUS Frequency Response
TRACKING frequency response
40
180°
NORMAL
GAIN UP
30
G
20
0°
φ
10
φ – Phase [degree]
G – Gain [dB]
90°
–90°
0
–180°
–10
2.1
10
100
1K
20K
f – Frequency [Hz]
FOCUS frequency response
40
180°
NORMAL
GAIN DOWN
30
20
G
0°
10
φ
–90°
0
–180°
–10
2.1
10
100
f – Frequency [Hz]
– 119 –
1K
20K
φ – Phase [degree]
G – Gain [dB]
90°
XLON
SPOA
VDD
ATSK
PWMI
VDD
FILI
SCLK
SENS
VCTL
XLAT
AVDD3
CLOK
V16M
VCKI
VPCO
TES2
SBSO
VSS
DOUT
DOUT
VDD
AVDD2
97
100 NC
LMUT
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
AOUT2
96
8
AIN2
95
7
LOUT2
6
AVSS2
93
94
5
AVSS1
92
4
LOUT1
91
3
AIN1
90
2
AOUT1
89
1
AVDD1
88
99
XVSS
LMUT
TFDR 38
XTAO
86
87
RMUT
FFDR 40
TRDR 39
XTAI
85
98
VSS 42
FRDR 41
XVDD
RMUT
VSS 43
EMPHI
83
84
MIRR
COUT
WDCK
COUT 27
WDCK 26
Driver Circuit
+5V
SSTP
SLED
SPDL
GND
FG
TD
TG
FD
LDON
Vcc
GND
RFO
FZC
FE
TE
CE
VC
Application circuits shown are typical examples illustrating the operation of the
devices. Sony cannot assume responsibility for any problems arising out of the use of
these circuits or for any infringement of third party patent and other right due to same.
DFCT
MIRR 28
LOCK
DFCT 29
FOK 30
LOCK 31
MDP 32
SSTP 33
FSTO 34
FSTI 35
SFDR 36
SRDR 37
TES1 45
TEST 44
SQCK
SQSO
EMPH
XRST
EXCK
82
SBSO
SYSM
SQSO
SQCK
XRST
MUTE
DATA
XLAT
CLOK
SENS
SCLK
PWMI
GFS
SCOR
FOK
LDON
VDD
GND
DATA
BCKI
XLON
EMPH
SPOB
XTSL 46
GFS
BCK
C4M
81
SCOR
80
XUGF
XUGF
BCK
PCO
FE 48
FILO
VC 47
CLTV
PCMDI
RFAC
79
AVSS3
SE 49
ASYI
PCMD
BIAS
78
WFCK
WFCK
PCMD
ASYO
NC 50
IGEN
LRCKI
AVDD0
LRCK
ADIO
77
TE
76
AVSS0
XPCK
XPCK
LRCK
CE
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
RFDC
C2PO
C2PO
– 120 –
C4M
§6. Application Circuit
CXD2588Q/R
CXD2588Q/R
Package Outline
Unit: mm
CXD2588Q
100PIN QFP (PLASTIC)
+ 0.1
0.15 – 0.05
15.8 ± 0.4
+ 0.4
14.0 – 0.01
17.9 ± 0.4
23.9 ± 0.4
+ 0.4
20.0 – 0.1
A
0.65
+ 0.35
2.75 – 0.15
±0.12 M
0° to 15°
DETAIL A
0.8 ± 0.2
(16.3)
0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SOLDER PLATING
SONY CODE
QFP-100P-L01
LEAD TREATMENT
EIAJ CODE
∗QFP100-P-1420-A
LEAD MATERIAL
COPPER / 42 ALLOY
PACKAGE WEIGHT
1.4g
JEDEC CODE
CXD2588R
100PIN LQFP (PLASTIC)
16.0 ± 0.2
∗
14.0 ± 0.1
75
51
76
(15.0)
50
0.5 ± 0.2
A
26 (0.22)
100
1
0.5 ± 0.08
+ 0.08
0.18 – 0.03
25
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0° to 10°
0.5 ± 0.2
0.1 ± 0.1
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY/PHENOL RESIN
SONY CODE
LQFP-100P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP100-P-1414-A
LEAD MATERIAL
42 ALLOY
JEDEC CODE
PACKAGE WEIGHT
– 121 –
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