LINER LTC2401CMS 1-/2-channel 24-bit upower no latency adc in msop-10 Datasheet

Final Electrical Specifications
LTC2401/LTC2402
1-/2-Channel 24-Bit µPower
No Latency ∆ΣTMADC in MSOP-10
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DESCRIPTIO
24-Bit ADC in Tiny MSOP-10 Package
1- or 2-Channel Inputs
Automatic Channel Selection (Ping-Pong) (LTC2402)
Zero Scale and Full Scale Set for Reference
and Ground Sensing
4ppm INL, No Missing Codes
4ppm Full-Scale Error
0.5ppm Offset
0.6ppm Noise
Internal Oscillator—No External Components Required
110dB Min, 50Hz/60Hz Notch Filter
Single Conversion Settling Time for
Multiplexed Applications
Reference Input Voltage: 0.1V to VCC
Live Zero—Extended Input Range Accommodates
12.5% Overrange and Underrange
Single Supply 2.7V to 5.5V Operation
Low Supply Current (200µA) and Auto Shutdown
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APPLICATIO S
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Weight Scales
Direct Temperature Measurement
Gas Analyzers
Strain-Gage Transducers
Instrumentation
Data Acquisition
Industrial Process Control
The LTC®2401/LTC2402 are 1- and 2-channel 2.7V to
5.5V micropower 24-bit analog-to-digital converters with
an integrated oscillator, 4ppm INL and 0.6ppm RMS
noise. These ultrasmall devices use delta-sigma technology and a new digital filter architecture that settles in a
single cycle. This eliminates the latency found in conventional ∆Σ converters and simplifies multiplexed applications.
Through a single pin, the LTC2401/LTC2402 can be
configured for better than 110dB rejection at 50Hz or
60Hz ±2%, or can be driven by an external oscillator for
a user defined rejection frequency in the range 1Hz to
120Hz. The internal oscillator requires no external frequency setting components.
These converters accept an external reference voltage
from 0.1V to VCC. With an extended input conversion
range of –12.5% VREF to 112.5% VREF (VREF = FSSET –
ZSSET), the LTC2401/LTC2402 smoothly resolve the offset and overrange problems of preceding sensors or
signal conditioning circuits.
The LTC2401/LTC2402 communicate through a 2- or
3-wire digital interface that is compatible with SPI and
MICROWIRETM protocols.
, LTC and LT are registered trademarks of Linear Technology Corporation.
No Latency ∆Σ is a trademark of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
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January 2000
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FEATURES
TYPICAL APPLICATIO
Pseudo Differential Bridge Digitizer
2.7V TO 5.5V
2.7V TO 5.5V
VCC
1µF
1
VCC
FO
10
LTC2402
REFERENCE VOLTAGE
ZSSET + 0.1V TO VCC
ANALOG
INPUT RANGE
–0.12VREF TO 1.12VREF
(VREF = FSSET – ZSSET)
0V TO FSSET – 100mV
2
3
4
5
FSSET
SCK
CH1
SDO
CH0
CS
ZSSET
GND
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1
2
9
4
8
3-WIRE
SPI INTERFACE
3
7
5
6
24012 TA01
VCC
LTC2402
FSSET
9
SCK
CH0
SDO
CH1
CS
ZSSET
GND
6
FO
8
3-WIRE
SPI INTERFACE
7
10
INTERNAL OSCILLATOR
60Hz REJECTION
24012TA02
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC2401/LTC2402
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ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltage (VCC) to GND .......................– 0.3V to 7V
Analog Input Voltage to GND ....... – 0.3V to (VCC + 0.3V)
Reference Input Voltage to GND .. – 0.3V to (VCC + 0.3V)
Digital Input Voltage to GND ........ – 0.3V to (VCC + 0.3V)
Digital Output Voltage to GND ..... – 0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2401/LTC2402C ................................ 0°C to 70°C
LTC2401/LTC2402I ............................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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PACKAGE/ORDER INFORMATION
ORDER PART NUMBER
ORDER PART NUMBER
TOP VIEW
TOP VIEW
1
2
3
4
5
VCC
FSSET
VIN
NC
ZSSET
10
9
8
7
6
LTC2401CMS
LTC2401IMS
FO
SCK
SDO
CS
GND
MS10 PART MARKING
MS10 PACKAGE
10-LEAD PLASTIC MSOP
VCC
FSSET
CH1
CH0
ZSSET
LTMB
LTMC
TJMAX = 125°C, θJA = 130°C/W
10
9
8
7
6
1
2
3
4
5
LTC2402CMS
LTC2402IMS
FO
SCK
SDO
CS
GND
MS10 PART MARKING
MS10 PACKAGE
10-LEAD PLASTIC MSOP
LTMD
LTME
TJMAX = 125°C, θJA = 130°C/W
Consult factory for Military grade parts.
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CONVERTER CHARACTERISTICS The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VREF = FSSET – ZSSET. (Notes 3, 4)
PARAMETER
CONDITIONS
Resolution
MIN
●
24
24
No Missing Codes Resolution
0.1V ≤ FSSET ≤ VCC, ZSSET = 0V (Note 5)
●
Integral Nonlinearity
FSSET = 2.5V, ZSSET = 0V (Note 6)
FSSET = 5V, ZSSET = 0V (Note 6)
●
●
Offset Error
2.5V ≤ FSSET ≤ VCC, ZSSET = 0V
●
Offset Error Drift
2.5V ≤ FSSET ≤ VCC, ZSSET = 0V
Full-Scale Error
2.5V ≤ FSSET ≤ VCC, ZSSET = 0V
Full-Scale Error Drift
2.5V ≤ FSSET ≤ VCC, ZSSET = 0V
Total Unadjusted Error
FSSET = 2.5V, ZSSET = 0V
FSSET = 5V, ZSSET = 0V
TYP
MAX
Bits
Bits
2
4
10
15
0.5
2
0.01
4
●
UNITS
0.04
ppm of VREF
ppm of VREF
ppm of VREF
ppm of VREF/°C
10
ppm of VREF
ppm of VREF/°C
5
10
ppm of VREF
ppm of VREF
3
µVRMS
Output Noise
VIN = 0V (Note 13)
Normal Mode Rejection 60Hz ±2%
(Note 7)
●
110
130
dB
Normal Mode Rejection 50Hz ±2%
(Note 8)
●
110
130
dB
Power Supply Rejection, DC
FSSET = 2.5V, ZSSET = 0V, VIN = 0V
100
dB
Power Supply Rejection, 60Hz ±2%
FSSET = 2.5V, ZSSET = 0V, VIN = 0V, (Note 7)
110
dB
Power Supply Rejection, 50Hz ±2%
FSSET = 2.5V, ZSSET = 0V, VIN = 0V, (Note 8)
110
dB
2
LTC2401/LTC2402
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A ALOG I PUT A D REFERE CE
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VREF = FSSET – ZSSET. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIN
Input Voltage Range
(Note 14)
FSSET
ZSSET
CS(IN)
Input Sampling Capacitance
CS(REF)
Reference Sampling Capacitance
IIN(LEAK)
Input Leakage Current
CS = VCC
●
–10
1
10
nA
IREF(LEAK)
Reference Leakage Current
VREF = 2.5V, CS = VCC
●
– 12
1
12
nA
●
– 0.125 • VREF
Full-Scale Set Range
●
Zero-Scale Set Range
●
TYP
MAX
UNITS
1.125 • VREF
V
0.1 + ZSSET
VCC
V
0
FSSET – 0.1
V
10
pF
15
pF
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● denotes specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
CS, FO
2.7V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 3.3V
●
MIN
VIL
Low Level Input Voltage
CS, FO
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ VCC ≤ 5.5V
●
VIH
High Level Input Voltage
SCK
2.7V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 3.3V (Note 9)
●
VIL
Low Level Input Voltage
SCK
4.5V ≤ VCC ≤ 5.5V (Note 9)
2.7V ≤ VCC ≤ 5.5V (Note 9)
●
IIN
Digital Input Current
CS, FO
0V ≤ VIN ≤ VCC
●
IIN
Digital Input Current
SCK
0V ≤ VIN ≤ VCC (Note 9)
●
CIN
Digital Input Capacitance
CS, FO
CIN
Digital Input Capacitance
SCK
(Note 9)
VOH
High Level Output Voltage
SDO
IO = – 800µA
●
VOL
Low Level Output Voltage
SDO
IO = 1.6mA
●
VOH
High Level Output Voltage
SCK
IO = – 800µA (Note 10)
●
VOL
Low Level Output Voltage
SCK
IO = 1.6mA (Note 10)
●
IOZ
High-Z Output Leakage
SDO
●
TYP
MAX
UNITS
2.5
2.0
V
V
0.8
0.6
V
V
2.5
2.0
V
V
0.8
0.6
V
V
–10
10
µA
–10
10
µA
10
pF
10
pF
VCC – 0.5
V
0.4
V
VCC – 0.5
V
–10
0.4
V
10
µA
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POWER REQUIRE E TS
The ● denotes specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
VCC
Supply Voltage
ICC
Supply Current
Conversion Mode
Sleep Mode
CONDITIONS
MIN
●
CS = 0V (Note 12)
CS = VCC (Note 12)
●
●
TYP
2.7
200
20
MAX
UNITS
5.5
V
300
30
µA
µA
3
LTC2401/LTC2402
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TI I G CHARACTERISTICS
The ● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
fEOSC
External Oscillator Frequency Range
●
tHEO
External Oscillator High Period
tLEO
External Oscillator Low Period
tCONV
Conversion Time
FO = 0V
FO = VCC
External Oscillator (Note 11)
fISCK
Internal SCK Frequency
Internal Oscillator (Note 10)
External Oscillator (Notes 10, 11)
DISCK
Internal SCK Duty Cycle
(Note 10)
fESCK
External SCK Frequency Range
(Note 9)
●
tLESCK
External SCK Low Period
(Note 9)
●
250
ns
tHESCK
External SCK High Period
(Note 9)
●
250
ns
tDOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 10, 12)
External Oscillator (Notes 10, 11)
●
●
1.64
tDOUT_ESCK
External SCK 32-Bit Data Output Time
(Note 9)
●
t1
CS ↓ to SDO Low Z
●
0
150
ns
t2
CS ↑ to SDO High Z
●
0
150
ns
t3
CS ↓ to SCK ↓
(Note 10)
●
0
150
ns
t4
CS ↓ to SCK ↑
(Note 9)
●
50
tKQMAX
SCK ↓ to SDO Valid
tKQMIN
SDO Hold After SCK ↓
●
15
ns
t5
SCK Set-Up Before CS ↓
●
50
ns
t6
SCK Hold After CS ↓
●
MAX
UNITS
2.56
307.2
kHz
●
0.5
390
µs
●
0.5
390
µs
●
●
●
(Note 5)
TYP
130.66
133.33
136
156.80
160
163.20
20480/fEOSC (in kHz)
19.2
fEOSC/8
45
ms
ms
ms
kHz
kHz
55
%
2000
kHz
1.67
1.70
256/fEOSC (in kHz)
ms
ms
32/fESCK (in kHz)
ms
ns
200
●
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7 to 5.5V unless otherwise specified. Input source
resistance = 0Ω.
Note 4: Internal Conversion Clock source with the FO pin tied
to GND or to VCC or to external conversion clock source with
fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
4
MIN
50
ns
ns
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation, the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: For reference voltage values VREF > 2.5V, the extended input
of – 0.125 • VREF to 1.125 • VREF is limited by the absolute maximum
rating of the Analog Input Voltage pin (Pin 3). For 2.5V < VREF ≤
0.267V + 0.89 • VCC, the input voltage range is – 0.3V to 1.125 • VREF.
For 0.267V + 0.89 • VCC < VREF ≤ VCC, the input voltage range is – 0.3V
to VCC + 0.3V.
LTC2401/LTC2402
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PIN FUNCTIONS
VCC (Pin 1): Positive Supply Voltage. Bypass to GND
(Pin␣ 4) with a 10µF tantalum capacitor in parallel with
0.1µF ceramic capacitor as close to the part as possible.
FSSET (Pin 2): Full-Scale Set Input. This pin defines the
full-scale input value. When VIN = FSSET, the ADC outputs
full scale (FFFFFH). The total reference voltage is
FSSET – ZSSET.
CH0, CH1 (Pins 4, 3): Analog Input Channels. The input
voltage range is – 0.125 • VREF to 1.125 • VREF. For
VREF > 2.5V, the input voltage range may be limited by the
absolute maximum rating of – 0.3V to VCC + 0.3V. Conversions are performed alternately between CH0
and CH1 for the LTC2402. Pin 4 is a No Connect (NC) on
the LTC2401.
ZSSET (Pin 5): Zero-Scale Set Input. This pin defines the
zero-scale input value. When VIN = ZSSET, the ADC
outputs zero scale (00000H).
GND (Pin 6): Ground. Shared pin for analog ground,
digital ground, reference ground and signal ground. Should
be connected directly to a ground plane through a minimum length trace or it should be the single-point-ground
in a single-point grounding system.
CS (Pin 7): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion, the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW on CS wakes up the ADC. A
LOW-to-HIGH transition on this pin disables the SDO
digital output. A LOW-to-HIGH transition on CS during the
Data Output transfer aborts the data transfer and starts a
new conversion.
SDO (Pin 8): Three-State Digital Output. During the data
output period, this pin is used for serial data output. When
the chip select CS is HIGH (CS = VCC), the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin can be used as a conversion status output. The conversion status can be observed by pulling CS
LOW.
SCK (Pin 9): Bidirectional Digital Clock Pin. In the Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the data output
period. In the External Serial Clock Operation mode, SCK
is used as digital input for the external serial interface. An
internal pull-up current source is automatically activated
in Internal Serial Clock Operation mode. The Serial Clock
mode is determined by the level applied to SCK at power
up and the falling edge of CS.
FO (Pin 10): Frequency Control Pin. Digital input that
controls the ADC’s notch frequencies and conversion
time. When the FO pin is connected to VCC (FO = VCC), the
converter uses its internal oscillator and the digital filter’s
first null is located at 50Hz. When the FO pin is connected
to GND (FO = 0V), the converter uses its internal oscillator
and the digital filter’s first null is located at 60Hz. When FO
is driven by an external clock signal with a frequency fEOSC,
the converter uses this signal as its clock and the digital
filter first null is located at a frequency fEOSC/2560.
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LTC2401/LTC2402
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Output Data Format
Table 1. LTC2401/LTC2402 Status Bits
The LTC2401/LTC2402 serial output data stream is 32 bits
long. The first 4 bits represent status information indicating the sign, selected channel, input range and conversion
state. The next 24 bits are the conversion result, MSB first.
The remaining 4 bits are sub LSBs beyond the 24-bit level
that may be included in averaging or discarded without
loss of resolution.
Bit 31 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is LOW if the last conversion
was performed on CH0 and HIGH for CH1.
Bit 29 (third output bit) is the conversion result sign indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0, this
bit is LOW. The sign bit changes state during the zero
code.
Bit 28 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0␣ ≤␣ VIN ≤ VREF, this bit is LOW. If the input is outside the
normal input range, VIN > VREF or VIN < 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
Bit 31
EOC
Bit 30
CH0/CH1
Bit 29
SIG
Bit 28
EXR
VIN > VREF
0
0/1
1
1
0 < VIN ≤ VREF
0
0/1
1
0
0
0/1
1/0
0
0
0/1
0
1
Input Range
VIN =
0+/0 –
VIN < 0
Bit 27 (fifth output bit) is the most significant bit (MSB).
Bits 27-4 are the 24-bit conversion result MSB first.
Bit 4 is the least significant bit (LSB).
Bits 3-0 are sub LSBs below the 24-bit level. Bits 3-0 may
be included in averaging or discarded without loss of
resolution.
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 1. Whenever CS is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device, CS
must first be driven LOW. EOC is seen at the SDO pin of the
device once CS is pulled LOW. EOC changes real time from
HIGH to LOW at the completion of a conversion. This
signal may be used as an interrupt for an external microcontroller. Bit 31 (EOC) can be captured on the first rising
edge of SCK. Bit 30 is shifted out of the device on the first
CS
SDO
BIT 31
BIT 30
BIT 29
BIT 28
BIT 27
BIT 4
EOC
CH0/CH1
SIG
EXT
MSB
LSB24
BIT 0
Hi-Z
SCK
1
SLEEP
2
3
4
5
DATA OUTPUT
27
28
32
CONVERSION
24012 F01
Figure 1. Output Data Timing
6
LTC2401/LTC2402
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falling edge of SCK. The final data bit (Bit 0) is shifted out
on the falling edge of the 31st SCK and may be latched on
the rising edge of the 32nd SCK pulse. On the falling edge
of the 32nd SCK pulse, SDO goes HIGH indicating a new
conversion cycle has been initiated. This bit serves as EOC
(Bit 31) for the next conversion cycle. Table 2 summarizes
the output data format.
As long as the voltage on the VIN pin is maintained within
the – 0.3V to (VCC + 0.3V) absolute maximum operating
range, a conversion result is generated for any input value
from – 0.125 • VREF to 1.125 • VREF. For input voltages
greater than 1.125 • VREF, the conversion result is clamped
to the value corresponding to 1.125 • VREF. For input
voltages below – 0.125 • VREF, the conversion result is
clamped to the value corresponding to – 0.125 • VREF.
through the sensor. The wires connecting the sensor to the
ADC form parasitic resistors RP1 and RP2. The excitation
current also flows through parasitic resistors RP1 and RP2,
as shown in Figure 2. The voltage drop across these
parasitic resistors leads to systematic offset and full-scale
errors.
In order to eliminate the errors associated with these
parasitic resistors, the LTC2401/LTC2402 include a fullscale set input (FSSET) and a zero-scale set input
(ZSSET). As shown in Figure 3, the FSSET pin acts as a zero
input full-scale sense input. Errors due to parasitic resistance RP1 in series with the half-bridge sensor are
RP1
Single Ended Half-Bridge Digitizer
with Reference and Ground Sensing
IEXCITATION
SENSOR
RP2
Sensors convert real world phenomena (temperature,
pressure, gas levels, etc.) into a voltage. Typically, this
voltage is generated by passing an excitation current
+
V
– FULL-SCALE ERROR
+
SENSOR OUTPUT
–
+
V
– OFFSET ERROR
24012 F02
Figure 2. Errors Due to Excitation Currents
Table 2. LTC2401/LTC2402 Output Data Format
Bit 31
EOC
Bit 30
CH SELECT
Bit 29
SIG
Bit 28
EXR
Bit 27
MSB
Bit 26
Bit 25
Bit 24
Bit 23
…
Bit 4
LSB
Bit 3-0
SUB LSBs*
VIN > 9/8 • VREF
0
CH0/CH1
1
1
0
0
0
1
1
...
1
X
9/8 • VREF
0
CH0/CH1
1
1
0
0
0
1
1
...
1
X
VREF + 1LSB
0
CH0/CH1
1
1
0
0
0
0
0
...
0
X
VREF
0
CH0/CH1
1
0
1
1
1
1
1
...
1
X
Input Voltage
3/4VREF + 1LSB
0
CH0/CH1
1
0
1
1
0
0
0
...
0
X
3/4VREF
0
CH0/CH1
1
0
1
0
1
1
1
...
1
X
1/2VREF + 1LSB
0
CH0/CH1
1
0
1
0
0
0
0
...
0
X
1/2VREF
0
CH0/CH1
1
0
0
1
1
1
1
...
1
X
1/4VREF + 1LSB
0
CH0/CH1
1
0
0
1
0
0
0
...
0
X
1/4VREF
0
CH0/CH1
1
0
0
0
1
1
1
...
1
X
0+/0 –
0
CH0/CH1
1/0**
0
0
0
0
0
0
...
0
X
–1LSB
0
CH0/CH1
0
1
1
1
1
1
1
...
1
X
–1/8 • VREF
0
CH0/CH1
0
1
1
1
1
0
0
...
0
X
VIN < –1/8 • VREF
0
CH0/CH1
0
1
1
1
1
0
0
...
0
X
*The sub LSBs are valid conversion results beyond the 24-bit level that may be included in averaging or discarded without loss of resolution.
**The sign bit changes state during the 0 code.
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LTC2401/LTC2402
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APPLICATIO S I FOR ATIO
removed by the FSSET input to the ADC. The absolute fullscale output of the ADC (data out = FFFFFFHEX ) will occur
at VIN = VB = FSSET, see Figure 4. Similarly, the offset errors
due to RP2 are removed by the ground sense input ZSSET.
The absolute zero output of the ADC (data out = 000000HEX)
occurs at VIN = VA = ZSSET. Parasitic resistors RP3 to RP5
have negligible errors due to the 1nA (typ) leakage current
at pins FSSET, ZSSET and VIN. The wide dynamic input
range (– 300mV to 5.3V) and low noise (0.6ppm RMS)
enable the LTC2401 or the LTC2402 to directly digitize the
output of the bridge sensor.
The LTC2402 is ideal for applications requiring continuous monitoring of two input sensors. As shown in
Figure 5, the LTC2402 can monitor both a thermocouple
temperature probe and a cold junction temperature sensor. Absolute temperature measurements can be
performed with a variety of thermocouples using digital
cold junction compensation.
The selection between CH0 and CH1 is automatic. Initially,
after power-up, a conversion is performed on CH0. For
each subsequent conversion, the input channel selection
12.5%
EXTENDED
RANGE
FFFFFH
RP1
IDC = 0
VB
RP3
IDC = 0
IEXCITATION
RP4
IDC = 0
VA
RP2
ADC DATA OUT
1
VCC
RP5
2
3
LTC2401
FSSET
SCK
VIN
SDO
CS
5
6
9
8
7
3-WIRE
SPI INTERFACE
00000H
ZSSET
GND
FO
12.5%
EXTENDED
RANGE
10
ZSSET
24012 F03
FSSET
VIN
24012 F04
Figure 3. Half-Bridge Digitizer with
Zero-Scale and Full-Scale Sense
Figure 4. Transfer Curve with Zero-Scale and Full-Scale Set
2.7V TO 5.5V
LTC2402
1
2
12k
COLD JUNCTION
THERMISTOR
100Ω
3
4
5
+
VCC
FO
FSSET
SCK
CH1
SDO
CH0
CS
ZSSET
GND
10
9
PROCESSOR
8
7
24012 F05
6
–
THERMOCOUPLE
ISOLATION
BARRIER
Figure 5. Isolated Temperature Measurement
8
LTC2401/LTC2402
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APPLICATIO S I FOR ATIO
is alternated. Embedded within the serial data output is a
status bit indicating which channel corresponds to the
conversion result. If the conversion was performed on
CH0, this bit (Bit 30) is LOW and is HIGH if the conversion
was performed on CH1 (see Figure 6).
typically look at a small differential signal sitting on a
large common mode voltage; they need accurate
measurements of the differential signal independent of
the common mode input voltage. Many applications
currently using fully differential analog-to-digital converters for any of the above reasons may migrate to a
pseudo differential conversion using the LTC2402.
There are no extra control or status pins required to
perform the alternating 2-channel measurements. The
LTC2402 only requires two digital signals (SCK and SDO).
This simplification is ideal for isolated temperature measurements or systems where minimal control signals are
available.
Direct Connection to a Full Bridge
The LTC2402 interfaces directly to a 4- or 6-wire bridge, as
shown in Figure 7. Like the LTC2401, the LTC2402 includes a FSSET and a ZSSET for sensing the excitation
voltage directly across the bridge. This eliminates errors
due to excitation currents flowing through parasitic resistors. The LTC2402 also includes two single ended input
channels which can tie directly to the differential output of
the bridge. The two conversion results may be digitally
subtracted yielding the differential result.
Pseudo Differential Applications
Generally, designers choose fully differential topologies
for several reasons. First, the interface to a 4- or 6-wire
bridge is simple (it is a differential output). Second, they
require good rejection of line frequency noise. Third, they
• • •
SCK
SDO
• • •
CH1 DATA OUT
CH0 DATA OUT
24012 F06
EOC
EOC
CH1
CH0
Figure 6. Embedded Selected Channel Indicator
IEXCITATION
5V
1
IDC = 0
2
350Ω
350Ω
3
4
350Ω
VCC
FSSET
LTC2402
9
SCK
CH1
SDO
CH0
CS
350Ω
IDC = 0
5
FO
8
3-WIRE
SPI INTERFACE
7
10
ZSSET
GND
24012 F07
Figure 7. Pseudo Differential Strain Guage Application
9
LTC2401/LTC2402
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APPLICATIO S I FOR ATIO
The LTC2402’s single ended rejection of line frequencies
(±2%) and harmonics is better than 110dB. Since the
device performs two independent single ended conversions each with > 110dB rejection, the overall common
mode and differential rejection is much better than the
80dB rejection typically found in other differential input
delta-sigma converters.
the noise level of the device (3µVRMS) divided by square
root of 2, independent of the common mode input voltage.
Typically, a bridge sensor outputs 2mV/V full scale. With
a 5V excitation, this translates to a full-scale output of
10mV. Divided by the RMS noise of 4.2µV(= 3µV • 1.414),
this circuit yields 2,300 counts with no averaging or
amplification. If more counts are required, several conversions may be averaged (the number of effective counts is
increased by a factor of square root of 2 for each doubling
of averages).
In addition to excellent rejection of line frequency noise,
the LTC2402 also exhibits excellent single ended noise
rejection over a wide range of frequencies due to its 4th
order sinc filter. Each single ended conversion independently rejects high frequency noise (> 60Hz). Care must be
taken to insure noise at frequencies below 15Hz and at
multiples of the ADC sample rate (15,600Hz) are not
present. For this application, it is recommended the
LTC2402 is placed in close proximity to the bridge sensor
in order to reduce the noise injected into the ADC input. By
performing three successive conversions (CH0-CH1-CH0),
the drift and low frequency noise can be measured and
compensated for digitally.
An RTD Temperature Digitizer
RTDs used in remote temperature measurements often
have long lead lengths between the ADC and RTD sensor.
These long lead lengths lead to voltage drops due to
excitation current in the interconnect to the RTD. This
voltage drop can be measured and digitally removed using
the LTC2402 (see Figure 8).
The excitation current (typically 200µA) flows from the
ADC through a long lead length to the remote temperature
sensor (RTD). This current is applied to the RTD, whose
resistance changes as a function of temperature (100Ω to
400Ω for 0°C to 800°C). The same excitation current flows
back to the ADC ground and generates another voltage
drop across the return leads. In order to get an accurate
measurement of the temperature, these voltage drops
must be measured and removed from the conversion
result. Assuming the resistance is approximately the same
The absolute accuracy (less than 10 ppm total error) of the
LTC2402 enables extremely accurate measurement of
small signals sitting on large voltages. Each of the two
pseudo differential measurements performed by the
LTC2402 is absolutely accurate independent of the common mode voltage output from the bridge. The pseudo
differential result obtained from digitally subtracting the
two single ended conversion results is accurate to within
5V
1
2
VCC
FSSET
LTC2402
IEXCITATION = 200µA
+
Pt
VRTD
100Ω
–
4
SCK
CH0
SDO
R1
IEXCITATION = 200µA
IDC = 0
R2
3
5
CS
9
8
7
3-WIRE
SPI INTERFACE
CH1
FO
10
ZSSET
GND
24012 F08
Figure 8. RTD Remote Temperature Measurement
10
LTC2401/LTC2402
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APPLICATIO S I FOR ATIO
for the forward and return paths (R1 = R2), the auxiliary
channel on the LTC2402 can measure this drop. These
errors are then removed with simple digital correction.
The result of the first conversion on CH0 corresponds to
an input voltage of VRTD + R1 • IEXCITATION. The result of the
second conversion (CH1) is – R1 • IEXCITATION. Note, the
LTC2402’s input range is not limited to the supply rails, it
has underrange capabilities. The device’s input range is
– 300mV to VREF + 300mV. Adding the two conversion
results together, the voltage drop across the RTD’s leads
are cancelled and the final result is VRTD.
An Isolated, 24-Bit Data Acquisition System
The LTC1535 is useful for signal isolation. Figure 9 shows
a fully isolated, 24-bit differential input A/D converter
implemented with the LTC1535 and LTC2402. Power on
the isolated side is regulated by an LT1761-5.0 low noise,
low dropout micropower regulator. Its output is suitable
for driving bridge circuits and for ratiometric applications.
During power-up, the LTC2402 becomes active at VCC =
2.3V, while the isolated side of the LTC1535 must wait for
VCC2 to reach its undervoltage lockout threshold of 4.2V.
Below 4.2V, the LTC1535’s driver outputs Y and Z are in a
high impedance state, allowing the 1kΩ pull-down to
define the logic state at SCK. When the LTC2402 first
becomes active, it samples SCK; a logic “0” provided by
the 1kΩ pull-down invokes the external serial clock mode.
In this mode, the LTC2402 is controlled by a single clock
line from the nonisolated side of the barrier, through the
LTC1535’s driver output Y. The entire power-up sequence,
from the time power is applied to VCC1 until the LT1761’s
output has reached 5V, is approximately 1ms.
Data returns to the nonisolated side through the LTC1535’s
receiver at RO. An internal divider on receiver input B sets
a logic threshold of approximately 3.4V at input A, facilitating communications with the LTC2402’s SDO output
without the need for any external components.
1/2 BAT54C
LT1761-5
+
T1
10µF
16V
TANT
IN
OUT
SHDN
BYP
10µF
+
GND
1µF
10µF
10V
TANT
2
+
1/2 BAT54C
RO ST1
RE
DE
DI VCC1
“SDO”
“SCK”
LOGIC 5V
1
10µF
10V
TANT
+
ST2
LTC1535
G1
1
1
VCC2
G2
2
ISOLATION
BARRIER
1
A
B
Y
Z
= LOGIC COMMON
2
10µF
CERAMIC
10µF
10V
TANT
LTC2402
FO
SCK
SDO
CS
GND
1k
2
24012 F09
= FLOATING COMMON
2
2
VCC
FSSET
CH1
CH0
ZSSET
2
T1 = COILTRONICS CTX02-14659
OR SIEMENS B78304-A1477-A3
Figure 9. Complete, Isolated 24-Bit Data Acquisition System
11
LTC2401/LTC2402
W
PACKAGE I FOR ATIO
Dimensions in inches (millimeters) unless otherwise noted.
U
U
MS10 Package
10-Lead Plastic MSOP
(LTC DWG # 05-08-1661)
0.118 ± 0.004*
(3.00 ± 0.102)
10 9 8 7 6
0.118 ± 0.004**
(3.00 ± 0.102)
0.193 ± 0.006
(4.90 ± 0.15)
1 2 3 4 5
0.040 ± 0.006
(1.02 ± 0.15)
0.007
(0.18)
0.034 ± 0.004
(0.86 ± 0.102)
0° – 6° TYP
0.021 ± 0.006
(0.53 ± 0.015)
SEATING
PLANE 0.009
(0.228)
REF
0.0197
(0.50)
BSC
0.006 ± 0.004
(0.15 ± 0.102)
MSOP (MS10) 1098
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1019
Precision Bandgap Reference, 2.5V, 5V
3ppm/°C Drift, 0.05% Max
LT1025
Micropower Thermocouple Cold Junction Compensator
80µA Supply Current, 0.5°C Initial Accuracy
LTC1043
Dual Precision Instrumentation Switched Capacitor
Building Block
Precise Charge, Balanced Switching, Low Power
LTC1050
Precision Chopper Stabilized Op Amp
No External Components 5µV Offset, 1.6µVP-P Noise
LT1236A-5
Precision Bandgap Reference, 5V
0.05% Max, 5ppm/°C Drift
LTC1391
8-Channel Multiplexer
Low RON: 45Ω, Low Charge Injection Serial Interface
LT1460
Micropower Series Reference
0.075% Max, 10ppm/°C Max Drift, 2.5V, 5V and 10V Versions,
MSOP, PDIP, SO-8, SOT-23 and TO-92 Packages
LT1461-2.5
Precision Micropower Voltage Reference
50µA Supply Current, 3ppm/°C Drift
LTC2400
24-Bit, No Latency ∆Σ ADC in SO-8
4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2404/LTC2408
4-/8-Channel, 24-Bit, No Latency ∆Σ ADC
4ppm INL, 10ppm Total Unadjusted Error, 200µA
12
Linear Technology Corporation
24012i LT/TP 0100 4K • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
 LINEAR TECHNOLOGY CORPORATION 2000
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